JPH043596B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device, and particularly to an MIS having a one-transistor, one-capacitor type memory cell.
Dynamic random access memory (RAM)
Regarding.

Background of the Technology A one-transistor, one-capacitor type memory cell, which is advantageous in terms of integration, is mainly used in MIS dynamic RAM. This memory cell is composed of a transistor having a source (or drain) connected to a bit line and a gate connected to a word line, the drain (or source) of this transistor, and an electrode held at a predetermined potential. Equipped with a capacitor. In this case, in a capacitor, if the impurity diffusion layer in the semiconductor substrate that acts as the drain of the transistor is used as one electrode, and the electrode that maintains the above-mentioned predetermined potential is used as its opposite electrode, there is a thin insulation between these two electrodes. A film such as an oxide film (SiO ₂ ) is formed. Information "1" or "0" is represented by whether or not charge is stored in this capacitor.

Normally, a power supply potential V _cc or V _ss is applied to the counter electrode of the capacitor of the above-mentioned memory cell, but recently, a potential of (V _cc −V _ss )/2 was applied to the counter electrode, and The insulating film of the capacitor is made thinner because there is a margin in the withstand voltage.
Therefore, if the capacitance of a capacitor is increased by making the insulating film thinner, for example, if the thickness of the insulating film is halved and the capacitance of the capacitor is doubled, higher integration of semiconductor devices becomes possible. . In other words, it provides an effective means for solving the problem of reduction in cell capacity due to miniaturization of device area.

Prior Art and Problems In a dynamic RAM in which a conventional potential V _cc /2 (V _ss = 0) is applied to the opposing electrode of a capacitor, V _cc is used as a means for generating the above-mentioned potential V _cc /2.
A voltage divider circuit is used to divide the voltage. The resistance value of the voltage divider circuit is set to be quite large, for example, several tens to several hundreds of kilohms, in order to keep the standby current low. Therefore, when the power is turned on, the potential of the opposing electrode of the capacitor of the memory cell rises considerably slower than _Vcc .

On the other hand, the precharging circuit that precharges the bit line potential sets the bit line potential to _Vcc , and the active restore circuit sets the higher bit line potential to Vcc.
After the power is turned on, when _Vcc rises to a predetermined _value , for example 5V, the precharging circuit precharges the bit line potential to _Vcc ,
Moreover, the active restore circuit can also raise the higher bit line potential to _Vcc .

Therefore, when the power is turned on, the potential of the transistor-side electrode of the capacitor may reach _Vcc even though the potential of the opposing electrode of the capacitor is still at a low level compared to _Vcc . As a result, a voltage of approximately _Vcc is applied to the insulating film of the capacitor. However, in this case, the maximum withstand voltage of the capacitor's insulating film is designed to be V _cc /2, so a voltage exceeding the maximum withstand voltage will be applied to the insulating film, and as a result, the insulating film will be destroyed. The problem is that there is a risk that

OBJECT OF THE INVENTION In view of the problems in the conventional type described above, an object of the present invention is to provide a means for quickly following the output of a voltage dividing circuit that determines the potential of the counter electrode when the power supply potential _Vcc rises. The purpose of this invention is to prevent the voltage applied to a capacitor of a memory cell from greatly exceeding a designed applied voltage even when power is turned on, thereby preventing destruction of the capacitor.

Structure of the Invention According to the present invention, in order to achieve the above-mentioned object,
first and second power supply potential supply means; a plurality of word lines; a plurality of bit lines; a one-transistor, one-capacitor type memory cell provided at the intersection of the bit line and the word line; a first resistive voltage dividing means for outputting a potential obtained by resistively dividing the supply potential difference of the power supply potential supply means and applying it to the opposing electrode of the memory cell; and the first resistive voltage dividing means when the first power supply potential rises. Provided is a semiconductor memory device characterized in that it includes a device that temporarily assists the rise of an output potential of a semiconductor memory device.

Embodiments of the Invention Hereinafter, the present invention will be described in comparison with a conventional type with reference to the drawings.

FIG. 1 is a circuit diagram showing a conventional semiconductor memory device. In FIG. 1, memory cell _MC1 is provided at the intersection of word line _WL1 and bit line BL,
Memory cell _C2 is provided at the intersection of word line _WL2 and bit line. Memory cell _MC1 ,
MC ₂ consists of transistors Q ₁ , Q ₂ and capacitor C ₁ ,
It is a one-transistor, one-capacitor type with _C2 . Capacitors C ₁ and C ₂ of memory cells MC ₁ and MC ₂
The nodes N ₁ and N ₂ on the transistor side are formed by an impurity diffusion layer in the semiconductor substrate, while the counter electrode formed by sandwiching the insulating film has a voltage of 1/2 of the power supply voltage V _cc .
is held at a potential of That is, the resistance R ₁ ,
A power potential OP of a voltage dividing circuit VD constituted by R ₂ (R ₁ =R ₂ ) is applied to the counter electrode. This allows the insulating films of the capacitors C ₁ and C ₂ to be guided to increase their capacitance. Also, the power supply voltage V _cc
In order to suppress the current consumption caused by this, the values of the resistors R ₁ and R ₂ are set to several tens to several hundreds of kΩ. Note that other word lines and other bit line pairs also exist, but are not shown. In addition, all the bit lines are connected to one dummy cell in addition to the original memory cell, and these dummy cells are connected to the bit line BL group and the dummy word line provided for each bit line group. Dummy word lines are also omitted from illustration.

The pair of bit lines BL are connected to a precharging circuit PRC, an active restore circuit ARE, and a sense amplifier circuit SA. here,
The precharging circuit PRC and the active restoring circuit ARE are connected to a power supply (voltage V _cc ).

The precharging circuit PRC is a transistor Q ₃ ,
Configured by Q ₄ , in standby mode,
When the clock signal BP goes high (BP>V _cc +
V _th (where V _th is the threshold voltage of the enhancement type transistor), transistors Q ₃ and Q ₄ are both turned on, and therefore the bit lines BL are both turned on.
Precharged to V _cc .

The active restore circuit ARE is composed of transistors Q ₅ to _{Q 8} and capacitors C ₃ and C ₄ . When the clock signal AR goes high in the restore mode (AR > V _cc + V _th ), the capacitors C ₃ ,
The potential of C ₄ increases. At this time, the bit lines BL,
If either of the potentials of BL is higher than _{Vcc −Vth} , transistor _Q5 or _Q8 is cut off,
Therefore, the potential of node N ₃ or N ₄ is V _cc +V _th
That's all. In other words, due to the bootstrap effect, either _the bit line BL or
will return to.

The sense amplifier circuit SA has transistors Q ₉ and Q ₁₀ that constitute a flip-flop, and the sense amplifier circuit SA operates by turning on the transistor Q ₁₁ by turning the clock signal LE high in the sense mode. be exposed.

The operation of the circuit shown in FIG. 1 will be explained with reference to FIG. FIG. 2 shows the state when the power supply voltage _Vcc is applied. That is, at time t ₀ , the power supply voltage
When V _cc is turned on, V _cc rises quickly and at time t ₁
While a predetermined value, say 5V, is reached at
The potential OP of the counter electrode rises very slowly because the resistance value of the voltage divider circuit VD is large.

When the power supply voltage V _cc becomes stable after time t ₂ , a refresh operation is started by the row address strobe signal and ends at time t ₂ . Note that signal control is performed by an external control circuit.

At time _t3 , when the bit line precharging signal BP changes from high to low, the mode shifts from standby mode to selection mode. As a result, for example, the potential of word line WL ₁ rises, transistor Q ₁ is turned on, and memory cell MC ₁ is selected. At this time, if the potential of the node _N1 of the memory cell _MC1 is high, the potential of the bit line BL will not decrease.
On the other hand, the bit line drops to a level intermediate between information "1" and "0" due to a dummy cell (not shown). In this way, a small potential difference is generated between the bit lines BL and BL. Conversely, if node _N1 of memory cell _MC1 has a low potential, the bit line
The potential of BL becomes lower than that of the bit line.

Next, at time _t4 , when the clock signal LE changes from low to high, the mode shifts to the sense mode, and the sense amplifier circuit SA operates. In other words,
The potential difference between bit lines BL and BL is amplified. At this time, the lower potential, that is, the potential of the bit line, drops to zero.

Next, at time _t5 , the clock signal AR becomes 0.
As a _result , the active restore circuit ARE is activated and enters restore mode.
At this time, the higher potential, that is, the potential of the bit line BL returns to _Vcc . Therefore, the potential of node _N1 is also
Return to V _cc .

That is, as shown in FIG. 2, although the potential OP of the counter electrode is still close to 0, the node N ₁
The potential of the capacitor _C1 becomes _Vcc , and a voltage of approximately _Vcc is applied to the insulating film of the capacitor C1.As a result, there is a problem that the insulating film may be destroyed.

In the present invention, since the potential OP of the counter electrode is quickly raised when _Vcc rises, breakdown of the insulating film of the capacitor of the memory cell can be prevented.

FIG. 3 is a circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention. In Figure 3,
A depletion type transistor _Q12 is added as a potential follower circuit _C1 . As a result, the threshold voltage of depletion mode transistor Q ₁₂ becomes V _th
(d), the source potential, that is, the potential of the counter electrode, can rise to |V _th (d)|. The standard value of V _cc
If it is 5V, |V _th (d)| is designed to aim for a value slightly smaller than 2.5V, for example, 2.0V, taking into account margins for variations due to the manufacturing process.

If the size of the transistor _Q12 is made sufficiently large, as shown in FIG. 4, the source potential of the transistor _Q12 , that is, the potential OP of _the counter electrode, will become |V _th )| rises to 2.0V, for example. Therefore, _Vcc (=5V) is not directly applied to the capacitor of the memory cell. Further potential OP by voltage divider circuit VD
gradually rises towards the target of 2.5V,
At this stage transistor _Q12 is cut off. In this way, when the power is turned on, the potential tracking function is achieved as described above, and on the other hand, when the steady state is reached, the transistor _Q12 is cut off and the counter electrode potential OP
is the set value determined only by the ratio of resistors R ₁ and R ₂ ,
Since this is not significantly affected by process variations, the counter electrode potential OP as designed can be easily achieved.

FIG. 5 is a circuit diagram showing a second embodiment of the semiconductor memory device according to the present invention. In Figure 5,
An enhancement type transistor Q ₁₃ and resistors R ₃ and R ₄ are provided as the potential tracking circuit C ₂ . The resistors R ₃ and R ₄ form a voltage dividing circuit VD', and the value thereof is set to be large like the resistors R ₁ and R ₂ of the voltage dividing circuit VD. However, the voltage divider circuit VD
The rise time constant of the output of is basically determined by the resistor R ₁ and the capacitance of the counter electrode, whereas the voltage divider circuit
The rise time constant of the output of VD′ is basically determined by the resistor R ₃ and the gate capacitance of the transistor Q ₁₃ , and is therefore smaller than the rise time constant.
The potential of _N5 rises relatively quickly as shown in FIG. As a result, the potential OP of the counter electrode also rises quickly.

Note that in FIG. 5, the transistor Q ₁₃ is of the enhancement type, so if R ₃ = R ₄ , the potential OP of the counter electrode is a value lower than the potential of the node N ₅ by the threshold voltage of the transistor Q ₁₃ . will be followed. Therefore, in order to compensate for such a voltage drop corresponding to the threshold voltage, resistor R ₃
It is sufficient to set the value of R4 to be smaller than the value of resistor _R4 .
In the steady state after the power supply has been turned on, the potential obtained by subtracting the threshold voltage of the transistor _Q13 from the output potential of the auxiliary voltage divider circuit VD' is as in the previous embodiment.
It is designed to be slightly lower than the steady state output potential of the original voltage divider circuit VD, thereby avoiding the influence of variations in the characteristics of the transistor _Q13 .

FIG. 7 is a circuit diagram showing a third embodiment of the semiconductor memory device according to the present invention. In Figure 7,
Capacitors C ₅ and C ₆ have been added to FIG. 5. In other words, the potential of node _N5 is raised by capacitive coupling between capacitors _C5 and _C6 . In this case, resistors R ₃ , R ₄ act as auxiliary means for capacitors C ₅ , C ₆ . That is, capacitor C ₅ ,
The rise in the potential of node _N5 due to _C6 is stabilized by resistors _R3 and _R4 .

Effects of the Invention As explained above, according to the present invention, the counter electrode potential OP can quickly follow _Vcc , so even if a read operation is performed when the power is turned on, the insulating film of the capacitor is Excessive voltage is not applied, so breakdown of the insulating film can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional semiconductor memory device.
2 is a timing diagram for explaining the circuit operation of the device shown in FIG. 1, FIG. 3 is a circuit diagram showing the first embodiment of the semiconductor device according to the present invention, and FIG. 4 is the device shown in FIG. 3. FIG. 5 is a timing diagram for explaining the circuit operation of the semiconductor memory device according to the present invention.
6 is a timing diagram for explaining the circuit operation of the device in FIG. 5, and FIG. 7 is a circuit diagram showing a third embodiment of the semiconductor memory device according to the present invention. be. _Vcc : first power supply means, _Vss (=0): second power supply means, _WL1 , _WL2 : word line, BL,
BL: bit line, VD: first voltage dividing means, VD': second voltage dividing means, C ₁ , C ₂ , C ₃ , C ₄ : potential following means,
Q ₁₂ : Depletion type transistor, Q ₁₃ : Enhancement type transistor, C ₅ , C ₆ : Capacitor.

Claims (1)

[Scope of Claims] 1. First and second power supply potential supply means, a plurality of word lines, a plurality of bit lines, a one-transistor, one-capacitor type memory cell provided at the intersection of the bit line and the word line, a first resistive voltage dividing means for outputting a potential obtained by resistively dividing the supply potential difference between the first and second power supply potential supply means and applying it to the opposing electrode of the memory cell; A semiconductor memory device comprising means for temporarily assisting the rise of the output potential of the first resistance voltage dividing means. 2. The potential following means includes a depletion type transistor, and the transistor has a drain connected to the first power supply potential supply means, a gate connected to the second power supply potential supply means, and a depletion type transistor that has a drain connected to the first power supply potential supply means, and a gate connected to the second power supply potential supply means. The semiconductor memory device according to claim 1, having a source connected to the output of the resistive voltage dividing means. 3. The potential following means is an enhancement type transistor having a drain connected to the first power supply potential supply means and a source connected to the output of the first resistive voltage dividing means, and the first,
2. The semiconductor memory device according to claim 1, further comprising second resistive voltage dividing means for dividing the supply potential difference of the second power supply potential supply means and applying the divided voltage to the gate of the enhancement mode transistor. 4. The method according to claim 3, wherein the second resistive voltage dividing means comprises at least two resistors connected in series, and the potential following means further comprises a capacitor connected in parallel to each of the resistors. Semiconductor storage device. 5. The second resistive voltage dividing means includes at least two resistors connected in series, and the potential following means is connected to one of the resistors connected to the second power supply potential supply means, and the potential following means is connected to one of the resistors connected to the second power supply potential supply means. 4. The semiconductor memory device according to claim 3, further comprising threshold compensation means for compensating the threshold voltage of the enhancement mode transistor.