JPH0436506B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal noise reduction circuit, and in particular has a one-field delay circuit in a feedback path with a band narrower than the input video signal band, and utilizes field correlation. The present invention relates to a video signal noise reduction circuit that reduces noise in a video signal.

Conventional technology Conventionally, in devices for reproducing video signals recorded on recording media such as magnetic tapes, in order to reduce the noise contained in the reproduced video signals, especially in consumer equipment, it has been necessary to perform recording with the same fidelity as in broadcasting equipment. Since reproduction is not required, a circuit is used that reduces noise in the reproduced video signal within a visually permissible range. Various such noise reduction circuits have been proposed in the past, and one of them, as shown in FIG. 1, is a so-called cyclic field-correlated noise reducer that has a one-field delay circuit in the feedback path. The noise reduction circuit was installed.

In FIG. 1, a reproduced video signal (for example, a luminance signal) that has been reproduced from, for example, a magnetic tape and then demodulated is supplied to subtraction circuits 2 and 3 via an input terminal 1, respectively. The reproduced video signal taken out from the subtraction circuit 2 is supplied to a 1-field delay circuit 4, where it is delayed for a period of 1 field or a natural number times the horizontal scanning period very close to 1 field, and then sent to the subtraction circuit 3. Supplied. The subtraction circuit 3 performs a subtraction operation of subtracting the output signal of the one-field delay circuit 4 from the reproduced video signal from the input terminal 1, and supplies the obtained signal to the subtraction circuit 2 through a limiter 5 and a coefficient circuit 6, respectively. . Here, while a video signal generally has so-called field correlation in which video information at one field interval is extremely close to each other, noise does not have such field correlation.

Therefore, the output signal of the subtraction circuit 3 is mainly noise having no field correlation. Limituta 5
limits the amplitude of the signal mainly composed of this noise to about the peak-to-peak level of the noise. Also,
The coefficient circuit 6 is a circuit that performs necessary weighting. The subtraction circuit 2 subtracts the output signal of the coefficient circuit 6 from the reproduced video signal from the input terminal 1, substantially cancels out the noise in the reproduced video signal with the output signal of the coefficient circuit 6, and returns the signal to the 1-field delay circuit 4. On the other hand, it is output to the output terminal 7. In this way, the input reproduced video signal is extracted from the output terminal 7 with its noise reduced.

Conventionally, the one-field delay circuit 4 in the above noise reduction circuit is a digital memory circuit or a charge circuit.
Analog shift registers using charge transfer elements such as coupled devices (CCD) are used, but in either case, there are problems such as high cost due to the need to secure the required transmission band for the reproduced video signal. It was hot. That is, when a digital memory circuit is used as the one-field delay circuit 4, the conventional structure is as shown in FIG. In the figure, a reproduced video signal to be output to the output terminal 7 in FIG. 1 is input to the input terminal 8. Assuming that the required transmission band of this reproduced video signal is 0 to 3 MHz, the input reproduced video signal is supplied to the A/D converter 10 through a low-pass filter 9 with an upper cutoff frequency of about 3 MHz, and here the clock pulse from the control circuit 11 is applied. A/D conversion is performed based on. Here, since the transmission band is 0 to 3 MHz, the sampling frequency of the reproduced video signal must be 6 MHz or more according to Nyquist's sampling theorem.

Therefore, if the input reproduced video signal is sampled at a frequency twice the color subcarrier frequency, the number of sample points per horizontal scanning period (1H) is:
In the case of NTSC system, the sampling frequency is approximately
Since it is 7.16MHz and the horizontal scanning frequency is 15.625KHz, it is approximately 455 (≒7160/15.625). Therefore,
The number of sample points per field is 1 to 455 above.
It can be determined by multiplying by the number of scanning lines of the field, 525/2, and becomes approximately 119.4×10 ³ . Now, assuming that the number of quantization bits per sample point is 8 bits, an 8-bit digital signal is extracted from the A/D converter 10 and supplied to a dynamic random access memory (DRAM) 12.

The DRAM 12 writes the above-mentioned 8-bit digital signal based on the read/write signal, write or read clock pulse, address signal, etc. from the control circuit 11, reads out the data one field before, and sends it to the D/A converter 13.
Output to. Based on the 7.16 MHz clock pulse from the control circuit 11, the D/A converter 13 converts the analog video signal obtained by D/A converting the digital signal read out from the DRAM 12 with a one-field delay, at the upper limit cutoff frequency. The signal is output to the output terminal 15 through a 3MHz low-pass filter 14.

Here, as mentioned above, the digital signal supplied to the DRAM 12 has 8 bits of quantization bits per sample point, and the number of sample points for one field is approximately 119.4×10 ³ , so it is 119.4 ×8
×10 ^3- bit storage capacity is required, which is 64k
This storage capacity requires 16 bits of DRAM. This makes the circuit extremely expensive.

Furthermore, when an analog shift register as shown in FIG. 3 is used as the 1-field delay circuit 4, this analog shift register is connected to the input terminal 16.
The input horizontal transfer register 17 is shifted to the right (horizontal transfer) by horizontal transfer clock pulses φ _H and _H of opposite phase from the input terminals 18 and 19. The horizontal transfer register 17 consists of n cells (n is a natural number) of the CCD, and when n horizontal transfer clock pulses are received within 1H, the 1H of the reproduced video signal is
The video information (sample information) for the number of times is written to the full nth stage. After that, input terminals 20, 21
The vertical transfer clock pulses φv, which are opposite in phase to each other,
Since φv is input once within the horizontal blanking period,
The n pieces of sample information accumulated in the above n cells are transferred in parallel to the vertical transfer registers 22 ₁ to 2 of n columns and m stages.
2n first stages and are stored there.

The vertical transfer registers 22 ₁ to 22n have m pieces in each column.
It consists of CCD cells, and performs vertical transfer one stage at a time in sequence based on a clock pulse φv, which comes in once every 1H, and is input to the output horizontal transfer register 23 by m vertical transfers. The horizontal transfer register 23 consists of CCD cells arranged in 1 row and n columns, and outputs input signals in series to the output terminal 24 within 1H in response to the horizontal transfer clock pulses φ _H and _H. As a result, a reproduced video signal obtained by delaying the input reproduced video signal of the input terminal 16 by (m+1)H is outputted to the output terminal 24. Therefore, the vertical transfer register 22
By selecting the number m of each stage from ₁ to 22n to 261 or 262, a video signal output delayed by one field (262H or 263H) can be obtained.

Here, as mentioned above, the number of sample points per 1H is 455
Therefore, the horizontal transfer registers 17, 23
and each of the vertical transfer registers 22 ₁ to 22n is 455
Consists of columns of cells. For this reason, when the above-mentioned analog shift register is made into an integrated circuit (IC), the chip area is large and it is expensive.
There were some things that could not be done.

Therefore, the present applicant filed a patent application (1) filed on the same date as the present patent application (title of invention: "Video signal noise reduction circuit").
proposed a noise reduction circuit in which the band of the one-field delay circuit was selected to be narrower than the transmission band of the input video signal. According to the proposed noise reduction circuit, it is possible to construct a one-field delay circuit at low cost, and even when an analog shift register is used, it can be integrated into an IC with one chip, and furthermore, it is possible to construct a high-frequency circuit with a small amplitude. It also has a component noise reduction effect (so-called crispning effect).

Problems to be Solved by the Invention However, since the noise reduction circuit proposed above also attenuates small-amplitude high-frequency components, the resolution of small-amplitude video signals deteriorates. This itself has little effect on the reproduced image, but for example, if this noise reduction circuit is connected to a VTR that already has a circuit that performs crispinig,
Crispinning is performed twice, resulting in a problem that the resolution of the small amplitude video signal is significantly reduced.

Therefore, the present invention solves the above problems by providing a filter circuit that provides the same frequency characteristics as the one-field delay circuit to the input video signal to be subtracted from the output signal of the narrow-band one-field delay circuit. The purpose of this invention is to provide a video signal noise reduction circuit that solves the problem.

Means for Solving the Problems The present invention provides a delay circuit that outputs a delayed video signal obtained by delaying an output video signal for one field period or a natural number multiple of a horizontal scanning period very close to the field period. a cyclic field correlation noise reduction circuit inserted into the circuit, which has the same frequency characteristics as the low frequency characteristics of the delay circuit, and imparts to the input video signal the same frequency characteristics as the delayed video signal of the delay circuit. a low-pass filter circuit; a first subtraction circuit that outputs a difference signal obtained by subtracting the filter output video signal from the low-pass filter circuit and the delayed video signal of the delay circuit; and the first subtraction circuit. an amplitude limiting weighting circuit that outputs an amplitude limiting weighted signal obtained by performing amplitude limiting and weighting on an error signal from the amplitude limiting weighting circuit; and subtracting the amplitude limiting weighting signal from the amplitude limiting weighting circuit and the input video signal. and a second subtraction circuit that outputs the output video signal obtained by the input video signal, and the band of the delay circuit is selected to be narrower than the transmission band of the input video signal. This will be explained with reference to Figure 4 and the following drawings.

Embodiment FIG. 4 shows a block diagram of an embodiment of the circuit of the present invention. In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. In FIG. 4, the reproduced video signal taken out from the subtraction circuit 2 is supplied to a 1-field delay circuit 26, where it is delayed by 1 field (or by a natural number times the horizontal scanning period very close to 1 field), and ,
After the band is limited, it is supplied to the subtraction circuit 3. 1
The field delay circuit 26 has a configuration as shown in FIG. 5, for example. First, the configuration and operation of this one-field delay circuit 26 will be explained. Fifth
In the figure, a baseband reproduced video signal inputted to the input terminal 8 and demodulated after being reproduced from, for example, a magnetic tape is supplied to an A/D converter 29 through a low-pass filter 28 with an upper cutoff frequency of 1.5 MHz. ,
After being sampled based on a clock pulse (sampling pulse) from the control circuit 30, it is converted into a digital signal having, for example, 8 bits of quantization bits per sampling point. Here, the repetition frequency of the above sampling pulse
fs is selected to be a frequency equal to the color subcarrier frequency (3.58MHz in the case of the NTSC system). Therefore, the number of sample points per 1H of this digital signal is
227 or 228 pieces.

The output digital signal of the A/D converter 29 is
The data is supplied to the DRAM 31, where it is written based on read/write signals, write or read clock pulses, address signals, etc. from the control circuit 30. Here, in this embodiment, the sampling frequency fs is selected to be 1/2 the sampling frequency of the conventional circuit shown in FIG. So the storage capacity of DRAM31 is
It will only require half of the DRAM of 12, which means 8
It can be configured with 64k bit DRAM.
Under the control of the output signal of the control circuit 30, the DRAM 31 reads out the stored digital signal of one field before and supplies it to the D/A converter 32.
The D/A converter 32 is applied with a clock pulse having a repetition frequency 1/2 times that of the conventional one from the control circuit 30, and converts the output digital signal of the DRAM 31 into an analog signal. This analog signal passes through a low-pass filter 33 with an upper limit cutoff frequency of 1.5 MHz and is output as a reproduced video signal delayed by one field from an output terminal 15 to a subtraction circuit 3 shown in FIG. 4.

In this embodiment, the storage capacity of DRAM 31 is smaller than that of the conventional one.
8 pieces of 64k bits, 1/2 of that of DRAM12
Since it can be configured with DRAM, the circuit configuration can be made inexpensive. Also, when an analog shift register as shown in FIG. 3 is used as the 1-field delay circuit 26, the register 17 ,22 ₁
Since the number n of each of the columns 22n and 23 can be reduced to 1/2 of the conventional number, the chip area of the IC can be reduced and the IC can be manufactured at low cost.

Therefore, the 1-field delay circuit 26 reduces the sampling frequency to 1/2 that of the conventional circuit 4 as described above.
Since the frequency is selected to be twice as high, only the signal component of 0 to 1.5 MHz, which is about half of the transmission band of the reproduced video signal from 0 to 3 MHz, can be transmitted, and the frequency characteristics of the 1-field delay circuit 26 are as shown in FIG. become.

Returning to FIG. 4 again, the reproduced video signal input to the input terminal 1 is supplied to the subtraction circuit 2, and is also supplied to the subtraction circuit 3 through the filter circuit 27. The frequency characteristic of the filter circuit 27 is 1
The frequency characteristics are selected to be substantially the same as the frequency characteristics of the field delay circuit 26 shown in FIG. Therefore, the subtraction circuit 3 can perform the operation of subtracting the substantially same narrowband signal component of the previous field taken out from the one-field delay circuit 26 from the narrowband signal component of the current field taken out from the filter circuit 27. Outputs the signal. That is, from the subtraction circuit 3, the sixth
Signal components and noise having no field correlation within the band shown in the figure are extracted and supplied to the subtraction circuit 2 through a limiter 5 and a coefficient circuit 6, respectively.

As a result, assuming that the reproduced video signal that enters the input terminal 1 has a band of 0 to approximately 3 MHz as shown in Figure 7A, and that white noise is superimposed on this as shown in Figure 7A. , subtraction circuit 2
As shown in Figure 7B, the frequency spectrum of the reproduced video signal extracted from It will be reduced. Note that the noise mixed into the reproduced video signal is not actually as shown in FIG. 7A, but for convenience of explanation, the case where there is white noise and it is mixed is shown here. .

By the way, if it is assumed that a reproduced video signal with perfect field correlation is input to input terminal 1 in FIG. 4, the noise reduction circuit shown in FIG.
It is considered to be equivalent to a circuit with a configuration as shown in the figure. In FIG. 8, the same components as those in FIG. 4 are designated by the same reference numerals, and their explanations will be omitted. Since the frequency characteristics of the 1-field delay circuit 26 are shown in FIG. 6, as shown in FIG. Terminal 1 and subtraction circuit 3
It is equivalent to a circuit provided between

Therefore, if the filter circuit 27 were not provided, small amplitude components below the limiting level of the limiter 5 of 1.5 MHz or higher would be supplied to the subtraction circuit 2 via the limiter 5 and the coefficient circuit 6. Therefore, small amplitude components of 1.5 MHz or more in the input reproduced video signal are subtracted by the subtraction circuit 2. Therefore, the reproduced video signal is extracted from the subtraction circuit 2 with its small amplitude components of 1.5 MHz or more reduced. Since most of the noise in the reproduced video signal consists of high frequency and small amplitude components, this reduces the noise. This is so-called crispspinning. With crisp pinning, small amplitude and high frequency components of the signal are also lost, so the resolution of small amplitudes in the horizontal direction of the screen is reduced.

In this embodiment, the filter circuit 27 having substantially the same frequency characteristics as the one-field delay circuit 26 is provided on the transmission path of the input reproduced video signal supplied to the subtraction circuit 3. Both input signals are in approximately the same band,
If there is perfect field correlation, subtraction circuit 3
The output signal of is approximately zero. Therefore, in this case, there is almost no signal supplied from the coefficient circuit 6 to the subtraction circuit 2, so that the above-described crispening effect can be avoided. Therefore, according to this embodiment, the resolution of small amplitudes in the horizontal direction of the screen does not deteriorate. In addition, the above-mentioned Crispinning effect is
This also occurs when the input reproduced video signal does not have perfect field correlation, and in this case as well, the above-mentioned crispinning effect can be eliminated.

Note that when an analog shift register having the configuration shown in FIG. 3 is used as the 1-field delay circuit 26, the number of stages (number of rows) of the vertical transfer registers 22 ₁ to 22n is a natural number, so the horizontal scanning period is Only a natural number times the delay time can be obtained, and one field period of 262.5H is accurate for input playback video signals of both 525 and 625 scanning lines.
Or a delay of 312.5H cannot be obtained. However, by selecting the delay time to be a natural number times the horizontal scanning period, which is very close to this one field period,
The desired noise reduction operation can be performed with almost no practical problems.

Effects As described above, according to the present invention, the one-field delay circuit and the input video signal to be subtracted from the output signal of the one-field delay circuit in the cyclic noise reduction processing circuit using field correlation. Since a filter circuit that provides approximately the same frequency characteristics is provided, even when the above-mentioned one-field delay circuit is selected to have a narrower band than the transmission band of the input video signal, the small amplitude and high frequency components of the input video signal can be attenuated. Therefore, the resolution of small-amplitude video signals is not degraded, and especially when the circuit of the present invention is connected to a video signal reproducing device such as a VTR that has a so-called crisp-spinning circuit in its reproduction system, Since the amount of attenuation of small-amplitude, high-frequency components of the video signal can be reduced only to the circuit that performs the above-mentioned crispinning, deterioration in resolution of the small-amplitude video signal can be minimized.

Furthermore, since the present invention is a cyclic field correlation noise reduction circuit, it is possible to achieve greater noise reduction compared to a non-cyclic field correlation noise reduction circuit.

Furthermore, a low-pass filter circuit having the same frequency characteristics as the low-frequency characteristic of the delay circuit inserted in the feedback path is provided, and the band of this delay circuit is selected to be narrower than the transmission band of the input video signal. According to
Both input signals supplied to the first subtraction circuit are signals of the same band, and if there is perfect field correlation, the difference signal output from the first subtraction circuit will be zero, thereby Since the small amplitude, high frequency components in the input signal are not lost from the output video signal, the resolution of small amplitudes in the horizontal direction of the screen can be increased compared to conventional systems.

[Brief explanation of drawings]

Fig. 1 is a block system diagram showing an example of a conventional circuit, Fig. 2 is a block system diagram showing an example of a 1-field delay circuit in the block system shown in Fig. 1, and Fig. 3 is another example of a 1-field delay circuit. 4 is a block system diagram showing an embodiment of the circuit of the present invention, and FIG. 5 is a block system diagram showing an embodiment of the 1-field delay circuit in the block system shown in FIG. 4. 6 shows an example of the frequency characteristics of the circuit shown in FIG. 5, and FIGS. 7A and 7B show examples of the frequency spectra of the input reproduced video signal and output video signal of the block system shown in FIG. 4, respectively. 8 is a block system diagram showing an equivalent circuit of the circuit shown in FIG. 4 when the input reproduced video signal has perfect field correlation. 1, 8, 16...Playback video signal input terminal, 4,
26...1 field delay circuit, 7, 15, 24
...Playback video signal output terminal, 10,29...A/
D converter, 11, 30...control circuit, 1
2, 31...Dynamic random access memory (DRAM), 13, 32...D/A converter, 27...Filter circuit, 35...Low pass filter.

Claims (1)

[Claims] 1. A cyclic field in which a delay circuit is inserted in the feedback path to output a delayed video signal obtained by delaying an output video signal for a field period or a period that is a natural number multiple of a horizontal scanning period very close to the field period. A low-pass filter that is a correlated noise reduction circuit and has the same frequency characteristics as the low-frequency characteristics of the delay circuit and gives the input video signal the same frequency characteristics as the delayed video signal of the delay circuit. a first subtraction circuit that outputs a difference signal obtained by subtracting the filter output video signal from the low-pass filter circuit and the delayed video signal of the delay circuit; an amplitude limiting weighting circuit that outputs an amplitude limiting weighted signal obtained by performing amplitude limiting and weighting on the error signal; and an amplitude limiting weighting circuit that outputs an amplitude limiting weighted signal obtained by performing amplitude limiting and weighting on the error signal; a second subtraction circuit that outputs the output video signal, the delay circuit having a band narrower than a transmission band of the input video signal.