JPH0441398B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an analog data acquisition circuit that collects data by A/D converting an input analog signal, and particularly relates to an analog data acquisition circuit that collects data by A/D converting an input analog signal. The present invention relates to an analog data acquisition circuit equipped with means for suppressing an increase in noise components when the rate is lowered.

[Conventional technology]

In electrocardiographs, blood flow meters, and the like, for example, when the time axis unit on the monitor display or the paper feed speed of the recorder is changed, the sampling rate of the analog input signal is also changed accordingly. For example, if the paper feed speed of the recorder is halved, the recording density of the signal waveform will be T/cm, as shown in Figure 2.
Since the data acquisition rate of the analog input signal is doubled from 2T/cm to 2T/cm, the data acquisition rate of the analog input signal is halved.

Figure 3 shows the general configuration of an analog data acquisition circuit used in such a device, where 1 is a sensor, 2 is a preamplifier, and 3 is an A/D.
A converter, 4 a processing device, 5 a monitor display, and 6 a recorder.

A weak analog signal output from the sensor 1 is amplified by a preamplifier 2 and input to an A/D converter 3. When the data request signal given from the processing device 4 turns ON, the A/D converter 3
By controlling the built-in sample and hold circuit,
The instantaneous value of the analog signal at that point in time is held, converted from analog to digital, and output to the processing device 4 as digital data.

By the way, the maximum data collection rate (throughput rate) is the conversion time of the A/D converter 3, Tc.
Then, the throughput rate = 1/(Tc) (Hz), and the upper limit frequency of the reproducible analog signal is half the data acquisition rate according to the sampling theorem. Therefore, as shown in FIG. 4, when the data acquisition rate of the device is variable, the frequency band of the preamplifier 2 is set to a value f _n / that corresponds to the upper limit value f _n .
Set to 2.

The processing device 4 determines a data collection rate according to the data output speed to the monitor display 5 and the recorder 6, and transmits a data request signal to the A/D converter 3 at a period based on the data collection rate. As mentioned above, the characteristics of the preamplifier 2 are determined to have the upper limit of the variable range of the data acquisition rate, that is, the band that is half the data acquisition rate, and therefore, the data acquisition rate is set to the upper limit. If so, even if the input analog signal contains noise with a frequency higher than the band of the preamplifier, it will not be converted by the A/D converter.

[Problem that the invention seeks to solve]

In a device where the data acquisition rate of the data acquisition circuit is variable, when the data acquisition rate is set to a low value, the preamplifier band becomes wider than the upper limit frequency that can be reproduced at that data acquisition rate due to the sampling theorem. High frequency components exceeding the band are A/D
It is converted by the converter and included as noise in the collected data.

Therefore, when changing the data acquisition rate, the band characteristics of the preamplifier are also changed in the same way, but in that case, it is necessary to provide a mechanism to switch the time constant circuit in the preamplifier, and an IC etc. There was a problem that it was not suitable for miniaturizing the circuit due to the method.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention has the following features:
The A/D conversion rate is fixed at the upper limit of the data collection rate, and when the data collection rate is lowered, the number of A/D conversion result data corresponding to the rate at which the data collection rate was lowered is averaged, that is, digital data By performing this smoothing, noise input due to the band of the preamplifier being too wide for the data acquisition rate is suppressed. The configuration of the present invention based on this includes a preamplifier that amplifies an input analog signal, an A/D converter connected to the preamplifier, and a fixed sampling pulse source that drives the A/D converter. an adder that accumulates the A/D conversion results output from the A/D converter;
a counter that holds the number of times the A/D conversion results have been accumulated; and a signal means with a variable repetition frequency that is transmitted in order to clear the adder and the counter and control the A/D conversion result accumulation circuit. and a divider for dividing the accumulation result output from the adder by the number of accumulations, and an output means for outputting the division result output from the divider as data. This is a characteristic feature.

〔Example〕

The details of the present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram of a data acquisition circuit according to an embodiment of the present invention. In FIG. 1, 7 is a preamplifier, 8 is an A/D converter, 9 is a sampling pulse generator, 10 is an adder, 11 is a latch circuit, 1
2 is a counter, 13 is a divider, and 14 is a latch circuit. Further, e _i represents an input analog signal, e _i ′ represents the amplified e _i , Ps represents a sampling pulse, DREQ represents a data request signal, and DATA represents output data.

The preamplifier 7 amplifies the input analog signal e _i and outputs it to the A/D converter 8 as e _i '. The band characteristics of the preamplifier are designed to be below the reproducible frequency determined by the upper limit value of the variable data acquisition rate of this data acquisition circuit.

The sampling pulse generator 9 generates a sampling pulse Ps with a repetition frequency equal to the upper limit value of the above-mentioned variable data acquisition rate. A/D
The converter 8 samples and holds the input analog signal e _i ′ for each sampling pulse Ps,
It is then converted into a digital signal and output (d).

The adder 10 and the latch circuit 11 constitute an accumulation circuit, which sequentially processes the A/D for a specified number of times.
The converted result d is accumulated. Latch circuit 11
is cleared by the data request signal DREQ and holds the addition result A of the adder 10 every Ps,
It is applied to one input of the adder 10 and added to the A/D conversion result d obtained at the next timing Ps. Therefore, Ps occurring between successive DREQs
The sequential A/D conversion result data is accumulated by the number of pieces. The counter 12 is also similar to the latch circuit 11.
cleared by DREQ, and the DREQ described above
Count the number of Ps in between. This count value is the number B of accumulations performed by the adder 10.

The divider 13 divides the above-mentioned accumulation result A by the number of accumulations B. This division result C represents an average value and is further stored in the latch circuit 14.
Output as DATA.

In this way, as the data collection rate decreases, that is, as the interval between the data request signals DREQ becomes longer, the number of times the A/D conversion result data is accumulated increases, and the width of the period in which the average value is taken becomes longer. This is equivalent to increasing the time constant of a smoothing circuit or a low-pass filter, and has the effect of attenuating high-frequency noise components.

Figure 5 shows an example of changing the data acquisition rate, and Figure 1 shows the input analog signal e _i , sampling pulse Ps (Ps ₁ , Ps ₂ ,...) and A/D conversion result d.
(d ₁ , d ₂ ,…) is shown. Figure 2 shows the data request signal when the data acquisition rate is at the upper limit of the variable range.
Indicates DREQ. In this case, the A/D conversion results d are not averaged by accumulation, and each d is output as is. Figure 3 shows that when the data collection rate is half,
Figure 4 shows the case where the data collection rate is 1/4.
DREQ is shown respectively. In FIG. 3, two A/D conversion results d are averaged, and in FIG. 4, four A/D conversion results d are averaged.

Note that each of the circuit elements indicated by 9 to 14 in FIG. 1 can be replaced by, for example, the software functions of a microprocessor.

〔Effect of the invention〕

As described above, according to the present invention, the noise removal characteristics can be changed digitally in accordance with changes in the data collection rate, and the circuit can be configured to be simple and compact.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a circuit according to one embodiment of the present invention, and FIG.
FIG. 3 is an explanatory diagram of changing the data acquisition rate, FIG. 3 is a configuration diagram of a conventional example, FIG. 4 is an explanatory diagram of band characteristics of a preamplifier, and FIG. 5 is an explanatory diagram of the operation of the embodiment. In the figure, 7 is a preamplifier, 8 is an A/D converter, and 9 is a preamplifier.
is a sampling pulse generator, 10 is an adder, 1
1 and 14 are latch circuits, 12 is a counter, 13 is a divider, e _i is an input analog signal, DREQ is a data request signal, and DATA is output data.

Claims (1)

[Claims] 1 a preamplifier that amplifies the input analog signal;
an A/D converter connected to the preamplifier; a fixed sampling pulse source for driving the A/D converter; and an addition for accumulating the A/D conversion results output from the A/D converter. a counter that holds the number of times the A/D conversion result has been accumulated; and a repetition frequency that is transmitted to clear the adder and the counter and control the number of times that the A/D conversion result has been accumulated is variable. a divider for dividing the accumulation result output from the adder by the number of accumulations; and an output means for outputting the division result output from the divider as data. An analog data acquisition circuit characterized by: