JPH0442822B2 - - Google Patents

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for forming an element isolation region, and in particular, the present invention relates to a method for forming an element isolation region, and in particular, an etching mask formed by taper etching an oxide film layer to form an oxide-resistant film such as a silicon nitride film. The present invention relates to a method for forming an element isolation region in which a mask for field oxidation is formed by etching a chemical film.

[Prior Art] As the patterns of integrated circuit devices become finer, the element isolation regions that insulate and isolate each element formed on the integrated circuit device from each other also become finer, and the area occupied by these regions is required to be made finer. There is. For this reason, various methods have been proposed as methods for forming element isolation regions, and the conventional selective oxidation (LOCOS) method is still in use with some modifications. In particular, recently, methods have been proposed to suppress the bird's beak, such as making the padded oxide thinner or forming a polycrystalline silicon layer between the padded oxide and the silicon nitride (Si ₃ N ₄ ) layer. ing.
Through these methods, crystal defects are also suppressed, and bird's beaks are suppressed to about 0.3 microns, less than half of the conventional level, thereby further improving the degree of integration of integrated circuit devices.

[Problems to be Solved by the Invention] However, as the circuit patterns of integrated circuit devices become further miniaturized, the fact that the bird's beak extends from the edge of the silicon nitride mask even if it is 0.3 microns becomes a major problem in the case of fine pattern formation. It is becoming an obstacle.

For example, if you are trying to form a device with an isolation region width of 1.2 microns and an activation region width of 1.2 microns, taking into account the 0.3 micron extension of the bird's beak, the mask dimensions will need to be 0.6 microns and 1.8 microns, respectively. be. However, since the exposure equipment used to form each of these regions is used to match the typical size of the device pattern, achieving dimensions such as 0.6 microns compared to the 1.2 micron rule will affect the performance of the exposure equipment. This results in the disadvantage that the limit is exceeded, and therefore, it is impossible to form such miniaturized regions.

In view of the above-mentioned problems in the conventional example, it is an object of the present invention to perform exposure without unnecessary and fine patterning exceeding the limit of the exposure device, and by simply performing exposure with a representative dimension. The purpose is to make it possible to realize fine patterns that exceed the performance limits of equipment, etc.

Another object of the present invention is to enable the formation of element isolation regions having minute dimensions that exceed the performance limits of exposure equipment, thereby further improving the degree of integration of semiconductor integrated circuit devices.

[Means for Solving the Problems] In order to achieve the above-mentioned object, a method for forming an element isolation region according to the present invention includes forming at least a thin oxide film, an oxidation-resistant film, and a masking oxide film on a semiconductor substrate such as silicon. a step of forming a layer in this order, a step of taper etching the mask oxide layer,
The method includes a step of etching the oxidation-resistant film using the tapered etched oxide layer as an etching mask, and a step of performing field oxidation of the semiconductor substrate using the oxidation-resistant film as a mask.
Taper etching of the masking oxide layer includes patterning a resist layer on the masking oxide layer and depositing at least the sidewalls of the resist layer in an etching region defined by the resist layer. This is done by dry etching the masking oxide layer.

[Operation] In the above method, the etching of the masking oxide layer is carried out by etching the masking oxide layer while depositing it on the sidewalls of a resist layer or the like that defines the etching region of the masking oxide layer. It is done. Therefore, as the etching progresses, the etching area defined by the resist layer gradually becomes smaller, thus performing taper etching. Furthermore, since this taper etching is performed in such a way that the etching area initially defined by the resist layer gradually becomes smaller, the oxidation-resistant etching is performed using such a taper-etched masking oxide layer as an etching mask. By etching the film, the area defined by the oxidation resistant film is also smaller than the etched area of the masking oxide layer initially defined by the resist layer. Therefore, by performing field oxidation using such an oxidation-resistant film as a mask, it is possible to form a fine element isolation region exceeding the performance limit of the exposure apparatus.

[Examples] Examples of the present invention will be described below with reference to the drawings.
FIGS. 1a to 1f show each step of a method for forming an isolation region according to an embodiment of the present invention. First, in FIG. 1a, a thermal oxide film (SiO ₂ ) 3 is grown on a silicon substrate 1 to a thickness of, for example, 100 angstroms, then a polycrystalline silicon layer 5 is deposited to a thickness of, for example, 500 angstroms, and then A silicon nitride film (Si ₃ N ₄ ) 7 is deposited thereon to a thickness of, for example, 1500 angstroms.
Next, phosphosilicate glass (PSG) 9 having a phosphorus (P) concentration of 4 wt% is deposited to a thickness of, for example, 1 micron. Further, in order to form an element isolation region, photoresist 11 is spin-coated to a thickness of, for example, 1 micron, and exposed and patterned using a mask with an element isolation region width of 1.2 microns and an activation region width of 1.2 microns. A photoresist mask 11 as shown in FIG. 1b is formed.

Next, the oxide film (PSG) 9 is tapered etched by an etching method using side deposition, which will be described in detail later, and the photoresist 11 and the like are removed by ashes. As a result, as shown in FIG. 1c, the oxide film 9 is tapered etched so as to bulge by, for example, 0.3 microns from the edge of the mask, and the width of the exposed portion of the silicon nitride film 7 defined by the oxide film 9 is 0.6 microns. Become.

Next, the silicon nitride film 7 is etched using the oxide film 9 as a mask, and the oxide film 9 is then removed. As shown in FIG.
It can be patterned to dimensions of 0.6 microns.

Next, field oxidation is performed to form a field oxide film 13 having a thickness of, for example, 5000 angstroms, as shown in FIG. 1e. This field oxide film 13 constitutes an element isolation region.

Furthermore, the silicon nitride film 7, the polycrystalline silicon layer 5, and the thin oxide film 3 at the bottom layer are removed. This makes it possible to obtain a field oxide film region, that is, a device isolation region of 1.2 microns and an activation region of 1.2 microns, as shown in FIG. 1f.

FIG. 2 schematically shows a three-electrode etcher as an example of an apparatus used for taper etching the oxide film 9 in the above-described element isolation region formation process. The device shown in the figure has an upper electrode 21
, a lower electrode 23 , and, for example, a mesh-shaped intermediate electrode 25 arranged between the upper electrode 21 and the lower electrode 23 . Intermediate electrode 25
is grounded, and a high frequency power source 31 is connected to the upper electrode 21 and the lower electrode 23 via variable capacitors 27 and 29, respectively. Further, a wafer 33 is placed on the lower electrode 23. Note that the upper electrode 21, the lower electrode 23, the intermediate electrode 25, etc. are housed in a predetermined chamber, and the chamber is configured so that etching gas and the like can be introduced as described later.
Detailed illustrations thereof are omitted.

In the device shown in FIG. 2, the output power of the high frequency power source 31 is fixed, for example, and the variable capacitors 27 and 2
By adjusting the capacitance value of 9, etching and deposition are simultaneously performed at a certain level on the wafer 33 placed on the lower electrode 23 side, and the deposition is so-called side deposition performed on the side wall of photoresist or the like. I can do it. That is, by increasing the power applied to the lower electrode 23, the self-bias of the lower electrode 23 increases, and the ion energy required for etching the oxide film can be increased. On the other hand, if the power applied to the upper electrode 21 is increased, the self-bias of the lower electrode 23 is reduced, the concentration of active species required for deposition is increased, and the amount of deposition is therefore increased.

The above phenomenon will be explained in more detail. in general,
As an etching gas for the oxide film, CHF ₃ ,
A gas system such as CHF ₃ +O ₂ , C ₂ F ₆ +CHF ₃ or C ₂ F ₆ +H ₂ is used. When these gas systems enter a plasma state, etchants are generated and, at the same time, reactive species that contribute to the polymerization reaction are also easily generated, and a polymer having carbon as a main chain is formed in an area where sputtering is not effective. However, when the power applied to the lower electrode 23 is large, the polymer to be formed is removed due to the sputtering effect. In general, sputtering efficiency has angular dependence on the incident angle of ions. When the angle of incidence is 0°, that is, when ions are incident perpendicularly to the wafer, the sputter rate has a certain value that is not very large, and as the angle of incidence increases to around 50°, the sputter rate increases. It shows a peak at around 50°. As the incident angle is further increased, the sputter rate decreases, and at an incident angle of 90 degrees, the sputter rate is 0, that is, the sputtering effect completely disappears. On the other hand, the deposition rate has little angle dependence and is determined by the concentration of active species. In the case of ordinary reactive ion etching, the polymer deposition rate is kept quite low, whereas the sputtering rate is sufficiently high. The workpiece is therefore etched vertically. In contrast, in the method according to the present invention, the deposition rate is set to a relatively large value, and is set to an extent that depends on the magnitude of the sputter rate. Therefore, when the sputter rate changes depending on the incident angle of ions, deposition is observed at the incident angle where the deposition rate exceeds the sputter rate. Therefore, by appropriately selecting the ratio of deposition rate to sputtering rate, the apparatus of FIG. 2 can be conditioned to perform deposition at relatively large angles of incidence.

Consider, for example, a sample to be etched as shown in FIG. 3a under such operating conditions. That is, in the sample shown in the figure, a silicon oxide layer (SiO ₂ ) 37 is formed on a silicon semiconductor substrate 35, and a photoresist 41 having an opening 39 for defining a contact hole, for example, is formed on this oxide layer 37. is formed. By etching such a sample to be etched using an etcher set to the operating conditions described above, oxide layer 37 can be simultaneously etched while depositing on the sidewall of opening 39 of photoresist 41. That is, if etching ions are incident perpendicularly to, for example, the oxide layer 37, the incident angle of these ions to the oxide layer 37 is 0°, but the incident angle to the side wall portion of the opening 39 of the photoresist 41 is approximately 0°. It will be 90°.
To this end, polymer is deposited on the sidewalls of opening 39 in photoresist 41, while oxide layer 37 is etched. In this manner, as shown in FIG. 3b, the etching area defined by the photoresist 41 is gradually narrowed as a result of simultaneous deposition on the sidewalls of the opening 39 and etching of the oxide layer 37. The oxide layer 37 is then tapered etched. In this case, the deposit is deposited from the sidewall of the opening 39 in the photoresist 41 to the sloped wall created in response to the etching of the oxide layer 37, as shown by the hatched area in FIG. 3b. After etching is performed in this way, if the deposit 43 and the photoresist 41 are removed, as shown in FIG. 3c,
A slope-etched oxide layer 37 is obtained.

Note that the above-mentioned taper etching is not limited to the three-electrode etcher shown in Fig. 2, but can also be applied to other devices, such as an ECR type etcher using a magnetron, by independently controlling the energy of ions perpendicularly incident on the wafer, etc. Alternatively, the wafer or the like can be cooled in a two-electrode parallel plate etcher to increase the gas adsorption efficiency.

[Effects of the Invention] As described above, according to the present invention, taper etching of an oxide film is performed by utilizing side deposition on a resist layer, etc., and the taper etched oxide film is used to form a silicon nitride film. Perform etching such as According to the oxide film etching method using side deposition, taper etching proceeds from the end of the resist mask, so the dimensions of the oxide film region after etching are smaller than the resist mask dimensions.
Moreover, in the taper etching method using side deposition described above, the taper angle can be controlled freely, so the increase in the lateral dimension from the mask edge to the bottom of the oxide film can be controlled arbitrarily. becomes possible. Therefore, according to the present invention, when a method for forming an element isolation region such as the improved LOCOS method is applied to the formation of devices with minute dimensions of about 1 micron or less, it is unnecessary and exceeds the limit performance of the exposure apparatus. There is no need to perform patterning. Therefore, it is possible to form fine patterns on integrated circuit devices without requiring extremely high performance from the exposure apparatus.

[Brief explanation of drawings]

1a to 1f are explanatory diagrams showing each step of a method for forming an element isolation region according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing a method for forming an element isolation region according to an embodiment of the present invention An electric circuit diagram schematically showing a three-electrode etcher for carrying out the etching, and FIGS. 3a to 3c show each method for taper etching of an oxide film used in the method for forming an element isolation region according to the present invention. It is an explanatory diagram showing a process. 1: Substrate, 3: Thin oxide film, 5: Polycrystalline silicon layer, 7: Silicon nitride film, 9: Oxide film layer, 11:
Photoresist layer, 13: Field oxide film, 2
1: Upper electrode, 23: Lower electrode, 25: Intermediate electrode, 27, 29: Variable capacitor, 31: High frequency power supply,
33: wafer, 35: silicon substrate, 37: oxide film layer, 39: opening, 41: photoresist.

Claims (1)

[Claims] 1. A step of forming at least a thin oxide film, an oxidation-resistant film, and a masking oxide layer on the surface of a semiconductor substrate in this order, a step of taper-etching the masking oxide layer, and a step of taper-etching the masking oxide layer. A method for forming an element isolation region, comprising the steps of: etching the oxidation-resistant film using a masking oxide layer as an etching mask; and performing field oxidation of a semiconductor substrate using the oxidation-resistant film as a mask. 2. Taper etching of the masking oxide layer is performed by patterning a resist layer on the masking oxide layer and depositing on at least the sidewalls of the resist layer in the etching area defined by the resist layer. 2. A method according to claim 1, which is carried out by etching said masking oxide layer. 3. The thin oxide film is a silicon dioxide film,
2. The method according to claim 1, wherein after forming a polysilicon layer on the silicon dioxide film, a silicon nitride film is formed as the oxidation-resistant film. 4. The method according to claim 1, wherein the masking oxide layer is a phosphosilicate glass layer.