JPH0442831B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention mainly relates to a semiconductor integrated circuit as a bipolar random access memory.

[Conventional technology]

Recent bipolar random access memories (hereinafter referred to as Bip RAM) use oxide isolation and trench type isolation to achieve even higher integration and speed, and also use information retention current to reduce power consumption. efforts are being made to reduce the number of

However, compared to the conventional Bip RAM,
Since the amount of information-holding charge generally tends to decrease, α-ray soft errors are likely to occur, which poses a major problem in terms of reliability.

In particular, BIP is used for buffer memory and control memory devices of medium-sized and large-sized computers.
This is critical because RAM does not allow ECC (Error Detection and Correction) to be used in these devices.

Let me add a little explanation about this α-ray soft error. α rays are used in semiconductor integrated circuits (hereinafter referred to as IC).
That's what it means. ), trace amounts of U (uranium) and
Released by alpha decay of Th (thorium). The energy of the emitted alpha rays ranges from a center of 5 MeV to a maximum of 9 MeV. When alpha rays with an energy of 5 MeV are irradiated into silicon, they penetrate to a depth of approximately 30 μm, generating 1.4×10 ⁶ electron-hole pairs. In particular, when the holes generated in the n-type collector region reach the collector-substrate junction, they are drawn by the electric field within the junction and flow toward the substrate. Further, electrons generated within the substrate and reaching the collector-substrate junction are drawn toward the collector by the electric field within the junction. As a result, current flows from the collector to the substrate.

For this reason, the collector potential of the off-side transistor forming the Bip RAM memory cell, a so-called flip-flop, decreases. When this potential change becomes approximately 1/2 or more of the hold voltage, inversion occurs. In other words, an α-ray soft error will occur.

Conventionally, the following measures have been taken to counter this problem.

(a) For the purpose of reducing alpha ray emissions from chip parts and inside, use IC forming materials and package materials with low content of alpha ray radioactive substances.

(b) For the purpose of reducing alpha rays from outside the chip, an alpha ray shielding film is attached to the chip surface.

(c) Increase the holding voltage and current of the memory cell in order to increase the amount of charge stored in the protection information.

(d) For the same purpose as in (c) above, increase the capacitance attached to the collector of a memory cell to increase the amount of charge stored in the cell.

[Problem that the invention seeks to solve]

With method (a) above, it is actually difficult to completely remove alpha-ray radioactive substances from the material, and so far there is no perfect countermeasure. In case (a), although shielding alpha rays from outside the chip is quite effective, it is not possible in principle to shield alpha rays from inside the chip.
The above method (c) has already reached its limit in terms of the forward voltage Vf of the shot key barrier diode SBD for memory cell clamping and the overall power, and further improvement is essentially difficult.

Although the above methods (a) to (c) can be expected to improve to a certain extent, it is not perfect.

Therefore, method (d) is the only complete countermeasure. However, increasing the capacitance attached to the collector as a countermeasure against α-ray soft errors has the disadvantage that the size of the transistor inevitably increases.

The purpose of the present invention is to attach the memory cell to the collector of the transistor constituting the memory cell without contradicting the direction of high integration and high speed through fine patterning, that is, without enlarging the shape of the memory cell. It has a structure that increases the total capacity (C _T ) and increases the margin against α-ray soft errors.
The goal is to provide IC.

[Means for solving problems]

The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit in which a semiconductor element region is separated by a groove formed in one main surface of a semiconductor substrate and whose inner surface is covered with an insulator, in which the inside of a first groove is made of metal or A highly doped conductor such as polysilicon is buried to approximately the height of the surface of the semiconductor substrate, and the inside of the second trench other than the first trench is filled with an insulator or an insulator such as polysilicon that is or is close to intrinsic. It consists of a semiconductor buried almost to the height of the surface of the semiconductor substrate.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing essential parts of a first embodiment of the present invention.

In this embodiment, grooves 16a, 1 are formed on one main surface of a P-type semiconductor substrate 11 and the inner surface is covered with an oxide film 17.
In the IC from which the semiconductor element region 13 made of an epitaxial layer is separated in 6b, the inside of the first trench 16a is filled with polysilicon 18a doped with high concentration of boron to the height of the surface of the semiconductor substrate 11, and The interior of the second groove 16b other than the first groove 16b is filled with intrinsic polysilicon 18 up to the height of the surface of the semiconductor substrate 11. In addition,
In the figure, 12 is a buried layer and 19 is a nitride film.

According to the structure of this embodiment, the semiconductor element region 13
Two capacitors are formed between the oxide film 17 and the trench 16a. Therefore, in the semiconductor element region 13
By forming a paired transistor of a flip-flop that constitutes a memory cell of Bip RAM and connecting its collector to the capacitance described above, the capacitance attached to the collector of the paired transistor can be increased without particularly increasing the chip area.

Next, the manufacturing method of this example will be explained.

FIGS. 2a to 2d are cross-sectional views of the main manufacturing steps of this embodiment.

First, as shown in FIG. 2a, a P-type semiconductor substrate 1
A buried layer 12 for a memory cell transistor region is formed on the buried layer 12 of the memory cell transistor region, and an epitaxial layer 13a of 5 Ωcm is grown thereon to a thickness of 1 μm. Then, a nitride film 14 having a thickness of 0.5 μm is grown on the epitaxial layer 13a, and a resist 15 is applied to the upper surface of the nitride film 14.

Next, as shown in FIG. 2b, the P-type semiconductor substrate 1
1 to form grooves 16 and separate semiconductor element regions 13.

Next, as shown in FIG. 2c, the nitride film 14 is removed, and the bottom and wall surfaces of the groove 16 and the semiconductor element region
3 surface is thermally oxidized at 1000° C. for 10 minutes to form an oxide film 17.

Next, as shown in FIG. 2d, the entire trench 16 is filled with intrinsic polysilicon 18 so that its height is approximately the same as the surface of the semiconductor element region 13.

Next, a nitride film 19 is formed on the upper surface of the wafer whose surface has become substantially flat. A groove 16a between a pair of transistors constituting a flip-flop is formed.
The nitride film 19 on the upper surface is selectively etched. Then, high concentration boron is diffused. The groove 1 between the pair of transistors thus forming a flip-flop
Only the grooves 6a are filled with polysilicon 18a doped with high concentration of boron, and the other grooves 16b are
This results in the embodiment shown in FIG. 1 filled with intrinsic polysilicon 18.

FIG. 3 is a schematic plan view showing the main parts of the second embodiment of the present invention.
This represents the plane of a wafer on which memory cell portions are formed. FIG. 4 is its equivalent circuit diagram.

In this embodiment, in the first embodiment shown in FIG.
In the two semiconductor element regions 13, flip-flop pair transistors Q ₁ and Q ₂ and their respective SBDs,
It forms a load resistance R. That is, base 20, emitter 21, collector 22, SBD
23. A memory cell is obtained by forming a load resistor 24 using a conventional method and connecting the open electrodes with Al wiring.

Thus, according to this embodiment, the transistor
Between the collectors of Q ₁ and Q ₂ , capacitances C ₁ and C ₂ formed on both sides of the groove 16a enter in parallel with the collector-base capacitance C _CB of transistors Q ₁ and Q ₂ , and all the capacitances attached to the collectors are It can be seen that the capacitance (C _T ) becomes large and is highly effective in preventing α-ray soft errors.

In Fig. 4, C _CS is the collector-substrate capacitance, and C _EB is the emitter-base capacitance.

In this embodiment, the thickness of the insulating film (oxide film 17 in this embodiment) on the wall surface of the groove 16a sandwiched between the collectors to which the capacitance is to be added is made thinner, while the characteristics allow it. C ₁ and C ₂ can be increased, and the margin for α-ray soft errors can be increased.
In this case, if you make only the insulating film at the bottom of the groove a little thicker,
High speed is not reduced. Furthermore, if an insulating film with a high dielectric constant is selected, the effect will be even greater. or,
There is absolutely nothing wrong with changing the concentration of doping into silicon.

FIG. 5 is a schematic plan view showing essential parts of a third embodiment of the present invention, and FIG. 6 is an equivalent circuit diagram thereof. In this embodiment, the groove 16a is inserted so that the additional capacitors C ₁ ′ and C ₂ ′ are inserted between the collector and the word line _WH .
It has been established. In this case as well, there is a sufficient effect against α-ray soft errors.

Although examples have been described above, the present invention is not limited to these examples,
Various variations can be considered.

〔Effect of the invention〕

As described above in detail, according to the present invention,
Highly doped polysilicon or conductor can be selectively formed inside the groove of the semiconductor element isolation region without impairing the performance of the semiconductor element, and capacitance can be formed between adjacent elements on both sides of the trench, which can improve memory cell performance. Capacitance can be added to the collector side of the detector, which is highly effective in preventing α-ray soft errors. Furthermore, other parasitic capacitances do not increase at all, and high-speed performance is not impaired.

Therefore, it is possible to obtain a semiconductor integrated circuit which not only has high-speed performance of elements and an improved degree of integration, but also has high reliability of the integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the main parts of the first embodiment of the present invention, FIGS. 2 a to d are sectional views showing the main manufacturing steps of this first embodiment, and FIG. FIG. 4 is a schematic plan view showing the main part of the third embodiment of the present invention, FIG. 4 is an equivalent circuit diagram thereof, FIG. 5 is a schematic plan view showing the main part of the third embodiment of the present invention, and FIG. 6 is its equivalent circuit diagram. It is a circuit diagram. 11...P-type semiconductor substrate, 12...buried layer,
13... Semiconductor element region, 13a... Epitaxial layer, 14... Nitride film, 15... Resist, 1
6, 16a, 16b...groove, 17...oxide film, 1
8...Intrinsic polysilicon, 18a...Polysilicon doped with high concentration boron, 19...Nitride film,
20... Base, 21... Emitter, 22... Collector, 23... SBD, 24... Load resistance, C ₁ ,
C ₁ ′, C ₂ , C ₂ ′...Additional capacitance, Q ₁ , Q ₂ ...Transistor, W _H ...Word line.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit in which semiconductor element regions are partitioned and separated by grooves formed in one principal surface of a semiconductor substrate and whose inner surfaces are covered with an insulating film, the grooves that partition at least one semiconductor element region are , a first groove whose inside is buried with a conductor to approximately the height of the surface of the semiconductor substrate; and a second groove which is connected to the first groove and whose inside is buried with a substantial insulator up to approximately the height of the surface of the semiconductor substrate. A semiconductor integrated circuit characterized by consisting of a groove. 2. A semiconductor integrated circuit according to claim 1, comprising a memory cell consisting of a flip-flop having a pair of vertical bipolar transistors as driving transistors, each formed in a pair of adjacent semiconductor element regions with a first groove in between. circuit.