JPH0443449B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an echo canceller for a bidirectional digital transmission system using a hybrid circuit.

In digital subscriber line transmission systems and the like, bidirectional digital transmission is made possible via a two-wire transmission line by using a hybrid circuit.
In such a transmission system, the transmitted signal goes around to the receiving side via the hybrid circuit and becomes an echo signal, which causes problems in the reception of digital data. Although technical means have been developed to avoid such inconveniences, there is still room for improvement in these means.

[Conventional technology]

The echo canceller that has been developed in the past is equipped with an echo canceller that cancels the echo signal coming through the hybrid circuit at a baud rate faster than the sampling period of the received signal, and eliminates the influence of the echo signal on the output of the line equalizer. This is what we try to eliminate as much as possible.

[Problem that the invention seeks to solve]

Since this echo canceller cannot completely cancel the echo, echo correction remains at the decision point, and the inconvenience caused by the presence of the echo signal remains unsolved.

Furthermore, in order to suppress the peak value of the residual echo correction to a predetermined value or less, it becomes necessary to increase the number of sampling points used in the correction. This is not a good idea as it will drastically increase the amount of hardware. Furthermore, since the dynamic range required for echo correction is required to be relatively large, the correction circuit must have high precision, in other words, a large number of bits.

[Means for solving problems]

The present invention provides an echo canceller that solves the above-mentioned problems, and the present invention provides an echo canceller that uses a line equalizer and a transmission digital signal to the hybrid circuit in a bidirectional digital transmission system using a hybrid circuit. a first correction means that receives a signal and a received signal from the hybrid circuit, corrects an echo signal from the hybrid circuit using a sampling clock higher than the baud rate of the received signal, and outputs the corrected signal to the line equalizer; In response to the digital signal transmitted to the circuit and the output signal of the line equalizer, the receiver is configured to suppress the correction residual of the echo signal at the decision point of the received signal using a baud rate clock extracted from the received signal. and second correction means for correcting the output signal of the line equalizer at the same sampling period as the baud rate of the signal.

[Effect]

According to the echo canceller of the present invention, in the first correction means that receives the transmitted digital signal inputted to the hybrid circuit and the received signal of the hybrid circuit, the echo signal included in the received signal is processed at a sampling rate higher than the baud rate of the received signal. The period is corrected and the corrected echo signal is input to a line equalizer to suppress high frequency components contained in the echo signal.

The second correction means suppresses the uncorrected echo component at the decision point of the received signal using the baud rate clock extracted from the received signal. Therefore, the echo component at the decision point in the received signal is almost suppressed.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the invention. 1 is a hybrid transformer of a bidirectional digital transmission system. 2 is a first stage echo canceller which receives the transmitted digital signal on line 3 and the echo canceller 1 signal on line 4 and sends out an echo replica-1 signal on line 5. A subtracter 6 receives the echo replica-1 signal and the received signal from the hybrid transformer 1, calculates the difference between them, and generates an echo cancel-1 signal on the line 4.

7 is a line equalizer which receives the signal on line 4 and applies a required equalization effect to the signal.

8 is the second stage echo canceller, which is line 3
It receives the above transmission digital signal and the echo cancel-2 signal on line 9 and sends out an echo replica-2 signal on line 10. A subtracter 11 receives the echo replica-2 signal and the output signal of the line equalizer 7, calculates the difference between them, and generates an echo cancel-2 signal on the line 9.

Figure 2 shows the first stage echo canceller 2 and the second stage echo canceller 2.
An example of an echo canceller used in the stage echo canceller 8 is shown. This exemplary echo canceller uses random access memory (RAM) 20
A table reference echo canceller using
Echo replica data is stored in the RAM 20. The data is updated during the echo canceller training period as follows. That is, echo replica data sequentially generated via an echo detection circuit 21, an addition circuit 22, and a flip-flop (FF) 23 is sent to a shift register 24,
The data are sequentially stored at addresses generated via the control circuit 25 and updated. and,
The echo replica data in the RAM 20 is supplied to an adder circuit 22 via a flip-flop (FF) 26 and also to a digital-to-analog (D/A) converter 27. The output signal of the D/A converter 27 is supplied as an echo replica-1 signal together with the received signal from the hybrid transformer 1 to a subtracter 6, from which an echo cancel-1 signal is generated.

Further, in this embodiment, the second stage echo canceller also has the same structure as the first stage echo canceller, as described above. The difference lies in the sampling clock. That is, whereas the second stage echo canceller operates with the required sampling clock, e.g. the baud rate sampling clock,
The first stage echo canceller operates at a high speed sampling clock that is a predetermined value higher than the baud rate mentioned above. This high speed sampling clock can also be of a much lower frequency than the sampling clock required by conventional echo cancellers.

The operation of the echo canceller of the present invention constructed in this way will be explained using FIG. 3.

The transmitted digital signal is transmitted through hybrid transformer 1.
At the time when the echo signal [3-1 in Figure 3] sent to the receiving side via the subtracter 6 reaches the subtracter 6, the first
The stage echo canceller 2 operates on a high-speed sampling clock [3-2 in Figure 3], and from there, the echo replica-1 signal for fine echo correction on the time axis is generated [3-3 in Figure 3]. is generated and supplied to the subtracter 6. As described above, this echo replica-1 signal is generated during training so as to reduce the output value of the subtracter 6, and is stored in the RAM 20 of the echo canceller 2. In the subtracter 6, the echo replica-1 signal is subtracted from the echo signal. Thereby, the correction is made to the extent that the correction residual at the output of the line equalizer 7 can be suppressed to a predetermined value or less. Thus, the echo canceller 1 signal (see 3-4 in FIG. 3) is supplied to the input of the line equalizer 7. This echo canceller 1 signal is transmitted to the first stage echo canceller 2.
Due to the high-speed sampling in , the residual echo output from the first echo canceller 2 has the following characteristics:
Contains high frequency components.

Since the line equalizer 7 is approximated by a high-gain filtering characteristic (inverse characteristic of the transmission line frequency characteristic), the frequency characteristic of the line equalizer 7 is approximately 1/2 (Nyquist) of the baud rate (fb). The frequency characteristic is such that the gain has a peak value at a frequency (fb), and the gain decreases rapidly in a frequency range exceeding the baud rate (fb). Therefore, when the echo canceller 1 signal is equalized by the line equalizer 7, the high frequency components of the residual echo output from the first stage echo canceller 2 are largely suppressed. A residual echo signal (echo correction residual) remains in the signal output from the line equalizer 7, as shown at 3-5 in FIG. The residual echo signal is supplied to a subtracter 11.

This subtracter 11 also has a sampling clock with the same baud rate as the received signal [3-6 in Figure 3].
Echo replica-2 for coarse residual echo correction on the time axis generated from the second-stage echo canceller 8 operating in
A signal (see 3-7 in FIG. 3) is supplied. This echo replica-2 signal is also generated during training by reducing the output of the subtracter 11 as described above, and is sent to the second stage echo canceller 8.
is stored in the RAM 20 of.

By receiving the above two signals and subtracting the echo replica-2 signal from the residual echo signal in the subtracter 11 which responds to the baud rate clock extracted from the received signal, the echo component is substantially eliminated at the decision point of the received signal. Echo cancelled-2 signal that is suppressed [3- in Figure 3]
8] is obtained.

In the above embodiment, the first-stage echo canceller and the second-stage echo canceller both obtained echo replica signals by training, and after that period, the obtained echo replica signals were used. , an adaptive version of the echo canceller may be used to dynamically deal with echo conditions.

Further, the gist of the present invention can also be applied to a case where a transversal type echo canceller is used.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to sufficiently correct the echo at the signal decision point, and it is possible to reduce the accuracy required for each echo canceller without increasing the circuit scale. , These advantages can be obtained, such as advantageous development of LSI echo cancellers.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a specific configuration example of an echo canceller used in the embodiment of FIG. 1, and FIG. 3 is a diagram showing signals in various parts of the embodiment of FIG. 1. It is a figure which shows a waveform. In the figure, 1 is a hybrid transformer, 2 is a first stage echo canceller, 6 and 11 are subtractors,
7 is a line equalizer, and 8 is a second stage echo canceller.

Claims (1)

[Scope of Claims] 1. A bidirectional digital transmission system using a hybrid circuit, comprising: a line equalizer; a first correction means for correcting an echo signal from the hybrid circuit using a sampling clock and outputting the corrected signal to the line equalizer; , the output signal of the line equalizer is controlled at the same sampling period as the baud rate of the received signal so as to suppress the correction residual of the echo signal at the decision point of the received signal using the baud rate clock extracted from the received signal. An echo canceller comprising a second correction means for performing correction.