JPH0443456B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention comprises a control unit, a transmitter, and a receiver, the transmitter and the receiver being connected via a transmission line to sequentially transmit data words in a data bit stream. The present invention relates to a data transmission device that serially transmits columns.

The control unit includes a clock device for providing a series of clock pulse signals to the data transmission device, and a word selection signal generator.

The word selection signal generator has a first clock signal input terminal supplied with the clock pulse signal and generates a two-level word selection signal for selecting a data word to be transmitted under level change control. First means are provided to do so. The word selection signal is provided to the transmitter and receiver. The transmitter comprises buffer means for temporarily storing the data words to be transmitted.

PRIOR ART The control unit used in such a data transmission device is realized in a known manner, for example in a device of the type CX899 from Sony. This known device is used as a control unit for audio equipment. The word selection signal generator generates a word selection signal with a constant period. A data word can be transmitted between two sequential level changes of the word select signal. Another data word is selected each time the level of the word selection signal changes. A fixed period of the word select signal corresponds to a fixed number of clock pulses of the clock pulse signal.

A disadvantage of the known data transmission device is that the period of the word selection signal is constant. Therefore, only a data word of a fixed number of bits can be transmitted from the transmitter to the receiver. If the data word to be transmitted contains less than said certain number of bits, it is necessary to complete the data word. This results in inefficient use of transmission lines.

If the data word to be transmitted contains more than said certain number of bits, the entire data word cannot be transmitted completely.

OBJECTS OF THE INVENTION It is an object of the invention to adapt the period of the word selection signal to non-constant periods and to adapt the length of time between two successive level changes of the word selection signal to different data words containing different numbers of data bits. The goal is to provide a data transmission device that can.

Another object of the invention is to provide a data transmission device in which a well-defined and constant time relationship is established between the word selection signal and the first bit of the data word to be transmitted.

Configuration for Achieving the Object In the data transmission device of the present invention, the control unit is provided with a word selection signal generator, and the word selection signal generator is configured to control the word selection signal between two successive level changes of the word selection signal. second means for setting the time length of the clock pulse signal to a set of different time values, each of the set of different time values corresponding to a total number of clock pulses of the clock pulse signal; transmission control means having a second clock signal input terminal connected to the signal output terminal and a second clock signal input terminal connected to the signal output terminal; It is characterized in that third means are provided for storing data words to be transmitted in said storage means.

second means of the word selection signal generator allow the length of time between two successive level changes of the word selection signal to be set to a set of different time values;
Therefore, the word selection signal no longer has a constant period since it can be generated at an integral multiple of the clock pulse period. Storing a data word in said storage means under control of level changes of said word selection signal results in a data word of variable bit length and a word selection signal of variable length of time between two successive level changes. Collaborative action takes place between them.

Further, in the data transmission apparatus of the present invention, the transmission control means is configured to change the first data bit of the stored data word to the data after at least one-half clock pulse with respect to the supplied level change of the word selection signal. Fourth means for outputting to the output terminal is provided. There is therefore a well-defined relationship between the word selection signal and the data word to be transmitted.

Preferably, said first data bit is the most significant bit of said data word. The advantage is that the position of the most significant bit is always known.

Furthermore, the data transmission device of the present invention includes buffer (accumulation) means for temporarily accumulating data words received by the receiver, the accumulating means having a data input terminal connected to the transmission line, and selectively an array of addressable storage cells, said storage cells being selectively addressed under control of sequentially applied clock pulses.

The use of an array of selectively addressable storage cells facilitates knowing where the data bits of data words having different word lengths are stored.

Preferably, the control unit acts as a master unit and the transmitter and receiver act as slave units. In this manner, collisions between different master units can be prevented.

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

In the following description, the present invention has been described as being used in a digital audio device, but this is merely an example, and the present invention is of course not limited to audio devices. It can be used in any data transmission device that transmits data diametrically in the form of a bit stream.

FIG. 1 shows a simplified embodiment of a digital audio device to which the present invention can be applied. The digital audio device of this example comprises a central control unit 1, a transmitter 2 and a receiver 3. The central control unit sends out a clock pulse signal (SCK) on serial clock line 4 and a word selection signal (WS) on word selection line 5. The data flow of the transmitter 2 and receiver 3 is transported via a serial data transmission line 6 (SD). The transmitter and the receiver are controlled by a clock pulse signal (SCK) and a word selection signal (WS) supplied by the central control unit, so that the transmitter 2 and receiver 3 act as slave units of the central control unit 1. Operate. The central control unit can also be included within the transmitter or receiver, with the transmitter or receiver acting as the master unit.

FIG. 2a shows the pattern of the clock pulse signal (SCK), and FIG. 2b shows the pattern of the word selection signal (WS). The clock pulse signal is generated by a clock device in a well known manner.
The word selection signal is a two-level signal whose level changes each time another word needs to be transmitted. In this example, the level change of the word selection signal WS is selected to always occur at the same time as the trailing edge of the clock pulse signal. Of course, the selection in the present invention is not limited to this.

The word selection signal is generated by a word selection signal generator that is part of the central control unit. This word selection signal generator can be configured in several forms. When data is generated by a digital data source, such as a compact disk, the frequency of the word selection signal is determined by the format of the output data word, which means that the digital data source acts as a word selection signal generator. means to operate. If the data is generated by a data source that provides unspecified data (analog or digital), a dedicated word select signal generator is required.

FIG. 3 shows an example of such a dedicated word selection signal generator. This word selection signal generator 24 is connected to a clock device 21 supplying a clock pulse signal SCK and to a microprocessor 20 which is part of a central control unit. This signal generator 2
4 includes a counter 22, one input terminal of which is connected to a clock device 21, and the other input terminal of which is connected to a microprocessor 20.
The counter 22 counts the supplied clock pulses and is reset every time a predetermined number of clock pulses are counted. The value of the predetermined number is set by a microprocessor. Counter 22 generates an output signal when reset, which output signal is applied to the data input terminal of flip-flop 23.
The clock input terminal of the flip-flop 23 is supplied with an inverted clock signal via an inverter 25. Flip-flop 23 changes state on the leading edge of a pulse applied to its clock input.

The flip-flop 23, when supplied with the output signal of said counter, changes state as soon as the leading edge of the signal is applied to its clock input terminal, i.e., by the trailing edge of the clock pulse, and the data output terminal of the flip-flop 23 changes state. A word selection signal (WS) is sent.

Since flip-flop 23 is controlled by the inverted clock signal, the level of word select signal WS always changes simultaneously with the trailing edge of the clock pulse signal, as shown in FIGS. 2a and 2b. Therefore, the clock pulse signal and the word select signal are synchronized with each other.

Under the control of the microprocessor 20, said predetermined number can be set to different values depending on, for example, the word length of the data words to be transmitted or depending on the capabilities of the transmitter or receiver. Setting different values in this way means that the (time) between two successive level changes of the word selection signal
This means that the length is not constant and can accommodate several values. Since the counter 22 counts the clock pulses, the length of time between two successive level changes of the word select signal is always an integer multiple of the clock pulse period. In particular, therefore, the word selection signal can be adapted to the number of bits contained in the data word to be transmitted.

FIG. 4 shows a preferred embodiment of the audio transmitter. The transmitter in this example has two data latches 1 that temporarily store the digital audio signals of the left 10 and right 11 audio channels of the audio device.
0 and 11. These data latches have control input terminals which are supplied with a signal WSA (described later), which signal WSA is supplied directly to data latch 11 and inverted to data latch 10. The output terminals of data latches 10 and 11 are connected via bus 12 to parallel data input terminals of shift register 13. clock pulse signal
After SCK is inverted (via inverter 17), it is supplied to the clock input terminal of shift register 13. The data output terminal of this shift register is connected to the data transmission line 6. The data bits of the data word stored in shift register 13 are output serially on data line 6 under the control of the trailing edge of the clock pulse. The transmitter also includes two flip-flops 14 and 15 having clock inputs connected to clock line 4. A signal input terminal of the flip-flop 14 is connected to a word selection line 5, a signal output terminal of the flip-flop 14 is connected to a signal input terminal of a flip-flop 15, and a first input terminal of an exclusive OR gate 16 via a line 18. Connecting. The second input terminal of this exclusive OR gate 16 is connected to line 19.
It is connected to the signal output terminal of the flip-flop 15 via. The output terminal of exclusive OR gate 16 is connected to the control input terminal of shift register 13.
Flip-flops 14 and 15 are of the type that change state only on the leading edge of a clock pulse applied to their clock input terminals.

Here, as shown in FIG. 2b, the level of the word selection signal WS changes from a high level (logic "1") to a low level (logic "0"), and as shown in FIG.
Assume that the level of the signal WSP at the output terminal of the exclusive OR gate 16 is at a low level, as shown in FIG. Since only flip-flops 14 and 15 change state on the leading edge of the clock pulse, a change in the level of the word select signal WS is a signal
It has no immediate impact on WSP. A leading edge of a clock pulse following a change in the level of word select signal WS changes the state of flip-flop 14. This is the signal WSA on line 18
This means that the level of is changed from logic "1" to logic "0". In that case exclusive OR gate 1
a logic “0” signal is present at the first input terminal of 6;
And a logic "1" signal is present at the second input terminal. Therefore, the signal WSP is as shown in Fig. 2d.
reach a high level. If a change in signal WSA that causes a change of state in flip-flop 15 is applied to this flip-flop, this signal WSP returns to a low level due to the leading edge of the next clock pulse.
It is clear that a change in the level of the signal WSP also occurs due to a change in the word selection signal from a low level to a high level.

Assume again that the level of the word selection signal WS changes from high level to low level. The leading edge of the clock pulse that follows this causes a level change in the signals WSP and WSA, as already mentioned, i.e. WSA:=0 and WSP:=1 (where:= is the value to the right of the equal sign. ). =1 applied to the control input terminal of data latch 10 and shift register 13
The data word present in data latch 10 is stored in shift register 13 under the control of WSP=1 applied to data latch 10 .

Under the control of the trailing edge of said subsequent clock pulse, the first bit of the data word previously stored in shift register 13 is outputted and applied to serial data line 6 as shown in FIG. 2c.

Other bits of the data word are output under the control of other trailing edges of the clock pulse signal.

Serial data input terminal D of shift register 13 is set to zero. This is done for the case where the data word present in shift register 13 contains fewer bits than the number of clock pulses between successive level changes of the word selection signal. In that case, the word will be zero-completed.

When the word selection signal changes from low level to high level, WSA:=1 and WSP:=1.
Under the control of WSA=1 and WSP=1, the data word present in data latch 11 is transferred to shift register 1 for serial output on data line 6.
It is stored in 3. By storing the data words of the left audio channel in data latch 10 and the data words of the right audio channel in data latch 11, and by outputting them alternately from data latches 10 and 11, time division multiplexing is performed on the same serial data line. Transmission of independent audio channels takes place.

For this preferred embodiment, data words are always stored in the shift register such that after storing the data word in shift register 13, the most significant bit (MSB) is always applied first to serial data line 6. Make it. Therefore, the MSB has a constant position with respect to level changes of the word selection signal. In the transmitter of FIG. 4, the MSB of a data word stored in shift register 13 is always applied to serial data line 6 one clock pulse after the change in level of the word select signal. This is illustrated in Figures 2a, b and c. Therefore, there is a one clock pulse delay between the level change of the word select signal and the application of the MSB to the serial data line. This delay is necessary because in this embodiment the transmitter is a slave unit of the central control unit that provides the word selection signal. The transmitter can store new data in the shift register 13 only after being provided with a level change of the word selection signal.
Delaying the transmission of the MSB by one clock pulse allows sufficient time to store the new data word. This delay is also important because the length between two sequential level changes of the word select signal is not constant. This means that the transmitter does not know when the next level change of the word select signal will occur. Therefore, the transmitter is
It is necessary to wait until a level change of the word selection signal is supplied.

Of course, the delay in transmitting the MSB with respect to the level change of the word selection signal is not limited to one clock pulse. If each data word to be transmitted contains at least as many bits as the number of clock pulses included in such delay time, then
It is also possible to delay the transmission of the MSB for more than one clock pulse. It is also possible to make the delay in transmitting the MSB shorter than one clock pulse, for example half the period of one clock pulse. This transmission delay can be less than half a clock pulse period, but this places strict requirements on the operational capabilities of the digital audio device.

The fact that the most significant bit (MSB) of the data word to be transmitted has a constant position with respect to level changes of the word selection signal is related to the master-slave relationship of the transmitter and the central control unit.
It is also related to the non-constant length between two successive level changes of the word selection signal. If the MSB is provided as the first bit of a new data word to be transmitted, it will be reliably transmitted. The reason is that there is at least one clock pulse for every time difference between two successive level changes of the word select signal. Also, if the receiver needs to be able to tolerate fewer bits than are included in the data word, sending the MSB first will only result in the loss of the least significant bit (LSB).

FIG. 5 shows a preferred embodiment of an audio receiver to be used in a digital audio device according to the invention. The receiver of this example includes the flip-flops 14 and 15 and the exclusive OR gate 1 shown in FIG.
Signal WSA in a similar manner as done by 6
and a flip-flop 30,3 that generates WSP.
1 and an exclusive OR gate 32. Furthermore, this receiver has N storage cells 41-1, 41-
2, . . . , 41-N;
This storage device has an output terminal connected to bus 43. Bus 43 connects first and second data latches 35
and 36 data input terminals. These data latches have clock input terminals that are supplied with an inverted (via inverter 39) clock pulse signal. Also, data latches 35 and 3
6 has a control input terminal connected to the output terminals of AND gates 37 and 38. The first input terminals of AND gates 37 and 38 are connected to the output terminal of exclusive OR gate 32 so as to be supplied with signal WSP. The second input terminals of AND gates 37 and 38 are connected directly to the output terminal of flip-flop 30 and to inverter 4 so as to be supplied with signals WSA and
0 respectively.

This receiver also has a counter 33 and a decoder 3.
It also has 4. Counter 33 has a clock input terminal which is supplied with an inverted (via inverter 39) clock pulse signal. This counter also has a reset input terminal R connected to the output terminal of the exclusive OR gate 32 so as to be supplied with the signal WSP. This counter counts the clock pulses supplied to the clock input terminal, and is reset each time the signal WSP=1 is supplied to its signal input terminal. The output terminal of this counter is connected to the input terminal of a decoder 34. j pieces (however, 1≦j
A value j is applied to the input terminal of the decoder 34 after each counting of clock pulses .ltoreq.N). This decoder decodes this value j and based on it generates a pulse Ej at its output terminal Ej. Pulse E ₁ and
The pulse pattern of E ₂ is shown in Figures 2e and f.
The decoder 34 can only receive count values of N or less. After receiving the value N, the decoder detects that the counter receives the signal
The operation of the counter is prohibited until it is reset by WSP=1 (that is, after the level of the word selection signal changes). The counter is inhibited from operating by an inhibit signal applied to its input terminal I. If the counter counts fewer than N clock pulses between two sequential resets, no corresponding number of Ej pulses will occur. The results are further explained below.

Pulse Ej is applied to a first input terminal of AND gate 42-j, which is part of storage device 44. The second input terminals of these AND gates 42-j are connected to the serial clock line 4 so as to be supplied with clock pulse signals. These AND gates 42-j
The output terminal of is connected to the control input terminal of the associated storage cell 41-j. Storage cell 41-j is composed of a flip-flop. The data input terminal of each storage cell is connected to a serial data line 6.

Here, the signal WSA becomes equal to "0" due to the level change of the word selection signal, and the signal WSP:
Assume that =1. Assume also that there is a data word on storage device 44, ie on bus 43.
Since WSA=1 and WSP=1, a logic ``1'' is produced at the output terminal of AND gate 38, which enables data latch 36. The data word on bus 43 is stored in data latch 36 under control of the trailing edge of the clock pulse applied to this data latch.
To be compatible with the selection made to the transmitter (ensuring signal WSA = 1 to store the data word of the right audio channel in the shift register), the data latch 36 is set to store the data word of the right audio channel. while securing the data latch 35 to store the data word of the left audio channel. Therefore, when WSP=1 and WSA=1, data latch 35 is enabled.

At about the same time as storing the data word in data latch 36, decoder 34 generates pulse _E1 . and by the leading edge of the subsequent clock pulse.
AND gate 42-1 is activated, thus enabling flip-flop 41-1. As mentioned in the description of the transmitter (Fig. 4, Fig. 2c), the most significant bit (MSB) of the data word to be transmitted
is present on data line 6 in this example. Since the clock pulse 41 is enabled, the MSB is the flip-flop 41-1.
and output on bus 43. The bits following the MSB are transferred to flip-flop 41-- under the control of pulse _P2 and the leading edge of the next clock pulse.
2 and output on bus 43. This selective addressing process of these flip-flops is such that pulse En occurs and flip-flop 4
This continues until each of 1-1 to 41-N contains the supplied data bit or until counter 33 is reset by a subsequent WSP=1 before pulse En occurs. Following the above
Under the control of the WSP=1 signal, the entire process is performed for subsequent data words.

The fact that WSP=1 can be generated before generating the pulse En means that the flip-flops 41-1 to 41-1
41-N may not be supplied with data bits.
However, this does not affect the number of data bits stored in one of data latches 35 and 36. As shown in FIG. 5, flip-flops 41-2 to 41-N have reset input terminals R connected to the output terminal of exclusive OR gate 32 so as to be supplied with signal WSP. this is,
The trailing edge of the WSP=1 signal causes flip-flop 4
1-2 to 41-N are reset, and therefore flip-flops 41-2 to 41-N are set to logic "0".
means that it comes to exist. This logic "0" can be rewritten by a data bit applied to the data input terminal of the flip-flop. However, if the flip-flop has an associated pulse Ej
If a data bit is not provided to the flip-flop because it has not been enabled via the data latch, a logic "0" is stored in the corresponding bit position in the data latch. Therefore, data latch 3
The data word to be stored in one of 5 and 36 is
Formed into N-bit data words as required.

Therefore, the receiver can receive data words of any word length. If the word length of the received data word is less than N bits, the data word is formed into an N-bit data word. If the word length of the received data word is greater than N bits, the bits following the Nth bit are ignored. Since the most significant bit, MSB, is always received first (and transmitted first), there is no problem in ignoring the least significant bit (at the end of the data word).

In this example, the flip-flop 41-1 has a signal
Does not supply WSP. The reason is that in this example WSP
This is because the leading edge of =1 occurs almost simultaneously with the trigger to flip-flop 41. If it is necessary to supply the signal WSP to the flip-flop 41-1, there is a possibility that interference will occur between the WSP and the MSB to be stored.

To prevent interference between flip-flop reset and data latch storage, flip-flops 41-2 to 41-N are reset under the control of the trailing edge of WSP=1.

The advantage of using storage device 44 with an array of flip-flops 41-1 through 41-N is that the receiver always knows that the MSB is located in flip-flop 41-1. This is particularly advantageous if the receiver operates as a slave unit and the receiver does not know when the level change of the word selection signal occurs and therefore does not know how many bits the incoming word contains.

Of course, in the present invention, the storage device 44 that cooperates with the counter 33 and the decoder 34 is not limited to the above embodiment. Alternatively, the storage device may comprise a register that is selectively addressed, for example by a pointer bit in a shift register.

By using a digital audio device according to the invention, it is possible to transmit audio data words of different word lengths one after the other without loss of time between successive data words due to the fixed time length of the word selection signal. can. In the digital audio device according to the invention, the length of time between two successive level changes of the word selection signal is variable. The signal WSP generated by the transmitter and receiver based on the level change of the word selection signal enables internal data processing of the transmitter and receiver. If the signal WSP becomes equal to a logic "1" (FIG. 2d), the LSB of the data word has already been sent to the serial data line 6 (FIG. 2c).
The transmitter shift register is then ready to store a subsequent data word, which data word is stored under the control of WSP=1.

At the receiver, the LSB is stored simultaneously with WSP:=1. The entire data word is therefore present in the storage device and can therefore be transferred to one of the data latches 35 and 36 under control of WSP=1.
If WSP:=0, the storage device is enabled to store the MSB of the subsequent data word.

Effects of the Invention The effects of the present invention will be further described as follows.

(1) The word selection signal can be applied to data words of different bit lengths.

This means that it is not necessary to keep the word length constant in one data stream. This means that the transmission capacity of a certain transmission channel can be maximized. All bits to be transmitted are transmitted, and there is no need for gaps between successive words. Furthermore, in order to create a word selection signal of an appropriate length, only the control unit needs to know the actual word length. If the data is transmitted in frames consisting of so-called non-uniform length data words, the frame format need not be uniform. For example, start words may have different lengths and non-start words may have a different number from frame to frame. Another example is when the data consists of numbers. In the case of small numbers,
The initial zero digits can be removed to increase transmission capacity. This can also be applied to audio data, if the audio amplification factor is small,
The preceding zero can be suppressed. What is needed is to match the channel for the word selection signal and the length of the word selection signal.

(2) There is a well-defined time relationship between the word selection signal and the first bit of the data word to be transmitted.

By doing so, the slaved receiver easily adapts to the actual received word length. This also applies to slave-operated transmitters.

(3) When transmitting the most significant bit as the first bit, the receiver can easily know the position of the most significant bit. If desired, the principle of non-uniformity of successive words allows the master receiver to ignore one or more bits of lesser importance at its discretion. This means that there are advantages in both transmitting the most significant bit MSB first and transmitting the less significant bits first.

[Brief explanation of drawings]

FIG. 1 is a simplified block diagram showing a digital audio device to which the present invention can be applied, FIG. 2 is an explanatory diagram of an example of the operation of the data transmission device of the present invention, and FIG. 3 is a block diagram of an example of a word selection signal generator. FIG. 4 is a block diagram showing a preferred embodiment of an audio transmitter according to the present invention, and FIG. 5 is a block diagram showing a preferred embodiment of an audio receiver according to the present invention. 1...Central control unit, 2...Transmitter, 3...
...Receiver, 4...Clock line, 5...Word selection line, 6...Data transmission line, 10,1
1...Data latch, 12...Bus, 13...Shift register, 20...Microprocessor, 2
1... Clock device, 22... Counter, 23...
...Flip-flop, 24...Word selection signal generator, 30, 31...Flip-flop, 32...
...Exclusive OR gate, 33...Counter, 34
...Decoder, 35, 36...Data latch, 4
1-1 to 41-N...storage cell, 43...bus,
44...Storage device.

Claims (1)

[Scope of Claims] 1. A data transmission device comprising a transmitter and a receiver connected by a transmission line for serially transmitting a data word sequence in bits, and a control unit, the control unit comprising: - a series of clock pulses; clock means for generating a signal; - a word selection signal generator synchronized with said clock pulse signal and generating a two-level word selection signal, said two-level word selection signal having various values between successive level changes; and having time intervals selectable to different values, each time interval corresponding to an integer multiple of the successive clock signals, thereby respectively indicating different word lengths in said successive data words. said transmitter: - having output buffer means connected to said transmission line, by means of which temporarily stores an output data word and synchronizes said data word bit by bit with said clock pulse; and output by the level change, while terminating this output by switching directly to the output of the next data word of the successive data words, the receiver: - being supplied by the transmission line; input buffer means for receiving input data words, temporarily storing said input data words by bit-by-bit synchronization, and terminating said reception by controlling said level changes; , and is configured to directly switch to reception of the next data word after successive data words. 2 The first bit of any data word shall be at least one-half of the time for a new level change.
2. The data transmission device according to claim 1, further comprising delay means for delaying the output by a clock pulse period. 3. A data transmission device according to claim 2, wherein said first bit is the most significant bit of said data word. 4. A data transmission device according to claim 1, 2 or 3, wherein said input buffer means has an array of memory cells, and the sequential addressing of these storage cells is controlled by clock pulses. 5. A data transmission device according to claim 4, wherein the addressing is performed according to the successive state of the katanta, and the counter is incremented by the clock pulse and reset by the level change. . 6. The data transmission device according to claim 1, wherein the control unit is a part of the transmitter. 7. The data transmission device according to claim 1, wherein the control unit is a part of the receiver. 8. The data transmission device according to claim 1, wherein the control unit is separate from the transmitter and the receiver, and operates both as slaves. 9. Any one of claims 1 to 8, wherein the data word represents audio data.
The data transmission device described in Section 1.