JPH0446501B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a high-speed, large-output horizontal deflection circuit for high-definition displays and the like.

[Background of the invention]

As a conventional technology for high-speed switching such as the output transistor of a horizontal deflection circuit, switching elements such as bipolar transistors and power
A method is known in which devices with high switching speeds such as MOSFETs are connected in parallel. A feature of this circuit is that it enables high-speed switching operation that shortens turn-on time.

However, with this circuit, it is not possible to shorten the turn-off time required for the switching performance of the output transistor of the horizontal deflection circuit. Therefore, even if this circuit is used as an output circuit of a high-speed, large-output horizontal deflection circuit, switching loss cannot be reduced.

Hereinafter, problems that arise when a conventional horizontal deflection circuit is operated at high speed and high output will be specifically described.

FIG. 3 is a diagram showing a conventional horizontal deflection circuit. This circuit includes a horizontal synchronizing signal input terminal 17, a horizontal oscillation circuit 16, a horizontal deflection drive 15, a drive pulse input terminal 1, a bipolar transistor 2, a resonant capacitor 9, a damper diode 10,
It is composed of a horizontal deflection coil 11, an S-shaped capacitor 12, a chiyoke coil 13, and a power supply 14.
As shown in this figure, when bipolar transistor 2 is used as the output transistor to perform high-speed, high-output horizontal deflection operation with a horizontal deflection frequency of 130 kHz and a horizontal deflection output current of 22 A, the switching loss in bipolar transistor 2 is becomes a problem. FIG. 6a shows the waveforms of the collector current I _C and collector voltage V _C of the bipolar transistor 2 in the circuit shown in FIG. 3, and FIG. 6b shows the waveform of the collector loss P _C of the bipolar transistor 2.

The switching loss is determined by the product of the collector current I _C and the collector voltage V _C during the falling time of the bipolar transistor 2, and is proportional to the cube of the horizontal deflection frequency and proportional to the square of the falling time.
That is, if the horizontal deflection frequency is _H and the falling time is t, the switching loss P _S of the bipolar transistor 2 can be expressed as P _S =k· _H ³ ·t ² . Here, k is a constant determined by the deflection power index and the scanning line rate (horizontal scanning period/horizontal period).

When the above-mentioned high-speed, large-output horizontal deflection operation is performed using a high-speed switching transistor with a falling time t≈200 ns, the switching loss is calculated to be about 22.5 W. This value compares with the switching loss of the output transistor in a normal horizontal deflection circuit with a horizontal deflection frequency of 15.7kHz.
The calculation is more than 100 times larger.

In addition, in order to reduce this switching loss,
The switching loss when using a power MOSFET that can reduce the switching speed to 30 ns or less as an output transistor is calculated using the horizontal deflection frequency.
When calculated for 130kHz and horizontal deflection output current of 22A, it is found to be approximately 0.5W, which is much smaller than a bipolar transistor. However, high-voltage power MOSFETs have the disadvantage of having a higher on-resistance than bipolar transistors. At present, there are power MOSFETs with a withstand voltage of about 1200V that can be used as output transistors in horizontal deflection circuits.
The on-resistance is at least about 3Ω. When a power MOSFET with an on-resistance of about 3Ω is operated at the horizontal deflection frequency of 130 kHz and horizontal deflection output current of 22 A, the loss during the on-period of the power MOSFET is calculated using a triangular wave approximation of the drain current.
This is 60W, which is approximately three times the switching loss of a bipolar transistor. Therefore, as an application of conventional technology, the horizontal deflection operation described above has been achieved by connecting multiple power MOSFETs in parallel to lower the equivalent on-resistance. However, in order to reduce the loss due to on-resistance to about 10W and enable practical use as an output transistor, it is necessary to increase the number of parallel power MOSFETs to 6 transistors, which is difficult to achieve in conventional horizontal deflection circuits. There is a problem in that the circuit scale becomes extremely large.

[Purpose of the invention]

An object of the present invention is to reduce the loss of the output transistor, which is a problem in high-speed, large-output horizontal deflection circuits.

[Summary of the invention]

In order to achieve the above object, the present invention reduces the loss of the output transistor by taking advantage of the advantages of both a bipolar transistor with low on-resistance and a power MOSFET with high switching speed. Specifically, both a bipolar transistor and a power MOSFET are used in parallel as output transistors, and when both are on, most of the current flows through the bipolar transistor, which has a low on-resistance. When turning off the output transistor, the bipolar transistor is turned off first. As a result, the collector current that previously flowed through the bipolar transistor decreases, and the drain current of the power MOSFET increases. Next, the collector current of the bipolar transistor is reduced enough that most of the current is used as the power source.
Concentrate on MOSFET, then power MOSFET,
Turns off based on high-speed switching performance with fall time of 30ns or less. By performing the above operations, switching loss in bipolar transistors and
This reduces both losses due to the on-resistance of the power MOSFET.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.
In each figure, the same numbers are used to indicate the same movements.

FIG. 1 is a circuit diagram of a circuit showing a first embodiment of the present invention, and FIG. 2 shows a dotted line portion 47 in FIG.
A specific circuit diagram is shown. The horizontal deflection circuit shown in FIG. 1 has a transformer 3, a transformer 3', a power MOSFET 7, a diode 8, a delay circuit 24,
The difference is that a drive circuit 23, a phase difference detection circuit 25, and a drive voltage adjustment circuit 26 are provided.

The operation of this circuit will be explained below. In this circuit, the collector current of bipolar transistor 2 I _C
and the change in drain current I _D of power MOSFET 7,
It is detected as a change in voltage by transformers 3 and 3'. Then, the phase difference detection circuit 25 detects a timing difference between the falls of the collector current _IC and the drain current _ID , and in response to this timing difference, the drive voltage adjustment circuit 26 drives the bipolar transistor 2. The falling start time of the pulse is adjusted. A specific circuit for realizing this operation is shown in FIG. In this circuit, voltages generated on the secondary sides of transformers 3 and 3' are inputted from terminals 27 and 28, and are inverted and amplified by transistors 30 and 31. The signal is then shaped into a rectangular wave by inverters 32 and 33 equipped with a Schmitt trigger circuit. Then, by ORing the outputs of the inverters 32 and 33 and the horizontal oscillation pulse input from the terminal 29 using the OR gates 34 and 35,
As the outputs of the OR gates 34 and 35, rectangular waves having equal rising edges and different falling edges are obtained. Here, the fall of the output voltage of the OR gate 34 is
The fall of the drain current ID of the power MOSFET ₇ corresponds to the fall, and the fall of the output voltage of the OR gate 35 corresponds to the fall of the collector current I _C of the bipolar transistor 2. And OR
The difference between the output voltages of the gates 34 and 35 is amplified by a differential amplifier 36 and integrated by an integrator 37. Then, the output of the integrator 37 is the transistor 4
After the impedance is converted by 3, the signal is input to the comparator 44.

On the other hand, the horizontal oscillation pulse inputted from the terminal 29 is inverted and amplified by the transistor 38 and integrated by the resistor 39 and capacitor 40. Here, the diode 39' functions to speed up the discharge of the capacitor 40, and due to this function, the voltage
This makes the fall of V ₃₉ faster. Therefore, the turn-on timing of the bipolar transistor is always constant, and plays an important role in ensuring stable operation of the bipolar transistor 2. The voltage V ₃₉ is inverted and amplified by a transistor 41 and impedance-converted by a transistor 42 before being input to a comparator 44 . The comparator 44 compares the emitter voltage of the transistor 42 and the emitter voltage of the transistor 43 to generate the base voltage of the drive transistor 42. This base voltage operates the drive transistor 45 and the drive transformer 46, and drives the bipolar transistor 2. At this time, the falling start time of the output voltage of the comparator 44 is controlled by the emitter voltage of the transistor 43. In other words, the fall of the collector current I _C of bipolar transistor 2 and the power
By varying the timing of the fall of the drain current _ID of the MOSFET 7, the start time of the fall of the drive pulse of the bipolar transistor 2 can be controlled. Specifically, the fall of the drive pulse of the bipolar transistor 2 is set so that the fall of the drain current I _D is earlier than the fall of the collector current I _C , so that the fall of the collector current I _C is earlier. Advance the downhill start time. Conversely, if the fall of the drain current I _D is slower than the fall of the collector current I _C , the fall start time of the drive pulse of the bipolar transistor 2 is set so that the fall of the collector current I _C is delayed. delay.
By controlling the fall start time of the drive pulse in this way, the difference in the fall timing of the collector current I _C and the drain current I _C is converged to an optimal value, and the bipolar transistor 2 and The total loss occurring in the power MOSFET 7 is minimized.

However, the horizontal oscillation pulse input from the terminal 29 is amplified by the transistor 38, and the resistor 39
When integrating with the capacitor 40, a time delay occurs. Therefore, the rectangular wave output from the comparator 44 is always delayed in phase from the horizontal oscillation pulse. For this reason, if the power
When driving MOSFET7 with a drive pulse in the same phase as the horizontal oscillation pulse, the power MOSFET
_{7, the fall of the collector current I C of} the bipolar transistor 2 cannot be accelerated. Therefore, in the horizontal deflection circuit shown in FIG. 1, the horizontal oscillation circuit 16 and the power
A delay circuit 24 is provided between the drive circuits 23 of the MOSFET 7 to solve the above problem.

Regarding the circuits of FIGS. 1 and 2 explained above, the fall of the collector current I _C is the drain current I _D
FIGS. 7A, B, and C show waveforms of various parts when the falling edge of the signal is slightly earlier than the falling edge of the signal.

In FIG. 7, a is the output signal V ₁₆ , V ₁₆ ' waveform of the horizontal oscillation circuit 16, b is the output signal V ₂₄ waveform of the delay circuit 24, c is the gate drive signal V ₂₃ waveform of the power MOSFET, and d is the drive voltage. Adjustment circuit 2
6 output signal V ₂₆ waveform, e is the base drive signal V ₁ waveform of bipolar transistor 2, f is the drain current I _D waveform of power MOSFET 7, g is the collector current I _C waveform of bipolar transistor 2, h
is the composite current I _CD of drain current I _D and collector current I _C
shows. i, j, h, l, m are signal waveforms of each part in the drive voltage adjustment circuit 26, i is the terminal 2
9 is the signal V ₃₈ waveform obtained by inverting and amplifying the signal V ₁₆ inputted by the transistor 38, j is the signal V ₃₉ waveform obtained by integrating the signal V 38 by the resistor 39 and the capacitor 40, and h is the signal V ₃₉ waveform _. The signal V 41 obtained by inverting and amplifying the signal V ₄₁ by the transistor 41
waveform, l is the input signal V ₄₂ of the comparator 44,
V ₄₃ waveform is shown. n, o, p, q, r, s, t,
u is a signal waveform of each part in the phase difference detection circuit 25, and n is a signal obtained by inverting and amplifying the signal _V27 input from the terminal 27 by the transistor 30.
V ₃₀ waveform, o is the signal input from terminal 28 V ₂₈
The signal V ₃₁ waveform obtained by inverting and amplifying the signal by the transistor 31, p is the output signal of the inverter 32
V ₃₂ waveform, q is the output signal V ₃₃ waveform of the inverter 33, r is the output signal V ₃₄ waveform of the OR gate 34, s
is the output signal V ₃₅ waveform of the OR gate 35, t is the output signal V ₃₆ waveform of the differential amplifier 36, and u is the integrator 37
shows the output signal _V37 waveform.

The feature of using the first embodiment of the present invention shown in FIG. 1 is that it is possible to eliminate variations in storage time of bipolar transistors with respect to temperature. In other words, even if the accumulation time of the collector current I _C becomes longer and the timing of the fall of the collector current I _C is delayed, the automatic control will advance the fall start time of the drive pulse of the bipolar transistor 2 by the delayed time. control is required. For this reason,
The fall timing of the combined current _ICD waveform of the collector current _IC of the bipolar transistor 2 and the drain current ID of the power _MOSFET 7 remains unchanged. This utilizes the feature of the power MOSFET that the storage time of the drain current _ID of the power MOSFET 7 is very short, and the variation in the storage time with respect to temperature can be ignored.

Figure 6c shows the horizontal deflection circuit shown in Figure 1, with a horizontal deflection frequency of 130 kHz and a horizontal deflection output current of 22 A.
Bipolar transistor 2 when operated with
collector current I _C , collector voltage V _C , power
MOSFET7 drain current I _D , drain voltage
The waveforms of V _D and a composite current I _CD of the collector current I _C and the drain current _ID are shown. As shown in FIG. 6c, when the horizontal deflection circuit according to the present invention shown in FIG.
During the ON period of the MOSFET 7 (until _t1 in FIG. 6), most of the current is concentrated in the bipolar transistor 2, which has a low on-resistance. During the period from when the collector current I _C of the bipolar transistor 2 starts falling to when the power MOSFET 7 starts falling (t ₁ to _{t 2} in FIG. 6), the collector current I _C decreases and at the same time, Drain current _ID increases. Therefore, the composite current I _CD of the collector current I _C and the drain current _ID continues to increase.
Also, the drain voltage V _D at this time is the power
This is the on-voltage generated by the on-resistance (≒3Ω) of MOSFET 7, and the collector voltage V _C is the drain voltage V _D at this time plus the on-voltage of diode 8 (approximately
1V). Next, during the period from when the drain current _ID starts falling until the drain current _ID stops flowing ( _t2 to _t3 in FIG. 6), the current is concentrated in the power MOSFET 7. Therefore, the loss during this period is
The only loss is the switching loss of MOSFET 7, and this loss value is extremely small due to the high-speed switching performance described above. Figure 6d shows the losses P _C and P _D occurring in the bipolar transistor 2 and power MOSFET 7, and the total loss P _CD of both.
The waveforms are shown below. Comparing this figure with the loss P _C of the horizontal deflection circuit in which bipolar transistor 2 is the only output transistor shown in FIG _. It can be seen that the number is decreasing.

As a result of the above horizontal deflection operation, the loss due to the saturation voltage of bipolar transistor 2 is
If the voltage is 2V (constant) and the collector current I _C is approximated by a triangular wave, it will be approximately 4.1W. Also, the fall time t of the collector current I _C of bipolar transistor 2
(≈200ns), the collector voltage V _C is the sum of the on-voltage due to the on-resistance (≒3Ω) of the power MOSFET 7 and the on-voltage of the diode 8, so the switching loss of the bipolar transistor 2 is about 1.7W. On the other hand, the loss due to the on-resistance of the power MOSFET 7 is very small (approximately 0.1 W) during the period when the bipolar transistor 2 is on.
During the fall time of the collector current I _C of the bipolar transistor 2, a large current flows into the power MOSFET 7, so the loss that occurs during this period is approximately
It becomes 3.2W. Furthermore, the switching loss that occurs when the power MOSFET 7 is turned off is approximately 0.5W, as described above. Therefore, the total loss of the bipolar transistor 2 and power MOSFET 7 is about 10W, which is about the same as when six power MOSFETs are used in parallel. Note that the _fall time t (≒
200ns), it is expected that the horizontal linearity will be extremely deteriorated due to the on-resistance of the power MOSFET 7. However, for a short period of about 200 ns, it is sufficient to shorten the horizontal retrace period by about 200 ns, which is a level that does not pose much of a problem in practice.

FIG. 4 is a circuit diagram of a circuit showing a second embodiment of the present invention. Compared to the first embodiment of the present invention shown in FIG.
The difference is that 4' is used. In this case, the transformer 3, as the current detection means described in the first embodiment,
Compared to the case where 3' is used, there is an effect that the circuit scale can be reduced.

FIG. 5 is a circuit diagram of a circuit showing a third embodiment of the present invention. In this circuit, the drain current of power MOSFET 7, which originally has a high on-resistance, is
Collector current I _C of bipolar transistor 2 with small on-resistance detected by resistor 4' of about 0.1Ω
The change in is detected by transformer 3. Therefore, in the horizontal deflection circuit according to the third embodiment, the loss in the detection resistor is made smaller than that in the horizontal deflection circuit according to the second embodiment (see FIG. 4), and the circuit scale is reduced compared to the horizontal deflection circuit according to the first embodiment. This has the advantage that it can be made smaller than the deflection circuit (see FIG. 1).

〔Effect of the invention〕

According to the present invention, the loss of the output transistor, which is a problem in a high-speed, large-output horizontal deflection circuit, is reduced by connecting a bipolar transistor and a power MOSFET in parallel. Specifically, during the on-period of the output transistor, the main current flows through the bipolar transistor with low on-resistance, and during the fall time when the output transistor turns from on to off, the main current flows through the bipolar transistor with a high switching speed.
Both are driven so that the main current flows through the MOSFET. Therefore, switching loss in the bipolar transistor and loss due to on-resistance of the power MOSFET can be reduced at the same time. As a result,
The total loss of the bipolar transistor and power MOSFET, which are output transistors, can be reduced to less than half the loss when both are used alone.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a circuit showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific circuit indicated by a dotted line 47 in FIG. 1, and FIG. 3 is a circuit diagram of a conventional horizontal deflection circuit. 4 is a circuit diagram of a circuit showing a second embodiment of the present invention, FIG. 5 is a circuit diagram of a circuit showing a third embodiment of the present invention, and FIG. 6 is a conventional horizontal deflection circuit. and a waveform diagram for explaining the operation of the horizontal deflection circuit of the present invention. FIGS. 7A, B, and C are waveform diagrams showing waveforms of various parts in the circuit showing the first embodiment of the present invention. 2... Bipolar transistor, 3, 3'... Transformer, 4, 4'... Resistor, 7... Power MOSFET,
15...Drive circuit, 16...Horizontal oscillation circuit, 23
...drive circuit, 24 ... delay circuit, 25 ... phase difference detection circuit, 26 ... drive voltage adjustment circuit, 30,
31, 38, 41, 42, 43, 45...transistor, 32,33...inverter, 34,35...
OR gate, 36... differential amplifier, 37... integrator,
39...Resistor, 39'...Diode, 40...Capacitor, 44...Comparator, 46...Drive transformer.

Claims (1)

[Scope of Claims] 1. In a horizontal deflection circuit comprising a horizontal oscillation circuit, a horizontal deflection drive circuit connected to the horizontal oscillation circuit, and a horizontal deflection output circuit connected to the horizontal deflection drive circuit, the horizontal deflection output circuit is a bipolar transistor and a power source whose drain is connected to the collector of said bipolar transistor
a first current detection means connected to the bipolar transistor to detect a collector current of the bipolar transistor;
second current detection means connected to the MOSFET to detect the drain current of the power MOSFET; and second current detection means connected to the first current detection means and second current detection means to detect a phase difference between the collector current and the drain current. A horizontal deflection circuit comprising: a phase difference detection circuit; and a drive voltage adjustment circuit that adjusts a falling start time of a drive pulse of the bipolar transistor in response to an output of the phase difference detection circuit. 2. The horizontal deflection circuit according to claim 1, wherein the collector of the bipolar transistor and the drain of the power MOSFET are connected via a diode. 3. The horizontal deflection circuit according to claim 1 or 2, wherein the first current detection means and the second current detection means are constituted by a transformer. Deflection circuit. 4. The horizontal deflection circuit according to claim 1 or 2, wherein the first current detection means and the second current detection means are constituted by resistors. Deflection circuit.