JPH0450744B2 - - Google Patents
Info
- Publication number
- JPH0450744B2 JPH0450744B2 JP61057439A JP5743986A JPH0450744B2 JP H0450744 B2 JPH0450744 B2 JP H0450744B2 JP 61057439 A JP61057439 A JP 61057439A JP 5743986 A JP5743986 A JP 5743986A JP H0450744 B2 JPH0450744 B2 JP H0450744B2
- Authority
- JP
- Japan
- Prior art keywords
- metal substrate
- copper plate
- oxide film
- layer
- aluminum oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明は混成集積回路に関し、特に金属基板を
用いる混成集積回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and particularly to improvements in a hybrid integrated circuit using a metal substrate.
(ロ) 従来の技術
従来の混成集積回路は第3図に示す如く、セラ
ミツク基板10上に貴金属の粉末を含むペースト
の印刷、焼成により、厚膜11を形成し、半導体
チツプと基板回路の接続の際のハンダ流出を防止
するため絶縁材料からなるダム13を設け、厚膜
の配線上をハンダメツキ12で覆つた後、あらか
じめ配線端子にハンダバンプを形成した半導体チ
ツプ14の表面を基板10の方向に向け基板10
に接続していた。(b) Prior Art As shown in FIG. 3, a conventional hybrid integrated circuit is manufactured by printing and baking a paste containing noble metal powder on a ceramic substrate 10 to form a thick film 11, which connects a semiconductor chip and a circuit board. A dam 13 made of an insulating material is provided to prevent solder from flowing out during the process, and after covering the thick film wiring with solder plating 12, the surface of the semiconductor chip 14, on which solder bumps have been formed on the wiring terminals in advance, is placed in the direction of the substrate 10. board 10
was connected to.
上述した同様の技術は特開昭59−106140号公報
に記載されている。 A technique similar to that described above is described in Japanese Patent Application Laid-Open No. 59-106140.
しかし、上述した混成集積回路では基板にセラ
ミツク基板を用いるために機械的な強度が弱く、
高価で且つ放熱作用がわるい欠点があつた。 However, the above-mentioned hybrid integrated circuit uses a ceramic substrate, so its mechanical strength is weak.
It had the drawbacks of being expensive and having poor heat dissipation.
そこで、第3図に示す如く、熱伝導性良好なア
ルミニウム基板20を用い、その基板20表面に
酸化アルミニウム膜21を形成して、更にその上
面に絶縁樹脂22を介して導電路23を形成した
後、その導電路23上に半導体素子24をフエイ
スダウン接続して斯上した欠点を解決していた。
しかしながら、上述したアルミニウム基板20の
熱膨張率αが24×10-6/℃、これに対し半導体素
子24の熱膨張率αが2.4×10-6/℃と両者の熱
膨張率αが著しく異なり、温度サイクルによつて
半導体素子24とアルミニウム基板20とを接続
するハンダにクラツクが発生する危惧を有してし
た。 Therefore, as shown in FIG. 3, an aluminum substrate 20 with good thermal conductivity was used, an aluminum oxide film 21 was formed on the surface of the substrate 20, and a conductive path 23 was further formed on the upper surface with an insulating resin 22 interposed therebetween. Thereafter, the semiconductor element 24 was face-down connected on the conductive path 23 to solve the above-mentioned drawback.
However, the thermal expansion coefficient α of the aluminum substrate 20 mentioned above is 24×10 -6 /°C, whereas the thermal expansion coefficient α of the semiconductor element 24 is 2.4×10 -6 /°C, which is a significant difference between the two. There was a fear that cracks would occur in the solder connecting the semiconductor element 24 and the aluminum substrate 20 due to temperature cycling.
斯上した欠点を除去するために第3図に示す如
く、銅板31、インバー32、銅板31の3層構
造の金属基板30を発明した。この3層構造基板
30によれば、金属基板30の熱膨張率αを著し
く低下させることができ半導体素子の熱膨張率α
と緩和することができるので金属基板と半導体素
子とを接続するハンダにクラツクが発生しない利
点を有していた。 In order to eliminate the above-mentioned drawbacks, we invented a metal substrate 30 having a three-layer structure of a copper plate 31, an invar 32, and a copper plate 31, as shown in FIG. According to this three-layer structure substrate 30, the thermal expansion coefficient α of the metal substrate 30 can be significantly reduced, and the thermal expansion coefficient α of the semiconductor element can be significantly reduced.
This has the advantage that cracks do not occur in the solder that connects the metal substrate and the semiconductor element.
(ハ) 発明が解決しようとする問題点
しかしながら、斯上した銅板、インバー、銅板
の3層構造基板の銅板上に直接樹脂層および銅箔
を貼着すると銅板の表面が圧延工程によつて極め
て緻密で平滑に形成されるため、ハンダリフロー
工程において、金属基板を320℃前後まで加熱す
ると絶縁樹脂層からガスが発生した際、そのガス
によつて銅板、即ち、金属基板と樹脂層とが剥離
して銅箔を押し上げる欠点を有していた。(C) Problems to be Solved by the Invention However, when a resin layer and a copper foil are directly pasted on the copper plate of the above-mentioned three-layer structure board of copper plate, invar, and copper plate, the surface of the copper plate is extremely damaged by the rolling process. Because it is formed densely and smoothly, when the metal substrate is heated to around 320℃ during the solder reflow process, gas is generated from the insulating resin layer, and the gas causes the copper plate, that is, the metal substrate and the resin layer to separate. This had the disadvantage of pushing up the copper foil.
(ニ) 問題点を解決するための手段
本発明は上述した点に鑑みてなされたものであ
り、第1図に示す如く、銅板2、インバー3、銅
板2の3層構造からなる金属基板1上にアルミメ
ツキ層4を設け、そのアルミメツキ層4上に陽極
酸化により酸化アルミニウム膜5を設けて解決す
るものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and as shown in FIG. This problem is solved by providing an aluminized layer 4 thereon and providing an aluminum oxide film 5 on the aluminized layer 4 by anodic oxidation.
(ホ) 作用
この様に銅板2、インバー3、銅板2の3層構
造の金属基板1上にアルミメツキ層4および酸化
アルミニウム膜5を設けることにより、その酸化
アルミニウム膜5の表面が多孔質で形成されるた
め樹脂層6との密着力がよくなり、樹脂層6の剥
離を防止することができる。(e) Effect By providing the aluminized layer 4 and the aluminum oxide film 5 on the metal substrate 1 having the three-layer structure of the copper plate 2, the invar 3, and the copper plate 2 in this way, the surface of the aluminum oxide film 5 is formed to be porous. Therefore, adhesion with the resin layer 6 is improved, and peeling of the resin layer 6 can be prevented.
(ヘ) 実施例
以下に本発明を第1図に示した実施例に基づい
て詳細に説明する。(f) Examples The present invention will be explained in detail below based on the examples shown in FIG.
金属基板1は銅板2、インバー3、銅板2の
夫々の積層比を1:3:1の割合で10〜30ton/
cm2の圧力のローラでクラツド処理を行い、圧延工
程で所定の厚さになるまで伸した後、プレス加工
で所定の大きさに打抜き形成される。その基板1
表面に電解メツキ法等によつてアルミニウムをメ
ツキしアルミメツキ層4が形成され、更にその表
面に陽極酸化処理を行い酸化アルミニウム膜5が
形成される。インバー3はニツケル36%、鉄64%
の合金であり、その熱膨張率αは1.5×10-6/℃
である。 The metal substrate 1 is made of copper plate 2, invar 3, and copper plate 2, each with a lamination ratio of 1:3:1 of 10 to 30 tons/
Cladding treatment is performed using rollers with a pressure of cm 2 , and after stretching in a rolling process to a predetermined thickness, it is punched into a predetermined size using a press. The board 1
The surface is plated with aluminum by electrolytic plating or the like to form an aluminized layer 4, and the surface is further anodized to form an aluminum oxide film 5. Invar 3 is 36% nickel and 64% iron.
It is an alloy with a coefficient of thermal expansion α of 1.5×10 -6 /℃
It is.
金属基板1上にアルミメツキ層4および酸化ア
ルミニウム膜5を形成した後、その面上に絶縁樹
脂層6および導電路7となる銅箔が貼着される。
絶縁樹脂層4はエポキシ樹脂等が用いられる。次
に、銅箔を所定のパターンにエツチングして導電
路7を形成し、その導電路7上に半導体素子8の
バンブ電極と対応する位置にAuを蒸着してハン
ダをデイツプしハンダリフロー工程で金属基板1
を320℃°前後に加熱し金属基板1上に半導体素
子8をフエイスダウン接続する。 After forming an aluminized layer 4 and an aluminum oxide film 5 on a metal substrate 1, an insulating resin layer 6 and a copper foil serving as a conductive path 7 are adhered onto the surface thereof.
The insulating resin layer 4 is made of epoxy resin or the like. Next, a conductive path 7 is formed by etching the copper foil into a predetermined pattern, and Au is deposited on the conductive path 7 at a position corresponding to the bump electrode of the semiconductor element 8, and solder is dipped in the solder reflow process. Metal substrate 1
is heated to around 320°C, and the semiconductor element 8 is connected face-down onto the metal substrate 1.
斯る本発明に依れば、銅板2、インバー3、銅
板2の3層構造の金属基板1上にアルミメツキ層
を介して酸化アルミニウム膜5を設けることによ
り、その酸化アルミニウム膜5の表面が多孔質で
形成されるため絶縁樹脂層6が孔の中へ浸透し密
着性がよくなり、基板1を320℃前後に加熱して
も従来の様な樹脂層6の剥離が発生しない利点を
有する。 According to the present invention, by providing the aluminum oxide film 5 on the metal substrate 1 having the three-layer structure of the copper plate 2, the invar 3, and the copper plate 2 via the aluminized layer, the surface of the aluminum oxide film 5 is made porous. Since the insulating resin layer 6 is made of a solid material, the insulating resin layer 6 penetrates into the holes and has good adhesion, and has the advantage that the resin layer 6 does not peel off as in the conventional case even if the substrate 1 is heated to around 320°C.
(ト) 発明の効果
上述の如く、本発明に依れば、銅板、インバ
ー、銅板の3層構造の金属基板上にアルミメツキ
層を介して酸化アルミニウム膜を設けることによ
り、酸化アルミニウム膜の表面に形成された孔に
樹脂が浸透するので、酸化アルミニウム膜と樹脂
層との密着が強固になり、ハンダリフロー工程に
おいて基板を加熱した際、樹脂層からガスが発生
しても従来発生していた樹脂層の剥離を防止する
ことができる。(G) Effects of the Invention As described above, according to the present invention, by providing an aluminum oxide film on a metal substrate having a three-layer structure of a copper plate, an invar plate, and a copper plate via an aluminized layer, the surface of the aluminum oxide film can be coated. Since the resin penetrates into the holes formed, the adhesion between the aluminum oxide film and the resin layer becomes strong, and even if gas is generated from the resin layer when the board is heated during the solder reflow process, the resin will not be released, which was previously the case. Peeling of layers can be prevented.
第1図は本発明の実施例を示す断面図、第2図
乃至第4図は従来例を示す断面図である。
1……金属基板、2……銅板、3……インバー
FIG. 1 is a sectional view showing an embodiment of the present invention, and FIGS. 2 to 4 are sectional views showing a conventional example. 1...Metal board, 2...Copper plate, 3...Invar
Claims (1)
設けられた3層構造の金属基板と、該金属基板上
に設けられたアルミメツキ層と、該アルミメツキ
層上に設けられた酸化アルミニウム膜と、該酸化
アルミニウム膜上に絶縁樹脂を介して設けられた
所望形状の導電路と、該導電路上に複数の半導体
素子が設けられたことを特徴とする混成集積回
路。1. A metal substrate with a three-layer structure in which both sides are made of copper plates and invar is provided between them, an aluminized layer provided on the metal substrate, an aluminum oxide film provided on the aluminized layer, and the oxidized 1. A hybrid integrated circuit comprising a conductive path of a desired shape provided on an aluminum film via an insulating resin, and a plurality of semiconductor elements provided on the conductive path.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61057439A JPS62214632A (en) | 1986-03-14 | 1986-03-14 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61057439A JPS62214632A (en) | 1986-03-14 | 1986-03-14 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62214632A JPS62214632A (en) | 1987-09-21 |
| JPH0450744B2 true JPH0450744B2 (en) | 1992-08-17 |
Family
ID=13055686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61057439A Granted JPS62214632A (en) | 1986-03-14 | 1986-03-14 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62214632A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5130274A (en) * | 1991-04-05 | 1992-07-14 | International Business Machines Corporation | Copper alloy metallurgies for VLSI interconnection structures |
| DE4334127C1 (en) * | 1993-10-07 | 1995-03-23 | Mtu Muenchen Gmbh | Metal core circuit board for insertion into the housing of an electronic device |
| KR101204191B1 (en) * | 2010-11-02 | 2012-11-23 | 삼성전기주식회사 | Heat-dissipating substrate |
| DE102015111667B4 (en) * | 2015-07-17 | 2025-11-06 | Rogers Germany Gmbh | Substrate for electrical circuits and methods for producing such a substrate |
| CN210157469U (en) * | 2018-12-29 | 2020-03-17 | 广东生益科技股份有限公司 | Metal base copper clad laminate |
-
1986
- 1986-03-14 JP JP61057439A patent/JPS62214632A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62214632A (en) | 1987-09-21 |
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