JPH0450743B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and more particularly to an improvement in the substrate structure of a hybrid integrated circuit in which semiconductor elements are connected face-down on a metal substrate.

(b) Prior Art As shown in FIG. 3, a conventional hybrid integrated circuit is manufactured by printing and baking a paste containing noble metal powder on a ceramic substrate 10 to form a thick film 11, which connects a semiconductor chip and a circuit board. A dam 13 made of an insulating material is provided to prevent solder from flowing out during the process, and after covering the thick film wiring with solder plating 12, the surface of the semiconductor chip 14, on which solder bumps have been formed on the wiring terminals in advance, is placed in the direction of the substrate 10. board 10
was connected to.

A technique similar to that described above is described in Japanese Patent Application Laid-Open No. 59-106140.

However, the above-mentioned hybrid integrated circuit uses a ceramic substrate, so its mechanical strength is weak.
It had the drawbacks of being expensive and having poor heat dissipation. Therefore, as shown in FIG. 3, an aluminum substrate 20 with good thermal conductivity was used, an aluminum oxide film 21 was formed on the surface of the substrate 20, and a conductive path 23 was further formed on the upper surface with an insulating resin 22 interposed therebetween. Thereafter, the substrate 20 is heated to 360 DEG to 370 DEG C. by solder reflow, and the semiconductor element 24 is connected face-down onto the conductive path 23, thereby solving the above-mentioned drawbacks.

(c) Problems to be Solved by the Invention As described above, the above-mentioned drawbacks can be solved by using an aluminum substrate. However, the thermal expansion coefficient of the aluminum substrate α24×10 ^-6 /℃,
Since the coefficient of thermal expansion α of the semiconductor element is α2.4×10 ^-6 /℃ and the coefficient of thermal expansion α of the two is significantly different, there is a risk that cracks may occur in the brazing material that connects the semiconductor element and the aluminum substrate due to temperature cycling. Was.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and as shown in FIG. This problem is solved by providing an invar 3 having a low coefficient of thermal expansion α between them to reduce the difference between the coefficient of thermal expansion α of the metal substrate 1 and the coefficient of thermal expansion α of the semiconductor element 7.

(e) Effect By forming the metal substrate 1 into a three-layer structure of aluminum 2, invar 3, and aluminum 2, the thermal expansion coefficient α of the metal substrate 1 and α of the semiconductor element 7 can be reduced.
can be alleviated.

(f) Examples The present invention will be explained in detail below based on the examples shown in FIG. The metal substrate 1 is made by cladding each of the aluminum plate 2, the invar 3, and the aluminum plate 2 in a ratio of 1:3:1 using a roller under a pressure of 10 to 30 tons/ ^cm2 , and then a predetermined thickness is obtained by a rolling process. After stretching it until it becomes , it is punched out to a predetermined size using a press. An aluminum oxide film 4 is formed on the surface of the substrate 1 by anodizing. Invar 3 is an alloy of 36% nickel and 64% iron, and its coefficient of thermal expansion α is 1.5×10 ⁻⁶ /°C.

After forming the alumite layer 4 on the metal substrate 1,
A conductive path 6 is formed on the upper surface with an insulating resin layer 5 interposed therebetween. The insulating resin layer 5 is made of epoxy resin or the like, and the resin and copper foil, which will become the conductive path 6, are integrated and adhered to the substrate 1, and the copper foil is etched into a predetermined pattern to form the conductive path 6. It is formed. Au is vapor deposited on the conductive path 6 at a position corresponding to the bump electrode of the semiconductor element 7, solder is dipped to form a bump electrode, and the substrate 1 is rotated 360° in a solder reflow process.
The semiconductor element 7 is connected face down onto the metal substrate 1 by heating to ~370°.

According to the present invention, the metal substrate 1 has a three-layer structure consisting of an aluminum plate 2, an invar 3, and an aluminum plate 2, in which the ratio is 1:3:1, so that the coefficient of thermal expansion α of the metal substrate 1 can be reduced. is 6.6×10 ^-6 /℃, which can reduce the difference with the thermal expansion coefficient α2.4×10 -6 /℃ of the semiconductor element 7, so that it is possible to reduce the difference between the thermal expansion coefficient α2.4×10 ^-6 /℃ of the semiconductor element 7 and the brazing material of the connection part due to the temperature cycle that conventionally occurs. This has the advantage that cracks do not occur.

As another example, if the lamination ratio of the metal substrate 1 is set to 1:1:1 and 1:2:1, the thermal expansion coefficient α of the former is 11.9×10 ^-6 /°C, and the thermal expansion coefficient α of the latter is 8.3.
×10 ^-6 /°C, and the lamination ratio may be 1:1:1, 1:2:1 or 1:3:1, but the preferred lamination ratio is 1:3:1.

(G) Effects of the Invention As described above, according to the present invention, by forming the metal substrate into a three-layer structure of aluminum, invar, and aluminum, a coefficient of thermal expansion α close to that of a semiconductor element can be obtained. Therefore, cracks do not occur in the brazing material that connects the semiconductor element and the metal substrate, and deterioration of the brazing material can also be prevented.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing a conventional example. 1... Metal substrate, 2... Aluminum plate, 3...
...Invar, 4...Aluminum oxide film, 5...
Insulating resin layer, 6... conductive path, 7... semiconductor element.

Claims (1)

[Scope of Claims] 1. A hybrid integrated circuit comprising: a metal substrate, a conductive path of a desired shape provided on the metal substrate via an insulating resin layer, and a plurality of semiconductor elements fixed on the conductive path; A hybrid integrated circuit characterized in that both sides of a metal substrate are made of aluminum plates, and a metal having a coefficient of thermal expansion lower than that of aluminum is provided between the aluminum plates to reduce the difference in coefficient of thermal expansion with the semiconductor element. . 2. The hybrid integrated circuit according to claim 1, characterized in that invar is used as the metal having the thermal expansion coefficient.