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JPH0450767B2 - - Google Patents
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JPH0450767B2 - - Google Patents

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Publication number
JPH0450767B2
JPH0450767B2 JP61173660A JP17366086A JPH0450767B2 JP H0450767 B2 JPH0450767 B2 JP H0450767B2 JP 61173660 A JP61173660 A JP 61173660A JP 17366086 A JP17366086 A JP 17366086A JP H0450767 B2 JPH0450767 B2 JP H0450767B2
Authority
JP
Japan
Prior art keywords
circuit
power
amplifier
signal
gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61173660A
Other languages
Japanese (ja)
Other versions
JPS6211170A (en
Inventor
Kohei Ishizuka
Yasuhiro Kita
Shigemichi Maeda
Kazuhiko Takaoka
Garo Kokuryo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Kokusai Denki Electric Inc
Original Assignee
Hitachi Denshi KK
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK, Hitachi Ltd filed Critical Hitachi Denshi KK
Priority to JP17366086A priority Critical patent/JPS6211170A/en
Publication of JPS6211170A publication Critical patent/JPS6211170A/en
Publication of JPH0450767B2 publication Critical patent/JPH0450767B2/ja
Granted legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電力検出回路を用いた利得制御回路、
特に、通信における変復調装置(モデム)の入力
増幅回路への入力電力を測定し、モデムの起動な
らびに上記増幅回路の自動利得制御を行なう回路
の構成に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a gain control circuit using a power detection circuit;
In particular, the present invention relates to the configuration of a circuit that measures the input power to the input amplifier circuit of a modem in communication, starts the modem, and automatically controls the gain of the amplifier circuit.

〔従来の技術〕[Conventional technology]

従来の利得制御回路の基本構成を第1図に示
す。入力アナログ信号は入力端子1を経て可変利
得増幅器3で所定の増幅度で増幅され、出力端子
2を経てモデム等の信号処理回路(図示せず)に
加えられる。増幅器3の出力の1部は電力検出回
路4で電力が検出される。この検出された電力に
よつて利得設定回路5で必要な利得制御信号を発
生し、上記可変利得増幅器へ制御信号を供給す
る。利得制御信号の一部は電力検出回路4に加え
られ、電力検出の演算に使用される。端子6には
設定したい基準の電力を信号として加える。
The basic configuration of a conventional gain control circuit is shown in FIG. An input analog signal passes through an input terminal 1, is amplified at a predetermined amplification degree by a variable gain amplifier 3, and is applied to a signal processing circuit (not shown) such as a modem through an output terminal 2. The power of a portion of the output of the amplifier 3 is detected by a power detection circuit 4. The detected power is used to generate a necessary gain control signal in the gain setting circuit 5, and the control signal is supplied to the variable gain amplifier. A portion of the gain control signal is applied to the power detection circuit 4 and used for power detection calculations. A desired reference power is applied to terminal 6 as a signal.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第1図の利得制御回路において、可変利得増幅
器3をデシベルリニアにデイジタル信号入力によ
り可変できるものとすると、電力検出回路4の出
力も、デシベル表示のデイジタル化された電力信
号であることが望ましい。この場合デシベル変換
回路は演算時間の短縮をはかるため読み出し専用
メモリ(ROM)で構成されることが多くある。
この手法によると、受信した電力のダイナミツク
レンジが広いと、その分だけROM容量の増加ま
たは演算時間が増大してしまう欠点があつた。
In the gain control circuit of FIG. 1, if the variable gain amplifier 3 can be varied linearly in decibels by digital signal input, it is desirable that the output of the power detection circuit 4 also be a digitized power signal expressed in decibels. In this case, the decibel conversion circuit is often configured with a read-only memory (ROM) in order to reduce calculation time.
This method has the disadvantage that if the dynamic range of the received power is wide, the ROM capacity or calculation time increases accordingly.

したがつて、本発明の目的は受信した電力のダ
イナミツクレンジが広い場合においても、ROM
容量の増加または、演算時間の増大をすることな
く、高速に利得が制御された精度よくデシベル表
示のデイジタル化した電力信号を得ることができ
る利得制御回路を提供することにある。
Therefore, an object of the present invention is to maintain the ROM even when the received power has a wide dynamic range.
It is an object of the present invention to provide a gain control circuit capable of obtaining a digitized power signal with high-speed gain control and accurate decibel display without increasing capacity or calculation time.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は上記目的を達成するため、電力検出回
路4を浮動小数点演算方式で実現し、仮数部と指
数部を用いてダイナミツクレンジの広い電力値を
有効的に表現し、この値を用いてデシベル変換を
行い、このデシベル表示の値が示す可変利得増幅
器の出力電力から現在の利得制御信号の示す利得
を引算して増幅器入力電力を求めるとともに、必
要な出力電力から求められた入力電力を引算して
利得制御信号とすることを特徴とするものであ
る。
In order to achieve the above object, the present invention implements the power detection circuit 4 using a floating point arithmetic method, effectively expresses a power value with a wide dynamic range using a mantissa and an exponent, and uses this value to effectively express a power value with a wide dynamic range. Perform decibel conversion, subtract the gain indicated by the current gain control signal from the output power of the variable gain amplifier indicated by this decibel display value to find the amplifier input power, and calculate the input power determined from the required output power. The feature is that the gain control signal is obtained by subtraction.

〔作用〕[Effect]

上記構成によれば、出口電力の制御の精度を決
める入力電力の検出値が浮動小数点で求められる
ので入力電力が広いダイナミツクレンジを持つに
かかわらず量子化誤差が小さく、さらに所望の出
力電力と検出された入力電力と差が直接増幅器の
利得であるので高速に精度良く利得が制御でき
る。
According to the above configuration, since the input power detection value that determines the accuracy of output power control is obtained as a floating point number, the quantization error is small even though the input power has a wide dynamic range. Since the difference from the detected input power is directly the gain of the amplifier, the gain can be controlled quickly and accurately.

〔実施例〕〔Example〕

以下、本発明による利得制御回路をデータ伝送
のモデムに適用した一実施例を第2図により詳細
に説明する。入力端子1に加えられたアナログ信
号はデシベルリニアに利得を可変できる可変利得
増幅器3によつて増幅され、アナログ・デイジタ
ルA/D変換器7でデイジタル信号に変換され
る。この信号は端子2よりモデムの復調回路に加
えられ、他の一端は2乗回路8に加えられたの
ち、平均化回路9で複数サンプル値から平均電力
に対応する信号に変換され、デシベル変換回路1
0でデシベル表示の信号に変換される。本発明は
デシベル変換回路10の入力である平均電力に対
応する信号を浮動小数点形式で表示し、デシベル
変換を行なうことを特徴とするものである。
Hereinafter, an embodiment in which a gain control circuit according to the present invention is applied to a data transmission modem will be described in detail with reference to FIG. The analog signal applied to the input terminal 1 is amplified by a variable gain amplifier 3 whose gain can be varied linearly in decibels, and converted into a digital signal by an analog/digital A/D converter 7. This signal is applied to the demodulation circuit of the modem from terminal 2, and the other end is applied to the squaring circuit 8, after which it is converted by the averaging circuit 9 into a signal corresponding to the average power from the multiple sample values, and then the decibel conversion circuit 1
0, it is converted to a signal expressed in decibels. The present invention is characterized in that a signal corresponding to the average power input to the decibel conversion circuit 10 is displayed in a floating point format and decibel conversion is performed.

すなわち、平均電力に対応する信号を Po′=a×2b(mw) なる浮動小数点形式であらわせば、このデシベル
変換器10の出力Poは次の如くなる。
That is, if the signal corresponding to the average power is expressed in a floating point format as Po'=a×2 b (mw), the output Po of this decibel converter 10 will be as follows.

Po=10logPo′(mw)/1(mw) =10loga+3b(dBm) この結果と、上記可変利得増幅器3に加える利得
制御の信号とにより、信号電力計算回路11は、
入力信号の電力値をデイジタル値で求めることが
できる。すなわち可変利得増幅器の利得をA
(dB)とすれば入力信号の電力値Piは Pi=Po−A(dBm) で求めることができる。
Po=10logPo′(mw)/1(mw)=10loga+3b(dBm) Based on this result and the gain control signal applied to the variable gain amplifier 3, the signal power calculation circuit 11 calculates the following:
The power value of the input signal can be determined as a digital value. In other words, the gain of the variable gain amplifier is A
(dB), the power value Pi of the input signal can be found as Pi = Po - A (dBm).

さらに必要な出力電力PoをPrefとすれば、 検出したPiから Pref−Pi=Aref を利得設定回路5により決定し、必要な利得制御
信号を可変利得増幅器に加えれば、必要な電力
Prefに相当する入力の増幅された信号を得ること
ができ、自動利得制御系を構成することができ
る。Prefは端子6より利得設定回路5に入力す
る。
Furthermore, if the required output power Po is Pref, the gain setting circuit 5 determines Pref−Pi=Aref from the detected Pi, and the necessary gain control signal is applied to the variable gain amplifier to obtain the required power.
An amplified input signal corresponding to Pref can be obtained, and an automatic gain control system can be constructed. Pref is input to the gain setting circuit 5 from the terminal 6.

〔発明の効果〕〔Effect of the invention〕

次に本発明による浮動小数点方式の効果につい
て述べる。第3図はデシベル変換回路10へのデ
イジタル入力の電力値が固定小数点方式による仮
数部8ビツトの場合と、本発明の浮動小数点方式
による仮数部5ビツト、指数部3ビツトの場合に
ついて比較した一例である。
Next, the effects of the floating point system according to the present invention will be described. FIG. 3 is an example of a comparison between the case where the power value of the digital input to the decibel conversion circuit 10 is based on the fixed-point system with an 8-bit mantissa, and the case where the digital input power value is based on the floating-point system of the present invention with a 5-bit mantissa and 3-bit exponent. It is.

この比較はデシベル変換回路10への入力どど
ちらも8ビツトの場合について行なつているが、
第3図より明らかな如く、浮動小数点方式がより
幅広い範囲まで電力値を取り扱うことができる。
また、仮数部の最小ビツトによる誤差は電力値が
大きい場合、固定小数点方式によるものが優れて
いるが、入力電力の小さい場合には固定小数点方
式による誤差が非常に増大する。これに対し、浮
動小数点方式は、誤差がほぼ一定であり、利得制
御に用いる回路として非常に有効である。
This comparison is performed when both inputs to the decibel conversion circuit 10 are 8 bits.
As is clear from FIG. 3, the floating point system can handle power values over a wider range.
Furthermore, when the power value is large, the error caused by the minimum bit of the mantissa part is better when the fixed point method is used, but when the input power is small, the error caused by the fixed point method increases significantly. On the other hand, the floating point method has a nearly constant error and is very effective as a circuit used for gain control.

また、固定小数点方式で電力値の変換限界を第
3図に述べた浮動小数点方式と同等にするために
は、デシベル変換回路10へのデイジタル入力の
ビツト数をさらに4ビツト増加する必要がある。
この入力ビツト数の増大は、例えばデシベル変換
を、読み出し専用メモリ(ROM)を用いて行な
う場合、仮にデシベルの電力値を8ビツト(1バ
イト)で表現すると、ROM容量は、256バイト
から4096バイトに飛躍的に増大する。また、他の
ハードウエアで実現する場合には、回路規模が非
常に大きくなる欠点がある。
Furthermore, in order to make the power value conversion limit in the fixed point system equivalent to that in the floating point system described in FIG. 3, it is necessary to further increase the number of bits of the digital input to the decibel conversion circuit 10 by 4 bits.
This increase in the number of input bits means that, for example, when performing decibel conversion using read-only memory (ROM), if the decibel power value is expressed in 8 bits (1 byte), the ROM capacity will increase from 256 bytes to 4096 bytes. will increase dramatically. Furthermore, if it is implemented using other hardware, there is a drawback that the circuit scale becomes extremely large.

この浮動小数点方式による演算処理は、ここで
述べた電力値のデシベル変換回路のみでなく、こ
の利得制御系の他の演算回路にも用いることがで
きる。
Arithmetic processing using this floating point system can be used not only for the power value decibel conversion circuit described here, but also for other arithmetic circuits in this gain control system.

以上実施例によつて方式を説明したが、本発明
は上記実施例に限定されるものではない。2乗回
路、平均化回路、デシベル変換回路、信号電力演
算回路、利得設定回路等は、専用の回路で構成す
る他、マイクロコンピユータ等の信号処理装置あ
るいは他のデイジタル処理装置と組合せて構成で
きることは明らかである。
Although the system has been described above with reference to embodiments, the present invention is not limited to the above embodiments. The squaring circuit, averaging circuit, decibel conversion circuit, signal power calculation circuit, gain setting circuit, etc. can be configured with dedicated circuits, or can be configured in combination with a signal processing device such as a microcomputer or other digital processing device. it is obvious.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は利得制御回路の基本的な構成図、第2
図は本発明による利得制御回路の実施例の構成
図、第3図は本発明による浮動小数点方式の効果
を示す線図である。 1……入力端子、2……出力端子、3……可変
利得増幅器、4……電力検出回路、5……利得設
定回路、6……利得設定信号入力端子、7……
A/D変換器、8……2乗回路、9……平均化回
路、10……デシベル変換回路、11……信号電
力計算回路。
Figure 1 is the basic configuration diagram of the gain control circuit, Figure 2 is the basic configuration diagram of the gain control circuit.
This figure is a block diagram of an embodiment of the gain control circuit according to the present invention, and FIG. 3 is a diagram showing the effect of the floating point system according to the present invention. DESCRIPTION OF SYMBOLS 1...Input terminal, 2...Output terminal, 3...Variable gain amplifier, 4...Power detection circuit, 5...Gain setting circuit, 6...Gain setting signal input terminal, 7...
A/D converter, 8... Square circuit, 9... Averaging circuit, 10... Decibel conversion circuit, 11... Signal power calculation circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 可変利得増幅器と、上記増幅器の利得を制御
するための利得設定回路と、上記増幅器の出力信
号と上記利得設定回路の出力信号から上記増幅器
の入力電力を検出する電力検出回路を備え、上記
電力検出回路は上記増幅器の出力信号をアナロ
グ・デイジタル変換するA/D変換器と、上記
A/D変換器の出力から上記増幅器の出力電力の
平均値を浮動小数点のデイジタル信号として求め
る演算回路と、上記演算回路の出力をデシベル信
号に変換するデシベル変換器と、上記デシベル変
換器の出力から上記利得設定回路の出力信号を引
算する回路とで構成され、上記利得設定回路は上
記増幅器の出力信号として必要な電力値から上記
電力検出回路の出力信号を引算することによつて
上記増幅器の利得制御信号を得るように構成され
たことを特徴とする自動利得制御回路。
1 comprising a variable gain amplifier, a gain setting circuit for controlling the gain of the amplifier, and a power detection circuit for detecting the input power of the amplifier from the output signal of the amplifier and the output signal of the gain setting circuit, The detection circuit includes an A/D converter that converts the output signal of the amplifier from analog to digital, and an arithmetic circuit that calculates the average value of the output power of the amplifier as a floating point digital signal from the output of the A/D converter. It consists of a decibel converter that converts the output of the arithmetic circuit into a decibel signal, and a circuit that subtracts the output signal of the gain setting circuit from the output of the decibel converter, and the gain setting circuit receives the output signal of the amplifier. An automatic gain control circuit characterized in that the automatic gain control circuit is configured to obtain a gain control signal for the amplifier by subtracting the output signal of the power detection circuit from the power value required for the automatic gain control circuit.
JP17366086A 1986-07-25 1986-07-25 automatic gain control circuit Granted JPS6211170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17366086A JPS6211170A (en) 1986-07-25 1986-07-25 automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17366086A JPS6211170A (en) 1986-07-25 1986-07-25 automatic gain control circuit

Publications (2)

Publication Number Publication Date
JPS6211170A JPS6211170A (en) 1987-01-20
JPH0450767B2 true JPH0450767B2 (en) 1992-08-17

Family

ID=15964734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17366086A Granted JPS6211170A (en) 1986-07-25 1986-07-25 automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPS6211170A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2691019B2 (en) * 1989-05-10 1997-12-17 株式会社日立製作所 White balance device
US6364086B1 (en) 1998-05-29 2002-04-02 Rexroth Star Gmbh Chain of rolling elements chain arrangement
US6424221B1 (en) * 2000-06-19 2002-07-23 Advanced Micro Devices, Inc. Programmable gain amplifier for use in data network
DE20101760U1 (en) 2001-02-01 2002-06-13 Rexroth Star Gmbh A roller chain
US7333567B2 (en) * 2003-12-23 2008-02-19 Lucent Technologies Inc. Digital detector utilizable in providing closed-loop gain control in a transmitter

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6030446B2 (en) * 1976-11-26 1985-07-16 シャープ株式会社 High-speed writing digital automatic gain control circuit
JPS608525B2 (en) * 1978-08-29 1985-03-04 松下電器産業株式会社 Magnetic recording and reproducing method
JPS55117318A (en) * 1979-03-02 1980-09-09 Matsushita Electric Ind Co Ltd Level converting device
JPS56117413A (en) * 1980-02-21 1981-09-14 Nec Corp Digital agc system
JPS58108809A (en) * 1981-12-23 1983-06-29 Fujitsu Ltd Digital agc circuit

Also Published As

Publication number Publication date
JPS6211170A (en) 1987-01-20

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