JPH045272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a semiconductor device such as an EPROM in which a chip housed in a package is exposed to light.

[Technical background of the invention and its problems]

The number of external lead-out terminals provided on an integrated circuit (IC) package is preferably as small as possible from the standpoint of package miniaturization and other aspects. Various means have been considered for reducing the number of external lead-out terminals, one of which is a circuit as shown in FIG. This circuit corresponds to the one disclosed in Japanese Patent Application No. 54-23204 by the same applicant, but a brief explanation will be given here.

Terminal 10 is connected to the drain and gate of enhancement type MOS transistor T10.
The source of transistor T10 is connected to node A. Node A is connected to potential V _c via the source and drain of depletion type MOS transistor T11. Node A is also connected to node D via the drain and source of depletion type MOS transistor T12. The gate of transistor T12 is connected to node D. Node D is further connected to potential V _s via the drain and source of enhancement type MOS transistor T13. This potential V _s is
Usually the potential of the semiconductor substrate (substrate), for example zero.

When the terminal 10 handles a signal of 0 to _Vc level, the gate end B of the transistor T11 is at logic "1", that is, the potential _Vc (for example, 5V). At this time, consider the potential of node A to be V _c ,
Let the gate threshold voltage of transistor T10 be V _th10 . Then, when <V _c +V _th10 , the transistor T10 is cut off and the node A is electrically disconnected from the terminal 10. In this case, a signal having a potential of 0 or _Vc is generated at the node D depending on the logic level of the gate terminal C of the transistor T13.

When the terminal 10 handles the signal _Vp , the gate terminal B becomes logic "0". Here, when the gate threshold voltage of the transistor T11 is V _th11 ′ and the voltage at the gate terminal B is V _GB , the following formula; V _p −V _th10 V _GB −V _th11 V _c V _GB −V _th11 is satisfied. Then, transistor T11 is cut off. Then, when the gate terminal C of the transistor T13 is logic "0", the potential of the node D becomes
V _p −V _th10 , and gate end C is logic “1”
When , the potential of node D becomes 0.

In the circuit of FIG. 1, the transistor T10 is turned on/off depending on the potential difference between the node A and the terminal 10.
It will be turned off. By this on/off, terminal 10
can be used as a terminal that handles two types of signals V _p .

When the terminal 10 is used as a signal terminal, the transistor T10 is turned off. Therefore, for example, the fan-out of other circuits connected to the terminal 10 is not reduced by the circuit current on the node A side. Typically, in a MOSIC, the current upper limit of the signal input circuit, that is, the current capability, is about ±10 μA. Therefore, it is desirable that the leakage current flowing from the terminal 10 to the node A or from the node A to the terminal 10 when the transistor T10 is off is sufficiently smaller than the above current capacity. If the transistor T10 is completely turned off, the above leakage current will not be a problem. However, when light enters the PN junction of the transistor T10, the leakage current may become large enough to be ignored.

As described above, a typical semiconductor device in which light may enter the P-N junction inside an IC is an ultraviolet erasable EPROM (Erasable Programmable
Read-Only Memory). In EPROM,
In order to irradiate the internal IC chip with ultraviolet rays, a package having a translucent portion or window on the IC chip is used. If such an EPROM is used without being shielded from external light such as indoor lighting,
P-N in IC chip including transistor T10
Light shines on the joint. Then, a junction leakage current (photocurrent) due to this light begins to flow through the terminal 10.

FIG. 2 is a graph illustrating the relationship between the junction leakage current and the illuminance of incident light. Figure 3 is the second
The measurement circuit for the graph in the figure is shown. In Figure 2, the reverse bias voltage V _D for the P-N junction is
is the parameter, the solid line indicates V _D =8V, and the broken line indicates V _D =0V. Figure 2 shows the leakage current I _L per 1 μm ² of light receiving area. Therefore,
In the case of a semiconductor device such as an EPROM which has a large substantial light-receiving area, when the illuminance is high, the total leakage current I _L becomes large enough to not be ignored.
For example, depending on the pattern layout, in the case of a 32K-bit EPROM, the substantial light-receiving area is approximately 1.5×10 ⁵ μm ² . in this case,
For example, if we take the case of illuminance 3000 lux from Fig. 2, I _L will be 4×10 ^-11 (A/μm ² ), so
Total leakage current is 1.5×10 ⁵ ×4×10 ^-11 = 6
×10 ^-6 (A) = 6 (μA). This leakage current of 6 μA is too large to be ignored compared to the current capacity (±10 μA) mentioned above. That is, if such an EPROM is used in a bright place, there is a risk that the circuit will not operate properly.

FIG. 4 partially shows an example in which the circuit of FIG. 1 is applied to an EPROM. V _p voltage sensing circuit 1
1 is whether the signal input to terminal 10 is V _p
This is a circuit that distinguishes whether it is OE or not and detects V _p , and consists of a type of level comparator. That is, when the potential of terminal 10 is below V _c (5V),
Node E becomes logic "1", and when the potential at terminal 10 is V _p (25V), node E becomes logic "0". Node E is connected to gate ends B, C and depletion type MOS transistors T14 ₁ to T
14 connected to the gate of _o . That is, the V _p voltage detection circuit 11 turns on/off the transistors T11, T13 and T14 ₁ to T14 _o according to the potential of the terminal 10 . Transistor T14 ₁ ~T1
4 _o is a gating transistor inserted between the row or column decoders 12 ₁ to 12 _o and the decoder output lines 13 ₁ to 13 _o .

Node D is connected to the gates of enhancement type MOS transistors T15 ₁ to T15 _o . The drains of transistors T15 ₁ to T15 _o are all connected to terminal 10, and the sources are connected to decoder output lines 13 ₁ to 13 _o via depletion type MOS transistors T16 ₁ to T16 _o , respectively. Such a decoder output line is for example 256
When using memory cells with 16 rows and 8 bits, 256 cells are used for each row and 16 cells are used for each column. Then, for each of the 256+16 decoder output lines, there is a transistor connected to the terminal 10, such as transistor T15. When light hits the PN junctions of such a large number of transistors, the aforementioned large leakage current causes an adverse effect.

FIGS. 5a and 5b partially show examples of conventional structures on semiconductor substrates. Figure 5a
are _the contact holes 22 1 for the N ⁺ regions, for example, the drain 21 ₁ and the source 21 ₂ , respectively.
22 ₂ , a wiring pattern, that is, a conductive layer 23 ₁ ,
23 Shows the state in which ₂ is placed. In addition, Fig. 5b shows
A cross section taken along line a-a in figure a is shown. In these figures, it is common knowledge in the industry to make the widths of the conductive layers 23 ₁ and 23 ₂ as narrow as possible in order not to reduce the integration density of the IC. Therefore, each of the conductive layers 23 ₁ and 23 ₂
Although it may partially cover the P-N junction formed between the N ⁺ type drain 21 ₁ or source 21 ₂ and the P-type substrate 24, most of the P-N junction portion is covered by the conductive layer 23. ₁ , 23 Not covered by ₂ . Further, the drain 21 ₁ , the source 21 ₂ and most of the substrate 24 are sequentially coated with an insulating layer 25 made of transparent silicon dioxide (SiO ₂ ) and an insulating layer 26 made of SiO ₂ containing phosphorus (P). Therefore, even if the conductive layers 23 ₁ and 23 ₂ are made of a light-shielding member such as aluminum (Al), the PN junction portion is hardly shielded from light. That is, from above the substrate 24, the conductive layers 23 ₁ ,
23 When a photon with energy hμ that has avoided ₂ is incident, this photon energy hμ enters the full band (valence band).
The electrons are excited and promoted to a conductor, and the photo leakage current flows to the conductive layers 23 ₁ and 23 ₂ . The diffusion depth of N-type impurities in the drains 21 ₂ and 21 ₂ is usually shallow, about 1 to 3 μm, so when the photon energy h μ is large, the P-N in the substrate 24
Even at the junction, the photo-leakage current is generated.

From the above, when a semiconductor device having a conventional structure as shown in FIG. 5 is exposed to light, a large leakage current is generated depending on the illuminance of the light.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor device that can prevent adverse effects caused by junction leakage current caused by light.

[Summary of the invention]

In order to achieve the above object, a semiconductor device according to the present invention includes a light shielding means on a semiconductor region in which a PN junction is formed. This light blocking means significantly reduces or blocks light incident on the PN junction. Therefore, leakage current caused by light hitting this PN junction is significantly reduced. The present invention is particularly useful when the PN junction through which this leakage current flows is connected to another circuit via an external lead-out terminal of a semiconductor device, such as an EPROM. That is, since the leakage current is effectively reduced by the present invention, even if an EPROM to which the present invention is applied is used in a bright place, the other circuits will not suffer from substantial adverse effects due to the leakage current, such as fan-out. There will be no reduction.

[Embodiments of the invention]

Next, embodiments of this invention will be described. In the description, the same or similar reference numerals will be used for the same or similar parts in multiple drawings to avoid redundant explanation.

Figures 6a to 6c show that the present invention can be used, for example, in an EPROM.
1 shows the external appearance of a package, that is, a storage body 1 when applied to. The upper surface of the storage body 1 is exposed to EPROM by photons or ultraviolet rays having energy hμ.
A light-shielding portion or window 3 is provided in order to erase data stored in the memory cells within. Further, as the storage body 1, a package whose entirety is translucent may be used.

FIG. 7 shows a first embodiment of the present invention, in which a is a plan view of the pattern and b is a plan view of the pattern.
FIG. 3 is a sectional view taken along line b. In the figure, a first semiconductor region of a first conductivity type, for example, a P-type substrate 24 includes:
A second conductivity type second semiconductor region, for example, an N ⁺ type drain 21 ₁ and source 21 ₂ are formed by diffusion. Further, a polysilicon gate 28 is formed on the channel region between the drain 21 ₁ and the source 21 ₂ with a gate oxide film 27 such as SiO ₂ interposed therebetween. Further, a field oxide film 29 made of SiO ₂ or the like is formed around the drain 21 ₁ and source 21 ₂ . The field oxide film 29 surrounds the drain ₂₁₁ on three sides,
Groove 3 whose tip reaches the surface of substrate 24
0 is formed. Also, the substrate 2 excluding this groove 30
An insulating layer 25 made of SiO ₂ is deposited on the surface of 4. Furthermore, an insulating layer 26 made of SiO ₂ containing P is deposited to a constant thickness inside the groove 30 and on the surface of the insulating layer 25. That is, a new groove 31 whose tip does not reach the surface of the substrate 24 is thereby formed. Further, a contact hole 22 ₁ is formed on the drain 21 ₁ , and a conductive layer 23 ₁ made of Al or the like is formed thereon. At this time, this conductive layer 23 ₁ connects the drain 21 ₁ and the substrate 2
While sufficiently covering the P-N junction consisting of 4,
It is formed so as to fill the groove portion 31. A contact hole 22 ₂ is also formed on the source 21 ₂ and a conductive layer 23 ₂ is formed on this as well.

Here, the process of forming the conductive layers 23 ₁ and 23 ₂ will be explained. First, an insulating layer 25 is deposited to a constant thickness on the entire surface of the substrate 24, and then a first
Grooves 3 are formed in the insulating layer 25 using a contact mask.
0 and two contact holes 22 ₁ and 22 ₂ are formed simultaneously. Next, the insulating layer 26 is again deposited to a constant thickness over the entire surface of the substrate 24, and then a second contact mask is used to only cover the insulating layer 26 deposited in the two contact holes 22 ₁ and 22 ₂ . remove. At this time, there is an insulating layer 2 in the groove 30.
6 remains with a constant thickness, and this creates a new groove 3.
1 is formed. Next, Al is deposited on the entire surface of the substrate 24 and patterned to sufficiently cover the PN junction between the drain ₂₁₁ and the substrate 24, as shown in FIG. A conductive layer 23 ₁ is arranged to surround this PN junction from three sides thereof, and a conductive layer 23 ₂ is connected to the source 21 ₁ .

By the way, the conductive layer 23 ₁ continuous with the wiring pattern
is a P-N consisting of the drain 21 ₁ and the substrate 24
It is formed to cover the joint from the top and three sides. In order to block light, this conductive layer ₂₃₁ includes a field oxide film 29 and two insulating layers 25 and 26.
The average illuminance of the light that goes around the PN junction by reflection through the PN junction is significantly reduced compared to the conventional one. For example, if the conductive layer 23 ₁ reduces the illuminance to 1/100, the graph of FIG. 2 shows that the leakage current I _L also decreases to approximately 1/100.
That is, the conductive layer 23 ₁ constitutes a light shielding means for reducing junction leakage current caused by light.

8 to 10 are modified examples of FIG. 7, in which FIG. 8a is a plan view of the pattern, and FIG.
9a is a pattern plan view, FIG. 9b is a sectional view along line d-d,
0A is a plan view of the pattern, and FIG. 0B is a sectional view taken along the line ee. In the case shown in FIG. 8, the second insulating layer 26 is not formed, and the groove portion 30 is formed simultaneously with the two contact holes 22 ₁ and 22 ₂ . Here drain 21
In order to completely remove the insulating layer 25 on the etching layer ₁ , the tip of the trench 30 enters into the field oxide film 29 by the amount of excess etching. Note that the deeper the groove 30 is so that the tip of the groove 30 does not reach the surface of the substrate 24, the less the light will go around.

In the case shown in FIG. 9, when forming the drain 21 ₁ , an N ⁺ type region 21 ₃ is formed at the same time, and the grooves 30 and 31 are further formed on this.
This groove portion 31 is filled with a conductive layer 23 ₁ .

What is shown in FIG. 10 is a polysilicon gate 2
8, a gate oxide film 27 ₂ and a polysilicon gate 28 ₂ are formed at the same time, and a groove 30 is further formed thereon, and this groove 30 is filled with a conductive layer 23 ₁ . .

In this manner, in the structure shown in FIGS. 7 to 10, the conductive layer 23 ₁ filling the groove 30 or 31 does not come into direct contact with the substrate 24 .

Figures 11a and 11b show a second embodiment of the invention, where Figure 11a is a pattern plan view and Figure 11b is a pattern plan view.
is a sectional view taken along line ff. As shown in the figure, a polysilicon layer 32 is formed on the drain ₂₁₁ .
is provided. This polysilicon layer 32 is used as a part of the wiring pattern to fill the contact hole 22 ₁ , and also connects the drain 21 ₁ and the substrate 24 .
while covering the P-N junction formed by
It is formed on the surface of the substrate 24 so as to surround the drain 21 ₁ on three sides, with a gate oxide film 27 ₃ interposed therebetween. Furthermore, the polysilicon layer 32 is a gate oxide film 2 that is continuous with the gate oxide film 27 ₃ .
It partially overlaps the polysilicon gate 28 via ₇₄ . With this structure, the polysilicon layer 32 and the polysilicon gate 28 block light, and the thin gate oxide films 27, 27 ₂ , 27 are formed around the PN junction.
_3,274 , so there is very little light going around _.

FIG. 12 shows a third embodiment of the present invention, in which FIG. 12a is a plan view of the pattern, FIG. FIG. Here, in the insulating layer 25,
A groove 30 whose tip reaches the surface of the substrate 24 except for a part is formed to surround the drain 21 ₁ , the source 21 ₂ and the polysilicon gate 28 from all sides. A conductive layer 23 made of Al is formed to cover the surface of the insulating layer 25 surrounded by the groove 30. Further, wirings 33 1 and 33 2 made of the first polysilicon layer are led out from the drain 21 ₁ and the source 21 ₂ , and the ends of these wirings _{33 1 and 33 2 and} the polysilicon gate 28 are connected to the substrate.
4 is led out to the outside through the lower part of the groove 30. And the above wiring 33 ₁ , 33 ₂
A second polysilicon layer 34 is formed in contact with the conductive layer 23 with the first polysilicon layer and the thin insulating layer 25 interposed therebetween at the intersections between each and the groove portion 30 . At the same time, a second polysilicon layer 34 is also formed at the intersection of the polysilicon gate 23 and the trench 30 so as to be in contact with the conductive layer 23 via the polysilicon gate 28 and the thin insulating layer. Further, in the portion of the substrate 24 where the tip reaches the surface thereof, an N ⁺ type region 21 ₃ is formed at the same time as the drain 21 ₁ and the source 21 ₂ are formed.

With such a structure, since the light goes around only through the thin insulating layer 25 in a part of the groove 30 surrounding the drain 21 ₁ and the source 21 ₂ , the light goes around almost completely. Note that the structure shown in Figure 12 can be used as an ultraviolet erasable EPROM (Erasable Programmable
If applied to a specific memory cell in a ROM (ROM), this memory cell will hardly be irradiated with ultraviolet rays.
Although it is an EPROM memory cell, it is just a memory cell.
Can be used as PROM.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to minimize the amount of light reflected from the PN junction and reduce the junction leakage current due to photocurrent without complicating the process in particular.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a circuit applicable to the semiconductor device according to the present invention, and FIG. 2 is a diagram showing the relationship between the leakage current I _L per unit area in a P-N junction and the illuminance of light incident on this P-N junction. Graph illustrating the relationship, Figure 3 is a diagram showing a measurement circuit for the graph in Figure 2, Figure 4 is a diagram partially showing an example of applying the circuit in Figure 1 to EPROM, Figure 5a 5 is a plan view of a pattern showing an example of a structure on a conventional semiconductor substrate, FIG.
Figures a, b, and c are external views illustrating a package of a semiconductor device according to the present invention, Figure 7a is a pattern plan view of a semiconductor device according to an embodiment of the present invention, and Figure 7b is the same as that of Figure 7a. 8a is a pattern plan view showing a modification of FIG. 7; FIG. 8b is a sectional view taken along line c-c in FIG. is a pattern plan view showing another modification of FIG. 7, FIG. 9b is a sectional view taken along line dd in FIG. 7a, and FIG. 10a is another modification of FIG. 7. FIG. 10b is a sectional view taken along line ee in FIG. 10a, FIG. 11a is a pattern plan view showing another embodiment of the present invention, FIG. 11b
is a sectional view taken along line ff in Figure 12a, Figure 12a
12b is a pattern plan view showing another embodiment of the present invention, FIG. 12b is a sectional view taken along line gg in FIG. 12a, and FIG. FIG. T10, T13, T15 ₁ to T15 _o ...Enhancement type MOS transistor, T11, T12,
T14 ₁ to T14 _o , T16 ₁ to T16 _o ...depression type MOS transistor, 1... housing (package), 3... window (transparent part), 10... terminal,
11... _Vp voltage detection circuit, 12 ₁ to 12 _o ...decoder,
13 ₁ to 13 _o ...decoder output line, 21 ₁ ... drain, 21 ₂ ... source, 21 ₃ ... N ⁺ type region, 22 ₁ ,
22 ₂ ... contact hole, 23, 23 ₁ , 23 ₂
... conductive layer, 24 ... P-type substrate, 25, 26 ... insulating layer, 27, 27 ₂ , 27 ₃ , 27 ₄ ... gate oxide film,
28, 28 ₂ ...Polysilicon gate, 29...Field oxide film, 30, 31...Trench, 32...Polysilicon layer, ₃₃₁ , ₃₃₂ ...Wiring, 34...Second polysilicon layer.

Claims (1)

[Claims] 1. A part of an ultraviolet erasable nonvolatile memory cell, which is constructed by forming source and drain regions made of a second semiconductor region of a second conductivity type in a first semiconductor region of a first conductivity type. or a transistor forming a peripheral circuit thereof; a wiring layer connected to the transistor; an insulating layer formed on the surface of the first semiconductor region; and surrounding the first semiconductor region on all sides in which the transistor is formed. formed on the insulating layer,
a groove portion whose tip reaches the surface of the first semiconductor region leaving a portion where the wiring pipe is provided; and a third semiconductor region of a second conductivity type formed on the surface of the first semiconductor region located at the tip of the groove portion. and a conductive light-shielding layer formed to fill the grooves, cover the surface of the insulating layer surrounded by the grooves, and have its tip contact the surface of the third semiconductor region. Device.