JPH0452978B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In order to ensure that the main memory write order is correctly transmitted to the central processing unit, the storage control device is provided with a circuit that monitors the propagation time of the buffer invalidation address,
To facilitate the provision of a circuit for efficiently performing buffer invalidation processing.

[Industrial application field]

The present invention relates to a data processing device, and in particular, when a system includes a plurality of central processing units each having a built-in cache memory, for example, a second tag or a buffer invalidation queue for each central processing unit is provided in a storage control device. The present invention provides a means for efficiently performing buffer invalidation processing and for correctly reflecting the main memory write order of a certain central processing unit or channel processing unit on another central processing unit.

[Prior art and problems]

If the storage controller has a second tag section or a buffer invalidation queue, there is a possibility that the buffer invalidation address will remain in the storage controller for more than a certain period of time, and as a result, a certain central processing unit or channel processing unit A situation arises in which the write order of main memory is not correctly reflected on other central processing units. For this reason, in the prior art, the second tag part and the buffer invalidation queue are not placed in the storage control device, and the buffer invalidation process causes a decrease in system performance. Particularly in recent years, as the number of central processing units in a single system has increased and the speed of central processing units has increased, the performance degradation due to buffer invalidation processing has become so large that it cannot be ignored.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
The storage control device has a second tag or a buffer invalidation queue as a function for performing buffer invalidation processing, and by monitoring the propagation time of the buffer invalidation address, a certain central processing unit or channel processing unit The purpose of the present invention is to provide a control method that ensures that the main memory write order of a central processing unit is correctly transmitted to other central processing units.

[Means to achieve the purpose]

Therefore, the main memory write order control method of the present invention includes: a plurality of central processing units; a main memory; and a storage control device that controls access to the main memory by the central processing units; The processing device has a buffer invalidation stack that stores the buffer invalidation address sent from the storage control device, and the storage control device stores the buffer invalidation address in the first tag section of the corresponding central processing device for each central processing device. a second tag section that holds the same information as the stored information; a buffer disable address generating means that generates a buffer disable address based on the main memory access request and the contents of the second tag section; and a buffer invalidation queue for storing the buffer invalidation address generated by the buffer invalidation address generating means, and the corresponding buffer invalidation queue is stored on the condition that the buffer invalidation stack busy signal from the corresponding central processing unit is not on. In a computer system configured to send the buffer invalidation address in the invalidation queue to the corresponding central processing unit, the storage controller includes, for each central processing unit, a buffer invalidation address in the corresponding buffer invalidation queue. Based on the number of buffer invalidation addresses and the buffer invalidation stack busy signal from the corresponding central processing unit, it is checked whether the propagation time of the buffer invalidation address within the storage control device exceeds a certain value, and A monitoring means is provided to send a cancel signal instructing to cancel the load access to the corresponding central processing unit when the value exceeds the value, and a monitoring means is provided for sending a cancel signal instructing to cancel the load access to the corresponding central processing unit. If a load access request has been issued when the data is accessed, the data is not used or registered in the cache, and the same load access request is sent again to the storage control device. It is.

[Embodiments of the invention]

First, an overview of the present invention will be explained. Due to its control, it is difficult for the central processing unit to always receive the buffer invalidation address from the storage control unit. However, if the storage control device has a second tag section or a buffer invalidation queue, the maximum number of buffer invalidation addresses at a certain point in time will increase, and the buffer invalidation addresses will not be sent to the central processing unit within a certain period of time. It becomes difficult to guarantee that they will be sent. The present invention monitors the propagation of a buffer invalidation address for each central processing unit using a relatively simple circuit, and detects when a state that exceeds a certain period of time occurs and the corresponding central processing unit performs a load or load to main memory.
If the access is in progress, the storage controller instructs the central processing unit to cancel the load access. Even with the bypass function, the central processing unit does not use the data and does not register the data in the cache memory. Thereafter, the central processing unit again initiates a block load request access to the main memory at the same address to ensure that the main memory write order of other processing units is correctly reflected. .

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a diagram showing an example of the configuration of a general computer system. In FIG. 1, 1-0 to 1-3 are main memory units, 2-0 and 2-1 are storage control units, 3-0 and 3-1 are service processors, and 4
-0 and 4-1 are system console interfaces, 5-0 to 5-3 are central processing units, 6
-0 and 6-1 are channel processing devices, 7-1 is the first
, 7-2 is a second tag portion, and 8 is a data portion. Each of main storage devices 1-0 to 1-3 is composed of a plurality of banks. Two central processing units and one channel processing unit are connected below the storage control device 2-0. Two central processing units and one channel processing unit are connected below the storage control device 2-0. Two central processing units and one channel processing unit are also connected under the storage control device 2-1. The storage control device controls data transfer between a lower-level processing device and a main storage device. An interface is provided between the storage controllers 2-0 and 2-1. For example, when the storage controller 2-0 wants to access the main storage unit 1-2, the storage controller 2-0 accesses the main storage unit 1-2 via this interface. Request to -1. Storage control device 2-0
has two tag parts 7-2, each tag part 7
-2 holds a copy of the corresponding tag section 7-1. The storage control device 2-1 also has two tag units 7.
-2. Service processor 3-
0 and 3-1 have a system console function, a system abnormality monitoring function, a maintenance console function, etc. The central processing unit 5-0 has a cache memory, and the cache memory is composed of a tag section 7-1 and a data section 8. Note that the cache memory is managed using a store-through method. Note that in the store-through method, if the write address exists in the first tag section, the write data is written to both the cache memory and main memory, and the write address is stored in the first tag section. If the write data does not exist in the main memory, the write data is written only to the main memory. The same applies to other central processing units. Each channel processing device 6-0, 6-
1 controls data transfer between the input/output device and the storage control device, and can have, for example, a maximum of 16 channels.

FIG. 2 is a diagram illustrating an example of propagation of buffer invalidation addresses in which if a main memory write address of a central processing unit is not processed within a certain fixed time, the order will not be correctly transmitted to other central processing units. Second
In the example shown in the figure, the central processing unit 5-0 initiates write access to the main memory in the order of STA, STB (A, B are address values), and the central processing unit 5-1 initiates read access to the main memory in the order of STA, STB (A, B are address values). It is started in the order of FCHB. At that time, if only the data for address A is loaded into the cache memory of the central processing unit 5-1 and the data for address B is not loaded, the central processing unit 5-1 transfers the data to the storage controller 2-0. main memory access to
Start FCHB.

When the storage controller 2-0 processes the write access STB in advance, the read access FCHB is kept waiting for a certain period of time due to bank busy, and the read access FCHB of the central processing unit 5-1, which is processed next, is processed by the central processing unit 5-1. This becomes new data updated by the processing device 5-0, and is sent to the central processing device 5-1.
When the central processing unit 5-1 receives the data of the read access FCHB from the storage control unit 2-0, it sets it in the operand word register OWR and starts execution, and at the same time writes the read access FCHA of the subsequent instruction to the cache memory. Do it against.
The central processing unit 5- which has been activated earlier up to this point
If the buffer invalidation address by the main memory write access STA of 0 is propagated to the central processing unit 5-1 and the buffer invalidation processing is not completed, the old memory remaining in the cache memory of the central processing unit 5-1 will be deleted. Data is used to execute instructions. If such a situation occurs, the main memory write order of the central processing unit 5-0 will not be correctly transmitted to the central processing unit 5-1.

FIG. 3 is an example of standardizing the interface between the storage control unit and the central processing unit and the internal processing of each unit in order to prevent the above situation from occurring. No matter how this regulation is changed, it is necessary to limit the propagation time of the buffer invalidation address in the storage control device to within a certain period of time, or to take some other countermeasure. In Figure 3, the storage controller maximizes the propagation of all buffer invalidation addresses.
22τ, and if it exceeds 22τ, the corresponding central processing unit is instructed to cancel the fetch. When the central processing unit receives DOW (timing signal sent 6τ before fetch data), it adds a flag to the buffer invalidation address in the buffer invalidation stack in the central processing unit, and invalidates the buffer with this flag. If a cache address is left unprocessed, subsequent cache fetches (e.g.
FCHA) is prohibited.

FIG. 4 is a logical configuration diagram of the storage control device of FIG. 1, particularly focusing on the buffer invalidation address propagation circuit. In FIG. 4, 9 to 12 are ports;
13 is a priority selection circuit, 14 is a bank busy control unit, 15 and 16 are registers, 17 is a pipeline, 18 is an interface control unit for the central processing unit and the channel processing unit, 19 is a RAM of the second tag unit, 20 is a coincidence detection circuit, 21 is a selector, 22 is a buffer invalidation queue, 23 is a queue control unit, and 24 is a second circuit for the central processing unit 5-1.
tag part, BIR0 to BIAR are registers,
MCH indicates a matching flag, and RDAT2 indicates a register. Port 9 is central processing unit 5-
Port 10 is for central processing unit 5-1, port 11 is for channel processing unit 6-0, and port 12 is for channel processing unit 6-1. The priority selection circuit 13 inputs main memory access requests sent from each port to the selected pipeline 17. At this time, a main memory access request specifying a busy bank is not selected. The bank busy control unit 14 is for notifying the priority selection circuit 13 which bank is busy. The pipeline 17 is composed of a plurality of control stages, and each stage performs unique control. The interface control unit 18 controls the transfer of data and control signals between the storage control device and the processing device connected thereunder. The RAM 19 is of a set associative type like the first tag section 7-1, and the contents of the tag section 7-1 of the central processing unit 5-0 are copied therein. The coincidence detection circuit 20 is
The read data from the RAM 19 and the upper part of the main memory write address data of the register BIR0 are compared, and if they match, the match flag MCH is turned on. If the read data from RAM19 and the upper part of the main memory write address data of register BIR0 match and the main memory write address is from another device, the register
BIR0 main memory write address data is a register
It is stored in the buffer invalidation queue 22 via the BIR1 and the selector 21. Furthermore, if the read data from RAM19 and the upper part of the main memory read address data of register BIR0 do not match, and the main memory read address is from the own device, the main memory read address data of register BIR0
Data is written to RAM 19 via BIR1 → loopback signal line → BIR0, and data in register RDAT2 (in which read data from RAM 19 is set) is stored in buffer invalidation queue 22 via selector 21. . The buffer invalidation addresses stored in the buffer invalidation queue 22 are sequentially sent to the central processing unit 5-0 via the register BIAR. Queue control section 2
3 controls the buffer invalidation queue 22, and sends the BI STACK from the central processing unit 5-0.
When a BUSY signal (a signal indicating that the buffer invalidation stack is full) is sent, the sending of the buffer invalidation address to the central processing unit 5-0 is interrupted.

If the storage control device does not have a second tag part, buffer invalidation queue, etc., it is relatively easy to ensure that the buffer invalidation address propagation time in the storage control device is within a certain fixed time. I can do it. However, in that case, if any of the buffer invalidation stacks in each central processing unit becomes FULL, it is necessary to prohibit writing to the main memory of all central processing units other than that central processing unit.

Conversely, if the second tag section and buffer invalidation queue etc. are included in the storage control device, the buffer invalidation stack in the corresponding central processing unit becomes FULL.
If this occurs, the buffer invalidation address remains in the buffer invalidation queue, making it difficult to guarantee the buffer invalidation address propagation time.

In the example shown in Figure 3, if write access and read access to the same address are consecutive, a data-out warning signal is sent for the read access.
The minimum number of cycles up to DOW is 22τ (number of machine cycles). If the buffer invalidation address is propagated in the storage controller without waiting, PIPELINE→BIR0→BIR1→BI QUEUE→
A total of 5τ is required for each register in BIAR. Further, the reasons why the buffer invalidation address is kept waiting are that several buffer invalidation addresses are accumulated in the buffer invalidation queue 22 and that the buffer invalidation stack of the corresponding central processing unit is
There are two reasons why the buffer invalidation address cannot be sent in the "FULL" state.If the waiting time due to these is Wt, then 5τ+Wt≦22τ holds true.In other words, if Wt≦17τ, there is no problem. .

FIG. 5 is a diagram showing an example of a time monitoring circuit for propagating a buffer invalidation address to a central processing unit according to the present invention. In FIG. 5, 25 is a subtraction circuit, 26 is a (+1) circuit, 27 is an addition circuit, and 28
and 29 are D flip-flops, 30 are SR flip-flops, 31 are AND circuits, 32 and 33
34 represents an OR circuit, 34 represents a NOR circuit, and 35 represents a register.

The circuit shown in FIG. 5 detects Wt>16τ. The value of 16τ is due to circuit considerations. Since it is difficult to detect the processing state shown in Figure 2 with a storage control device, we pay attention to all main memory write accesses and use the circuit shown in Figure 5 to detect when any of them becomes Wt > 16τ. Then, it instructs the corresponding central processing unit to cancel the main memory read access. If the central processing unit has not initiated a main memory read access, this cancel signal can be ignored. The conditions of the circuit for detecting Wt>16τ in FIG. 5 are as follows.

Wt＞16τ= [(BI INQ counter - BI OUTQ counter) +BI STACK BUSY counter value] +BI STACK BUSY 2ND (BI INQ counter - BI OUTQ counter) indicates the number of buffer invalidation addresses in the buffer invalidation queue, ( BI STACK BUSY counter value) indicates the time when the corresponding central processing unit has a buffer invalidation stack in the FULL state;
STACK 2ND) has a buffer invalidation queue.
Indicates that the "BI STACK BUSY" signal has been turned on twice in a non-EMPTY state.

In FIG. 5, the subtraction circuit 21 is (BI INQ
This is used to calculate the counter (BI OUTQ counter). (+1) circuit 26 is (BI STACK
BUSY counter value). When flip-flop 28 is set, (+1)
The circuit 26 increases the value of the clock each time it is generated.
1, and when the OR circuit 33 outputs logic "1",
The value of the (+1) circuit 26 is forced to zero. (+
1) The circuit 26 stops counting at "15". The adder circuit 27 is a 4-bit one, [(BI INQ
Counter - BI OUTQ counter) + BI STACK
BUSY counter value].
When the addition result becomes "16" or more, the carry signal is turned on. This carry signal is sent via the OR circuit 32 and register 35 to the corresponding central processing unit as a cancel signal. When D flip-flop 28 is set while D flip-flop 29 is reset and SR flip-flop 30 is set, AND circuit 31 outputs a logic "1". The output of the AND circuit 31 becomes the BI BUSY 2ND signal. signal
When EMPTY becomes a logic 1, a logic 1 is input to the OR circuit 33, and the SR flip-flop 30 is reset. SR flip-flop 3 is activated even when the BI BUSY 2ND signal is turned on.
0 is reset. BI BUSY 2ND signal is OR
It is sent as a cancel signal to the corresponding central processing unit via the circuit 32 and register 35. If the central processing unit issues a main memory load access request (synonymous with a main memory fetch access request) when receiving the cancel signal, the central processing unit does not use the data and registers it in the cache memory. The main memory load access request to the same address is started again. For example, in FIG. 3, if the cancel signal is sent before 22τ, the central processing unit does not use the fetch data FCHB, and instead uses the fetch data FCHB.
The main memory fetch access request FCHB (next main memory fetch access request) is started again without registering in the cache memory. If a cancel signal is received while the next main memory fetch access request is being issued, the central processing unit performs a similar operation. By performing such an operation, it is possible to ensure that the main memory write order of a certain central processing unit or channel processing unit is correctly transmitted to other central processing units.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to have a second tag part and a queue for holding a buffer invalidation address in the storage control device, and buffer invalidation processing can be performed efficiently. By having a time monitoring circuit for buffer invalidation address propagation to the central processing unit in the storage control unit, the buffer invalidation queue and buffer invalidation stack corresponding to a certain central processing unit in the system are FULL.” It is possible to achieve remarkable effects such as lowering the probability that the write processing of the entire system will be inhibited due to a state in which the write process is disabled.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of the configuration of a general computer system, and Figure 2 shows that if the main memory write address of a central processing unit is not processed within a certain period of time, the order will not be correctly transmitted to other central processing units. FIG. 3 is a diagram showing an interface and processing rules for ensuring that the main memory write order of a central processing unit is correctly transmitted to other central processing units; FIG. 4 is a logical configuration diagram focusing on the buffer invalidation address propagation part of the storage control device shown in FIG. 1, and FIG. 5 is a diagram showing an example of a time monitoring circuit for buffer invalidation address propagation to the central processing unit. be. 1-0 to 1-3...main memory unit, 2-
0 and 2-1...Storage control device, 3-0 and 3-1...
...Service processors, 4-0 and 4-1...System console interfaces, 5-0 to 5-3...Central processing units, 6-0 and 6-1...
...channel processing device, 7-1...first tag section,
7-2...second tag section, 8...data section, 9 to 12...port, 13...priority selection circuit, 1
4...Bank busy control unit, 15 and 16...Registers, 17...Pipeline, 18...Interface control unit for the central processing unit and channel processing unit, 19...RAM of the second tag unit, 2
0... Match detection circuit, 21... Selector, 22...
... buffer invalidation queue, 23 ... queue control section, 24 ... second tag section for the central processing unit 5-1, BIR0 to BIAR ... register,
MCH...Matching flag, RDAT2...Register, 25...Subtraction circuit, 26...(+1) circuit,
27...addition circuit, 28 and 29...D flip
Flop, 30...SR flip-flop, 3
1...AND circuit, 32...OR circuit, 33...
NOR circuit, 34... register.

Claims (1)

[Scope of Claims] 1 A system comprising a plurality of central processing units, a main storage device, and a storage control device that controls access to the main storage device of the central processing units, and each central processing unit has a storage control device. The storage controller has a buffer invalidation stack for storing buffer invalidation addresses sent from the central processing unit, and the storage controller stores, for each central processing unit, the same information as the information stored in the first tag section of the corresponding central processing unit. a buffer invalidation address generation means for generating a buffer invalidation address based on the main memory access request and the contents of the second tag portion; and a buffer invalidation address generation means. It has a buffer invalidation queue that stores the generated buffer invalidation address, and invalidates the buffer in the corresponding buffer invalidation queue on condition that the buffer invalidation stack busy signal from the corresponding central processing unit is not on. In a computer system configured to send buffer invalidation addresses to a corresponding central processing unit, the storage control unit stores, for each central processing unit, the number of buffer invalidation addresses in the corresponding buffer invalidation queue. It is checked whether the buffer invalidation address propagation time within the storage control device exceeds a certain value based on the buffer invalidation stack busy signal from the corresponding central processing unit, and if the buffer invalidation address propagation time exceeds a certain value, A monitoring means is provided for sending a cancel signal instructing cancellation of a load access to a corresponding central processing unit, and the monitoring means is configured to send a load access request to each central processing unit upon receiving a cancel signal instructing cancellation of a load access. If the data has been issued, the data is not used or registered in the cache, and the same load access request is sent to the storage control device again. 2. The monitoring means for each central processing unit includes calculation means for calculating the number of buffer invalidation addresses in the corresponding buffer invalidation queue, and an on buffer invalidation stack busy signal sent from the corresponding central processing unit. a counter for counting the duration of , an addition means for adding the output of the calculation means and the output of the counter, and means for sending a cancel signal to the corresponding central processing unit when the addition result of the addition means exceeds a certain value. A main memory write order control system according to claim 1, characterized in that: 3. Means for the monitoring means for each central processing unit to send a cancel signal to the corresponding central processing unit when the buffer invalidation stack busy signal is turned on twice under the condition that the corresponding buffer invalidation queue is not empty. 3. A main memory write order control system according to claim 2, comprising: