JPH0453456B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A reference adjustment method for a parallel comparison type A-D converter, in which conversion data due to code transition uncertainty is a problem when converting a high frequency band analog signal to a digital signal. Disclosed is an adjustment method that allows distortion to be adjusted to approximate low frequency differential linearity adjustment.

[Industrial application field]

The present invention relates to a method capable of adjusting the differential linearity of an A-D converter by taking into account the influence of code transition uncertainty, and more specifically, the present invention relates to a method that allows adjustment of the differential linearity of an A-D converter, taking into account the influence of code transition uncertainty. The transition uncertainty is determined by using a superimposed signal with a high frequency signal of minute amplitude, and the comparator output has a duty ratio of 50%.
The present invention relates to a method that enables adjustment of good differential linearity in a high frequency region by setting a reference voltage such that

The key circuit of an A-D converter is a comparator circuit, and a comparator circuit using MOS technology has an 8-bit A-
D converters with conversion speeds of approximately 35M samples/second are common, and 6-bit parallel comparison A-D converters using sapphire insulating substrates have conversion speeds of 40M samples/sec.
Devices that operate up to samples per second have also reached practical use.

However, in realizing an A-D converter in a higher frequency range, there is a need for a circuit that corrects distortion of converted data due to the characteristics of the comparison circuit.

[Prior art] A parallel comparison type A-D conversion circuit installs comparators in the number corresponding to the quantum levels, compares the analog input voltage with each of these quantization levels in parallel, and determines which level of the comparator is operating. This is a method of obtaining digital output depending on the method, and is an A-D conversion circuit capable of extremely high-speed conversion operation.

However, due to differences in characteristics such as the conversion speed at which the output of the comparator changes from 1 to 0 or 0 to 1, the higher the frequency, the wider the area of code transition uncertainty becomes, making it difficult to perform digital conversion that accurately corresponds to analog input. There is a problem that has become impossible.

[Problem that the invention seeks to solve]

Regarding the above problems, the development of MOS technology and the use of sapphire as an insulating substrate have been used to increase the speed of circuits, reduce the code transition uncertainty, and gradually put A-D converters in high frequency range into practical use. However, there are limits to the high frequencies that can be used.

The present invention was created in view of these points, and by adding a simple circuit to the conventional A-D conversion circuit using a comparator, it is possible to perform high-frequency conversion with good differential linearity. The purpose of this invention is to provide a reference adjustment circuit that

[Means for solving problems]

As shown in the principle block diagram of the reference adjustment method according to the present invention in FIG. ,
It is composed of comparators 3 whose number corresponds to the quantization level that compares the input analog signal and the comparison reference voltage, and the reference voltage regulator group is equal to the number of comparators and finely adjusts the comparison reference voltage applied to the comparators. Bias voltage source 5 in actual use, which is equipped with a variable resistor having the same resistance value that can be adjusted, and one of which is connected in series with respect to the input analog signal via a terminating resistor and a switch 4.
and a bias voltage source 6 during adjustment with a variable voltage value, and when adjusting the A-D converter, one comparator in the comparator group uses its reference voltage under the bias voltage during actual use. Set the level of the analog input signal for adjusting the sine wave so that it is the minimum level necessary for inverting 1 and 0, and then set the level of the analog input signal for adjusting the sine wave to the comparator to be adjusted by the bias voltage source during adjustment.
A corresponding variable resistor in the reference voltage regulator group is adjusted to generate a comparison reference voltage such that a corresponding bias voltage is applied and the comparator output has a duty ratio of 50% under the bias voltage. This is achieved by a reference adjustment method for a parallel comparison type A-D converter characterized by the following.

[Effect]

The output voltage of the reference voltage generation circuit 1 is the difference voltage between the maximum V _H and the minimum V _L of the comparison reference voltages of the comparator group 3 as the full-scale voltage V _FS , and in the case of an X-bit A-D converter, the full-scale voltage is The resistors of the reference voltage regulator group 2 are provided so that V _FS is divided in steps of V _FS /2 ^X and each divided voltage becomes a reference voltage for comparison of 2 ^X -1 comparators.

The individual resistors of reference voltage regulator group 2 each have the same resistance value, but each of these resistors is a variable resistor and finely adjusts the comparison reference voltage applied to each comparator. Adjustments are now possible.

The adjustment method is to use a sine wave analog input signal for adjustment as the adjustment input signal, adjust it to the minute signal level necessary to impress one comparator, and use the bias switcher 4 to apply the adjustment signal to the analog input circuit. After superimposing bias voltage 6, comparator group 3
Set the duty ratio of the bit output to 50%,
This is performed by finely adjusting the variable resistors constituting the reference voltage regulator group 2 to set the comparison reference voltage.

〔Example〕

Figure 2 shows an embodiment of the present invention, in which high-speed comparators C ₁ to C ₇ are used as comparators, and 100Ω variable resistors RV ₁ to RV ₇ are connected in series as reference voltage regulators. The configured 3-bit A-
It is a D converter.

Furthermore, in this circuit, resistors R ₁ and R ₂ are 50Ω, and by setting each variable resistor in the center, it is possible to obtain comparison reference voltages that are approximately equally spaced.

A bias voltage of -1.3V during actual use is set between the termination resistor 7 and the ground, and a power supply that can be varied from -1.7V to -0.9V is used as the bias voltage during adjustment.

Adjustment of differential linearity by this circuit is performed by the following procedure.

The bias switcher 4 is set to the bias voltage 5 during actual use.

Set the signal level of the sine wave adjustment analog input suitable for adjustment.

The setting conditions are, for example, comparator C ₄ where the fourth comparison reference voltage is set in comparator group 3.
is the minimum level required to invert from 1 to 0 and from 0 to 1. At this time, if necessary, adjust the fourth reference voltage regulator _R4 .

The bias switcher 4 is switched to the bias voltage 6 for adjustment.

The voltage of the bias voltage 6 during adjustment is set to the reference voltage applied to one of the comparators to be adjusted, for example, -0.9V for the first comparator _C1 of the comparator group 3, and -0.9V for the second comparator C1. -1.0V for ₂ ...7
If it is the second voltage, set it to -1.5V.

The voltage of the reference voltage regulator 2 is adjusted so as to obtain "1" and "0" signals with a duty ratio of 50% for the output bits where the 1→0 inversion of the comparator set by can be directly observed.

FIG. 3 is an explanatory diagram of the above-mentioned duty ratio adjustment circuit. In FIG. 3, A is an example of an adjustment circuit, and the comparator C ₂ in the diagram is the comparator C 2 of one embodiment of FIG. _2.
This is an excerpt from the above section, and therefore, the bias voltage 6 during adjustment is set to -1.0V.

When a sinusoidal analog signal _B1 is input to the adjustment circuit of A as the comparator input of B, a bit output such as _C1 is obtained as the bit output of C.

Of the waveforms of this bit output _C1 , T _W1 shows a relatively stable bit output part in the high level region, T _W2 shows a relatively stable bit output part in the low level region, and a shows the unstable region of the output part. In the figure, this region a is called the code transition uncertainty region.

In addition, the occupation ratio of the stable bit output section to the bit output range including T _W1 or T _W2 and a is called the duty ratio, and when it is 1:1, it is 50
It is defined as %.

Now, if analog signal _B2 , which is the same as analog signal _B1 , is input to _{comparator C2 and the bit output of C2 is obtained, the duty ratio of T W1 will be} 50% or more, and the duty ratio of T _W2 will be It will be less than 50%. In this case, the bit output of _C3 can be obtained by adjusting the variable resistor R _V2 of the reference voltage adjustment circuit so that the duty ratios of T _W1 and T _W2 are each 50%.

Perform the adjustment for each of the other comparators in sequence.

When the above-mentioned adjustment of the comparators C ₁ to _{C 7} constituting the comparator group 3 is completed, the bias switch 4 is switched to the bias voltage 5 for actual use, and the device stands by in the use state.

By using the circuit of the present invention that performs the adjustment according to the above procedure, it is possible to perform adjustment in consideration of the influence of code transition uncertainty in the high frequency region, resulting in A-D conversion with improved conversion characteristics in the high frequency region and less distortion. becomes possible.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an A-D converter with improved characteristics in a high frequency region with an extremely simple circuit configuration and adjustment method, and it is extremely useful in practice. It is.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a reference adjustment circuit according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of duty ratio adjustment. In FIG. 1, 1 is a reference voltage generation circuit, 2 is a group of reference voltage regulators, 3 is a group of comparators, 4 is a bias switch, 5 is a bias voltage during actual use, 6 is a bias voltage during adjustment, 7 is the terminating resistance.

Claims (1)

[Claims] 1 a reference voltage generating circuit 1, a reference voltage regulator group 2 for dividing its output voltage and providing a comparison reference voltage to a comparator, and a number of reference voltage regulators 2 for dividing the output voltage and providing a comparison reference voltage to a comparator, and a number of reference voltage regulators corresponding to the quantum ratio level for comparing the input analog signal and the comparison reference voltage. Comparator 3
The reference voltage regulator group is equipped with variable resistors equal to the number of comparators and having the same resistance value that can finely adjust the comparison reference voltage applied to the comparators. A bias voltage source 5 during actual use and a bias voltage source 6 during adjustment whose voltage value is variable are provided, either of which are connected in series via a switch 4. When adjusting the A-D converter, the bias voltage source 5 during actual use is connected. 1 in the comparator group under
1 and 0 for the reference voltage in each comparator.
The level of the analog input signal for adjusting the sine wave is set to the minimum level required for inversion of the sine wave, and then the corresponding bias voltage is applied to the comparator to be adjusted from the bias voltage source during adjustment, A parallel comparison type characterized in that the corresponding variable resistor in the reference voltage regulator group is adjusted to generate a comparison reference voltage such that the comparator output has a duty ratio of 50% under such bias voltage. How to adjust the reference of an A-D converter.