JPH0454377B2 - - Google Patents
Info
- Publication number
- JPH0454377B2 JPH0454377B2 JP57029294A JP2929482A JPH0454377B2 JP H0454377 B2 JPH0454377 B2 JP H0454377B2 JP 57029294 A JP57029294 A JP 57029294A JP 2929482 A JP2929482 A JP 2929482A JP H0454377 B2 JPH0454377 B2 JP H0454377B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- substrate
- printing
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はセラミツク基板上に半導体チツプが塔
載され、半導体チツプの電極と基板上の配線導体
との間がリード線によつて接続される混成集積回
路の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is based on a semiconductor chip mounted on a ceramic substrate, and the electrodes of the semiconductor chip and the wiring conductors on the substrate are connected by lead wires. The present invention relates to a method for manufacturing a hybrid integrated circuit.
このような混成集積回路の半導体チツプの搭載
のためのダイボンデイングあるいは半導体チツプ
との接続のためのワイヤボンデイングを行う場
合、以前は顕微鏡を用いて目視によつて位置を確
認して作業していた。しかし最近は生産の合理化
のためにダイボンデイング、ワイヤボンデイング
の自動化の要請が高まつている。
Previously, when performing die bonding for mounting a semiconductor chip in such a hybrid integrated circuit or wire bonding for connection to a semiconductor chip, the position was confirmed visually using a microscope. . However, recently there has been an increasing demand for automation of die bonding and wire bonding in order to streamline production.
この場合、ボンデイングすべき位置の正確な認
識が必要で、そのために基板上に位置合わせマー
クを付ける。位置合わせマークは例えば金ペース
トを配線導体のための導線材料ペーストと同一工
程で印刷焼成することによつて付けられる。ま
た、このような金ペーストの印刷焼成による金マ
ーク以外に別の工程でセラミツク基板と判別のつ
きやすい色を印刷してやることが考えられる。 In this case, it is necessary to accurately recognize the position to be bonded, and for this purpose alignment marks are provided on the substrate. The alignment marks are attached, for example, by printing and firing gold paste in the same process as the conductor material paste for the wiring conductor. Furthermore, in addition to the gold mark formed by printing and firing such gold paste, it is conceivable to print a color that is easy to distinguish from a ceramic substrate in a separate process.
まず前者の印刷金マークは通常の光学パターン
認識機ではセラミツク基板との判別ができないと
いう問題である。
First, the former problem is that printed gold marks cannot be distinguished from ceramic substrates using a normal optical pattern recognition machine.
また後者の別の工程で判別のつきやすい色を印
刷焼成してやる場合、判別し易い色を印刷するた
めの工程が増えてしまう。さらに判別のためのマ
ークと金ペーストによる配線導体との形成が別と
なり、配線導体とマークとの相互間隔が各基板に
よつて、若干異なつてしまうことが避けられず、
位置合わせマークとして不適当である。つまり、
極端な場合、半導体チツプが異なる導体パターン
間に橋絡接続してしまつたり、ワイヤボンデイン
グが導体に接続されないという問題が生ずる。 In addition, when printing and firing easily distinguishable colors in the latter separate process, the number of steps for printing easily distinguishable colors increases. Furthermore, since the marks for identification and the wiring conductors using gold paste are formed separately, it is inevitable that the mutual spacing between the wiring conductors and the marks will differ slightly depending on each board.
It is inappropriate as an alignment mark. In other words,
In extreme cases, the problem arises that the semiconductor chip has bridging connections between different conductor patterns, or that wire bonds are not connected to the conductors.
本発明が解決しようとする課題は、通常のパタ
ーン認識機で基板の正確な位置検出ができ、確実
なダイボンデイング、ワイヤボンデイングを行う
ことのできる混成集積回路の製造方法を提供する
ことである。 The problem to be solved by the present invention is to provide a method for manufacturing a hybrid integrated circuit that can accurately detect the position of a substrate using a regular pattern recognition machine and can perform reliable die bonding and wire bonding.
この課題は混成集積回路の基板上に設定された
位置合わせマークを光学的に検出して、半導体チ
ツプを基板上においてボンデイング接続してなる
混成集積回路の製造方法であつて、前記位置合わ
せマークが、先に回路の抵抗体と同時に暗色の周
緑部を前記基板上に形成し、次いで回路の導体形
成と同時に前記周緑部上に明色の中央部を形成し
て設けられることによつて達成される。
This subject is a method for manufacturing a hybrid integrated circuit in which alignment marks set on a substrate of a hybrid integrated circuit are optically detected and semiconductor chips are bonded on the substrate. , by first forming a dark-colored peripheral green part on the substrate at the same time as the resistor of the circuit, and then forming a light-colored central part on the peripheral green part simultaneously with the formation of the circuit conductor. achieved.
位置合わせマーク抵抗体と同時に形成される周
緑部と導体形成と同時に周緑部上に形成される中
央部からなり、マークの位置の認識は暗色の周緑
部と明色の中央部との境界において行われること
により、該境界が光学パターン認識機による判別
がつきやすく、更に導体ペーストと抵抗体ペース
トの印刷の位置ずれがあつても、マークの周緑部
と中央部との境界と導体パターンとの間に位置ず
れがなく、極めて高い制度の位置合わせとなり、
ダイボンデイング、ワイヤボンデイングが所定の
位置で正確に自動的に実施できる。
The positioning mark consists of a peripheral green part that is formed at the same time as the resistor and a central part that is formed on the peripheral green part at the same time as the conductor. By performing this at the boundary, the boundary can be easily distinguished by an optical pattern recognition machine, and even if there is a misalignment between the printing of the conductor paste and the resistor paste, the boundary between the peripheral green part and the center part of the mark and the conductor can be easily distinguished. There is no positional deviation between the pattern and the alignment is extremely accurate.
Die bonding and wire bonding can be performed accurately and automatically at predetermined locations.
以下図を引用して本発明の実施例について説明
する。第1図の平面図、第2図の断面図におい
て、セラミツク基板1の上に導体ペーストの印
刷、焼成により厚膜導体2および3が形成されて
いる。位置合わせマーク4は暗色部41と中央の
明色部42とからなり、例えば先ず抵抗体パース
トの印刷焼成により暗色(黒色)部41を形成
し、ついで金ペーストの印刷焼成により明色(金
属色)部42が形成される。暗色部41は混成集
積回路の厚膜抵抗(図示せず)と、明色部42は
厚膜導体2,3と同時に印刷焼成することができ
る。
Embodiments of the present invention will be described below with reference to the drawings. In the plan view of FIG. 1 and the cross-sectional view of FIG. 2, thick film conductors 2 and 3 are formed on a ceramic substrate 1 by printing and firing a conductor paste. The alignment mark 4 consists of a dark color part 41 and a light color part 42 in the center. For example, the dark color (black) part 41 is first formed by printing and firing a resistor burst, and then the light color (metallic color) is formed by printing and firing a gold paste. ) portion 42 is formed. The dark color portion 41 can be printed and fired at the same time as the thick film resistor (not shown) of the hybrid integrated circuit, and the light color portion 42 can be printed and fired simultaneously with the thick film conductors 2 and 3.
このような暗色部41と明色部42とからなる
位置合わせマーク4、両部の色調の相違により通
常のパターン認識機によつて判別して明確な2値
化信号を出すことができ、その信号に基づいて半
導体チツプ5の導体2の上へのダイボンデイン
グ、チツプ5と導体3を接続するリード線6のワ
イヤボンデイングを所期の通りに実施することが
できる。 Due to the difference in color tone of the alignment mark 4 consisting of the dark color part 41 and the light color part 42, a normal pattern recognition machine can distinguish it and output a clear binary signal. Based on the signal, die bonding of the semiconductor chip 5 onto the conductor 2 and wire bonding of the lead wire 6 connecting the chip 5 and the conductor 3 can be carried out as desired.
またマーク4の位置の認識は暗色41と明色部
42との境界43において行われるから、導体ペ
ーストと抵抗体ペーストのスクリーン印刷の位置
ずれがあつても、境界43と導体2,3との間に
は位置ずれはなく、極めて高い精度の位置合わせ
となり、ダイボンデイング、ワイヤボンデイング
は所定の位置で正確に自動的に実施できる。 Furthermore, since the position of the mark 4 is recognized at the boundary 43 between the dark color 41 and the light color portion 42, even if there is a misalignment between the screen printing of the conductor paste and the resistor paste, the position of the mark 4 is recognized between the boundary 43 and the conductors 2 and 3. There is no positional deviation between them, resulting in extremely high precision positioning, and die bonding and wire bonding can be performed accurately and automatically at predetermined positions.
さらに、この実施例では、位置合わせマークと
して抵抗及び導体は、いずれも混成集積回路を構
成する際に行われる抵抗印刷・焼成工程及び導体
パターンの印刷・焼成工程において、それぞれ同
時に形成することができるため組立工数が増える
心配はない。 Furthermore, in this embodiment, the resistor and conductor as alignment marks can be formed simultaneously in the resistor printing/firing process and the conductor pattern printing/baking process, which are performed when constructing a hybrid integrated circuit. Therefore, there is no need to worry about an increase in assembly man-hours.
位置合わせマークは図示した2個所に限定され
ず、位置制度の要求の低い場合には1個所でもよ
く、高い場合には3個所以上設けてもよい。 The positioning marks are not limited to the two locations shown in the figure, but may be provided at one location if the requirements for position accuracy are low, or may be provided at three or more locations if the requirements are high.
以上述べたように本発明に基づく混成集積回路
は基板上に回路の導体と同時に形成される明色部
との回路の抵抗体と同時に形成される暗色部とか
らなら位置合わせマークを有するので、該明色部
と暗色部との境界が光学パターン認識機により判
別がつきやすく、組立工数を増やすことなく、通
常の光学パターン認識機により明確な位置認識信
号を発信させることができ、所定の位置へのダイ
ボンデイングあるいはワイヤボンデイングの自動
化が極めて容易に可能となるため、製造原価の低
減の上に得られる効果は極めて大きい。
As described above, the hybrid integrated circuit according to the present invention has alignment marks on the substrate, which are made up of a light colored part formed at the same time as the circuit conductor and a dark colored part formed at the same time as the circuit resistor. The boundary between the bright color part and the dark color part can be easily distinguished by an optical pattern recognition machine, and a clear position recognition signal can be sent by a normal optical pattern recognition machine without increasing the number of assembly steps. Since it becomes possible to automate die bonding or wire bonding extremely easily, the effect of reducing manufacturing costs is extremely large.
また、導体ペーストと抵抗体ペーストの印刷の
位置ずれがあつても、マークの周緑部と中央部と
の境界と導体パターンと明色の中央部との間に位
置ずれがなく、極めて高い制度の位置合わせが行
える。 In addition, even if there is a misalignment between the printing of the conductor paste and the resistor paste, there is no misalignment between the border between the green peripheral part and the center of the mark and the conductor pattern and the bright center, resulting in extremely high accuracy. can be aligned.
第1図は本発明の一実施例の要部平面図、第2
図は同じく要部断面図である。
1……セラミツク基板、4……位置合わせマー
ク、41……暗色部、42……明色部。
Fig. 1 is a plan view of essential parts of an embodiment of the present invention;
The figure is also a sectional view of the main part. 1... Ceramic substrate, 4... Positioning mark, 41... Dark color part, 42... Light color part.
Claims (1)
的に検出して、半導体チツプを基板上においてボ
ンデイング接続してなる混成集積回路の製造方法
であつて、前記位置合わせマークが、先に回路の
抵抗体と同時に暗色の周緑部を前記基板上に形成
し、次いで回路の導体形成と同時に前記周緑部上
に明色の中央部を形成して設けられることを特徴
とする混成集積回路の製造方法。1. A method for manufacturing a hybrid integrated circuit in which alignment marks set on a substrate are optically detected and semiconductor chips are bonded and connected on the substrate, the alignment marks being first detected by the resistance of the circuit. Manufacturing a hybrid integrated circuit characterized in that a dark colored peripheral green part is formed on the substrate at the same time as the body, and then a light colored central part is formed on the peripheral green part at the same time as the conductor of the circuit is formed. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57029294A JPS58147037A (en) | 1982-02-25 | 1982-02-25 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57029294A JPS58147037A (en) | 1982-02-25 | 1982-02-25 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58147037A JPS58147037A (en) | 1983-09-01 |
| JPH0454377B2 true JPH0454377B2 (en) | 1992-08-31 |
Family
ID=12272218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57029294A Granted JPS58147037A (en) | 1982-02-25 | 1982-02-25 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58147037A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6130240U (en) * | 1984-07-26 | 1986-02-24 | 富士通株式会社 | die bonder |
| WO2007057954A1 (en) * | 2005-11-17 | 2007-05-24 | Fujitsu Limited | Semiconductor device and method for manufacturing same |
| JP4618738B2 (en) * | 2007-08-24 | 2011-01-26 | 日東電工株式会社 | Dicing die bond film and semiconductor chip fixing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56146242A (en) * | 1980-04-16 | 1981-11-13 | Hitachi Ltd | Positioning method of bonding position at fixed position on substrate |
-
1982
- 1982-02-25 JP JP57029294A patent/JPS58147037A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58147037A (en) | 1983-09-01 |
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