JPH0455032B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a video signal processing method in a television receiver or the like, and in particular, to converting a 2:1 interlaced scanning video signal into a sequential scanning video signal. The present invention relates to a scanning line doubling interpolation method used in this case.

(Conventional example) It is well known that the transmission and reception of television images is carried out according to a specific standard television system. The interlaced scanning method has been adopted as a scanning standard, and has the characteristic that it can reproduce an image with a large number of images per second as an image with a large number of images per second. The interlaced scanning method that is widely used in television systems currently in practical use is mainly a 2:1 interlaced scanning method.

By the way, images reproduced by the standard television system that uses interlaced scanning as the scanning standard have long been considered to be satisfactory in practical use, but the performance of each part of the television receiver is Along with this improvement, the demand for improving the image quality of reproduced images has also become stronger, and one way to meet this demand is to convert the video signal according to the interlaced scanning method to the video signal according to the progressive scanning method, for example. , 60 fields per second,
The number of images per second is 30, 2:1 interlaced scanning is performed, and 1
525 video signals are transmitted in a period of 1/60 seconds that can produce a reproduced image with 525 scanning lines constituting one image (262.5 scanning lines constituting one field). Attempts began to be made to convert the format into a video signal to produce a reproduced image.

FIG. 6 is a block diagram showing an example configuration of a conventional scanning line doubling interpolation method used when converting a video signal based on 2:1 interlaced scanning into a video signal based on progressive scanning. 19 in the figure
is an input terminal for the video signal to be processed, and in the illustrated example, the input terminal 19 is the input terminal for the video signal to be processed.
In contrast, a color television video signal (for example, an NTSC color television video signal) in which a brightness signal and a color signal are band-sharing multiplexed within the band of the brightness signal is supplied. has been done.

The color television video signal supplied to the input terminal 19 is separated into a luminance signal Y and a carrier color signal C by a YC separation circuit 20, and is then separated into a luminance signal Y and a carrier color signal C.
is supplied to a scanning line doubling circuit 21, and the carrier color signal C is supplied to a demodulator 22.

The demodulator 22 outputs two color difference signals (RY) and (RY) from the carrier color signal C, and the color difference signal (RY) is supplied to the scanning line doubling circuit 23. Further, the color difference signal (B-Y) is supplied to the scanning line doubling circuit 24. The above-mentioned scanning line doubling circuit 21 converts the luminance signal Y according to the 2:1 interlaced scanning method applied thereto into a luminance signal Y2 according to the progressive scanning method and outputs the same. In the doubling circuit 23, the 2
Color difference signal (R-Y) according to pair-one interlaced scanning method
is converted into a color difference signal (R-Y) 2 according to the progressive scanning method and outputted, and furthermore, the above-mentioned scanning line 2
The doubling circuit 24 converts the applied color difference signal (R-1) according to the 2:1 interlaced scanning method into a color difference signal (R-Y) 2 according to the progressive scanning method and outputs the converted signal.

Now, the color difference signal (R-Y) according to the 2:1 interlaced scanning method is converted into the color difference signal (R-Y) according to the progressive scanning method.
-Y)2 and outputs the color difference signal (B-Y) according to the 2:1 interlaced scanning method, and the color difference signal (B-Y) according to the progressive scanning method. )2, the scanning line doubling circuit 24, etc. shown in FIG. 7a is used because the frequency band (in the vertical direction) of the color signal is relatively narrow. Two signal values y0, which are adjacent in one horizontal scanning period H,
Using the average value of y1 Zy = (y0 + y1)/2 as the interpolated value,
A configuration that can create a new scanning line signal to be inserted between the two horizontal scanning lines described above, that is, a system conversion using a doubling interpolation method using intra-field processing. A device configured to be able to generate interpolated signals is used.

On the other hand, the luminance signal Y according to the 2:1 interlaced scanning method
The scanning line doubling circuit 21 that converts the method into the luminance signal Y2 according to the sequential scanning method and outputs the same may be a doubling interpolation method using in-field processing described with reference to a in FIG. A device configured to be able to generate an interpolation signal by applying system conversion using the doubling interpolation method using interframe processing shown in FIG. 7B is used.

The above-mentioned doubling interpolation method using interframe processing refers to the interpolation of two adjacent frames separated by one frame period (the period indicated by 1/30 seconds in the figure), as shown in FIG. 7b. Average value Zx of signals x0 and x1 = (X0
This method uses +x1)/2 as an interpolation value to create a signal for a new scanning line to be inserted between two horizontal scanning lines.

Now, the mode of interpolation of video signals and the locations of problems in the case of the conventional doubling interpolation method described above will be explained as follows with reference to FIGS. 8 to 11.

α1, α2, α3, α4... shown in Figure 8a.
are the video signals before double interpolation, that is, the luminance signal Y, color difference signal (R-Y),
(B-Y), etc. are present in each horizontal scanning period (1H period) on the time axis, and α1, α2, α3 described above in a of FIG. , α4, . . . are the portions where the horizontal synchronization signal is supposed to exist.

In addition, d of FIG. 8 shows image information α1', α2' in which the information of each part of α1, α2, α3, α4, etc. described above in a of FIG. 8 is time-axis compressed to 1/2.
，
α3′... and image information obtained by compressing the image information of each part of the interpolated signals β12, β23, β34... shown in c in Fig. 8 to 1/2 on the time axis are sequentially and alternately arranged on the time axis. FIG. 3 is a schematic diagram of the scanning line doubled signals arranged in an array.

Next, we will discuss the differences between scanning line doubling interpolation by intra-field processing and scanning line doubling interpolation by interframe processing applied in the case of the conventional doubling interpolation method, and the distortion that occurs in each case. About the 9th
This will be explained with reference to FIGS. 11 to 11.

The figures shown in FIGS. 9a to 9c, respectively, are 2
The position of the pixel generated by the video signal (original signal) before double interpolation and the position where the interpolated pixel should be placed are indicated by white circles, and the position where the interpolated pixel should be placed is indicated by the white circle. By the black circle mark,
Each is displayed on a time-perpendicular two-dimensional space plane, and vertical lines in the image connect pixel positions within the same field.

Each pixel is assumed to be sampled, and its value is assumed to be 0 or more; however, for the sake of convenience, the analog value itself is used instead of a binary number for the sake of convenience. .
In the figure, the numerical value displayed inside the white circle indicating the pixel position represents the numerical value (sample value) of the pixel, and in the illustrated example, the value of the pixel within the area surrounded by the dotted line It is assumed that the numerical value is 1, and the numerical values of pixels outside the above area are 0.

(The meanings of the white circles and numbers displayed in the figure, the meaning of the vertical lines in the figure, and how to set the area, etc., explained in Figure 9 are based on Figure 5 and 1.
The same applies to the cases of FIGS. 0 and 11).

Figure 9a shows an example of a still image in which part of the screen is bright, and Figure 9b shows an example of a moving image in which part of the screen is brightened for a moment.Furthermore,
FIG. 9c is an example of a moving image in which bright parts move from the top to the bottom of the screen.

The drawings shown in FIG. 10 a and FIG. This drawing corresponds to figure a, and in the figures shown in figure 10 b and figure 11 b, the video signal of a moving image in which a part of the screen is made bright for a moment is doubled. This drawing corresponds to b in Fig. 9 showing the arrangement of pixels generated by the video signal (original signal) before being interpolated, and also c in Fig. 10 and c in Fig. 11. The drawing shown in Fig. 9 corresponds to c in Fig. 9, which shows the arrangement of pixels caused by a video signal of a moving image in which a bright part moves from the top to the bottom of the screen. It is.

And a to c in Fig. 10 are a to c in Fig. 9.
11 is a diagram showing a state in which interpolated pixels based on interpolated values obtained by performing intra-field processing on the video signal shown in FIG. a to c in the figure are number 9
A diagram showing a state in which interpolated pixels based on interpolated values obtained by performing interframe processing on the video signals shown in a to c in the figure are inserted at the positions of the black circles in a to c in Fig. 9. It is.

First, interpolated pixels based on interpolated values obtained by performing intra-field processing on a video signal that produces a pixel arrangement as shown in a to c in FIG.
In the figures shown in a to c of Fig. 10, which show the states inserted in the positions of the black circles in a to c of the figures, the case of a moving image in which a part of the screen is made bright for a moment is shown. Figure 10 b
In this case, by inserting interpolated pixels based on the interpolated values obtained by performing intra-field processing at the positions of the black circles in b in Fig. 9, no distortion occurs in the area surrounded by the dotted line. It is clear that the interpolation is performed without any interference.

However, the interpolated pixels based on the interpolated values obtained by performing in-field processing on the still image video signal that produces the pixel arrangement shown in Figure 9a are located at the positions of the black circles in Figure 9a. Looking at the diagram shown in Figure 10 a showing the inserted state, the boundary of the area surrounded by the dotted line before interpolation (the boundary between the part with pixel value 1 and the part with 0 pixel value) is the interpolated pixel. By inserting , the boundary changes to the one shown by the dashed-dotted line in a of FIG. 10, and since the pixel values move up and down for each field, line flicker becomes noticeable at the boundary of the area.

In addition, in-field processing is applied to a video signal that produces a pixel arrangement as shown in c in Figure 9, that is, a video signal of a moving image in which a bright part moves from the top to the bottom of the screen. Figure 10 shows that the interpolated pixel based on the interpolated value obtained is inserted at the black circle position in c of Figure 9.
Looking at the diagram shown in figure c, the boundary of the area surrounded by the dotted line before interpolation (the boundary between the part where the pixel value is 1 and the part where the pixel value is 0) is changed to c in Figure 10 by inserting the interpolated pixel. It can be seen that the border changes to look like a dashed-dotted line, and the width in the vertical direction appears to be wider than the original image.

Next, the interpolated pixels based on the interpolated values obtained by performing interframe processing on the video signal that produces the pixel arrangement shown in FIGS. 9 a to c are located at the positions of the black circles in FIGS. 9 a to c. In the diagrams a to c of FIG. 11, each showing a state in which the image is inserted into a still image, FIG. In the case of a in FIG. 11, even if the interpolated pixel based on the interpolation value obtained by performing interframe processing on the position of the black circle in a of FIG. 9 is inserted at the position of the black circle in a of FIG. , it is clear that interpolation is performed without any distortion occurring in the area surrounded by the dotted line.

However, in the case of b in Figure 11, which shows a video in which a part of the screen is made bright for a moment, the image obtained by applying interframe processing to the position of the black circle in b in Figure 9 is If we look at Figure 11b, which shows that the interpolated pixels based on the interpolated values have been inserted at the positions of the black circles in Figure 9b, we can see that the interpolated pixels are inserted at the positions of the black circles in Figure 9b. The boundary of the area surrounded by the previous dotted line (the boundary between the part where the pixel value is 1 and the part where the pixel value is 0) changes to a boundary as shown by the dashed-dotted line in Fig. 11b by inserting the interpolated pixel. However, as a result, horizontal stripes appear on the screen, albeit only for a moment.

In addition, interframe processing is applied to a video signal that produces a pixel arrangement as shown in Fig. 9c, that is, a video signal of a moving image in which a bright part moves from the top to the bottom of the screen. Looking at c in Fig. 11, which shows that the interpolated pixel based on the interpolated value thus obtained has been inserted at the position of the black circle in c in Fig. 9, it is similar to the case of c in Fig. 10 described above. In addition, the boundary of the area surrounded by the dotted line before interpolation (the boundary between the part where the pixel value is 1 and the part where the pixel value is 0) changes to the boundary shown by the dashed-dotted line in c in Fig. 11 by inserting the interpolated pixel. , it can be seen that the width in the vertical direction appears to be wider than the original image.

(Problems to be Solved by the Invention) As described above, in the conventional scanning line doubling interpolation method, distortion occurs at the boundaries of the reproduced image, resulting in line flickering, image broadening, and striped patterns. There was a need for a solution to this problem.

(Means for Solving the Problems) The present invention provides means for sampling a video signal based on 2:1 interlaced scanning when converting a video signal based on 2:1 interlaced scanning into a video signal based on progressive scanning. , let y1 be the sample value at any time among the sample values obtained by the sampling means, and
The sample value of the sample value y1 one horizontal scanning period ago is
Let y0 be the sample value ``(field period) + (1/2 horizontal scanning period)'' before the sample value y1, and furthermore, let the sample value ``(field period) + (1/2 horizontal scanning period)'' before the sample value y1 be ``(1 field period) - (1/2 horizontal scanning period)"
Letting the subsequent sample value be x1, each sample value x0,
a first intermediate value generating means for obtaining sample values indicating intermediate values of x1 and y0; and each of the sample values described above.
a second intermediate value generation means for obtaining a sample value indicating an intermediate value for x0, x1, and y1, a sample value obtained by the first intermediate value generation means described above, and a second intermediate value generation means described above; Comparing with the sample value obtained by means,
The present invention provides a scanning line doubling interpolation method comprising means for setting the smaller absolute value of the sample values compared as an interpolated value for scanning line doubling interpolation.

(Example) Hereinafter, specific contents of the scanning line doubling interpolation method of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an embodiment of the scanning line doubling interpolation method of the present invention, and FIGS.
The figure is a block diagram showing an example of the configuration of the constituent parts of the scanning line doubling interpolation method shown in FIG. 1, and FIG. FIG. 3 is a diagram used to explain the principle.

First, the principle of construction of the scanning line doubling interpolation method of the present invention will be explained with reference to FIG. In FIG. 4, y1 is a sample value at an arbitrary time, y0 is a sample value one horizontal scanning period before the sample value y1, and x0 is "(field period) + ( 1/2 horizontal scanning period)" previous sample value,
x1 is the sample value after "(1 field period) - (1/2 horizontal scanning period)" with respect to the above sample value y1, and the above four sample values (pixel values) x0, x1, y0, y1 is arranged in a two-dimensional time-perpendicular space. For convenience, the above sample value is assumed to be a positive value including O (corresponding to the fact that when sampling a video signal and converting it from analog to digital, positive logic sampling and quantization is generally performed) ).

Also, Z shown at the center of the four sample values x0, x1, y0, y1 arranged in the time-vertical two-dimensional space is the horizontal scanning line from which the sample value y0 was obtained. This is an interpolated value that should be placed at an intermediate position between the sample value y1 and the horizontal scanning line from which the sample value y1 was obtained.

In the scanning line doubling interpolation method of the present invention, the intermediate value of the sample values x0, y0, x1 and x0, y1,
Scanning line doubling interpolation is performed by using the smaller value of x1 as the interpolated value Z, and the interpolated value Z can be calculated by calculating the following equation. It is determined by

Z=MIN{MID(x0, y0, x1), MID(x0, y1,
x1)} However, MIN (p, q) is the formula to obtain the smaller of pq, and MID (p, q, r) is the formula for p,
This is a formula to obtain an intermediate value between q and r.

Scanning line doubling is performed by applying the principle of the scanning line doubling interpolation method of the present invention described above to a video signal that produces pixel arrangement patterns as shown by a to c in FIG. 9 described above. The result of the interpolated field is
Shown in figures a to c.

As mentioned above, a in FIG. 9 shows an example of a still image in which a part of the screen is bright, and b in FIG. 9 shows an example of a moving image in which a part of the screen is brightened for a moment. Further, c in FIG. 9 is an example of a moving image in which a bright part moves from the top of the screen.

The drawing shown in FIG. 5a shows pixels generated by the video signal (original signal) of a still image before being subjected to doubling interpolation by the scanning line doubling interpolation method of the present invention. a in Figure 9 showing the arrangement of
In addition, the drawing shown in FIG. This is a drawing corresponding to b in Fig. 9 showing the arrangement of pixels generated by a video signal (original signal) before double interpolation, and further shown in c in Fig. 5. The drawing shows the video signal (original signal) before the video signal of a moving image in which a bright part moves from the top to the bottom of the screen is doubled and interpolated by the scanning line doubling interpolation method of the present invention.
The ninth figure shows the arrangement of pixels caused by
This is a drawing corresponding to c in the figure.

As can be seen from a to c in FIG. 5, according to the scanning line doubling interpolation method of the present invention, when the original signal to be subjected to scanning line doubling interpolation is a video signal of a still image. However, even if the original signal to which scanning line doubling interpolation is to be performed is a video signal of a moving image in which part of the screen is made brighter for a moment, or scanning line doubling interpolation is to be performed. Even if the original signal to be output is a video signal of a moving image in which the bright part moves from the top to the bottom of the screen, in either case, the area in the original pixel array {a to c in Figure 9} According to the scanning line doubling interpolation method of the present invention, the interpolation process is performed accurately in the area of the same boundary line as the boundary line of FIG. The drawbacks of the conventional example explained with reference to a to c can be satisfactorily solved.

In the block diagram of FIG. 1 showing an embodiment of the scanning line doubling interpolation method of the present invention, numerals 1 to 3 are delay circuits each configured to have a predetermined delay time, and A video signal x1, which is subjected to scanning line doubling interpolation, is supplied to the delay circuit 1 via a line 1. Further, the video signal x1 is supplied to an intermediate value extraction circuit 4 and an intermediate value extraction circuit 5.

The delay times in the delay circuit 1 and delay circuit 3 described above are respectively "(1 field period) - (1/2
The delay time in the delay circuit 2 is set as "one horizontal scanning period (1H)".

As mentioned above, the video signal x1 supplied from line 1 to delay circuit 1 is converted into signal y1 delayed by "(1 field period) - (1/2 horizontal scanning period)" in delay circuit 1. is supplied to the delay circuit 2 and also to the intermediate value extraction circuit 5 via line 2.
given to.

Delay circuit 2 outputs a signal y1 input thereto with a delay of 1H for 1 horizontal scanning period.
Output y0 and send it to delay circuit 3 and delay circuit 7
It is also supplied to the intermediate value extraction circuit 4 via the line 3.

The delay circuit 3 described above outputs the signal x0 through the line 4, which is a signal x0 that is delayed by "(1 field period) - (1/2 horizontal scanning period)" to the signal y0 input thereto. , its output signal x0 is supplied to an intermediate value extraction circuit 4 and an intermediate value extraction circuit 5.

The two intermediate value extraction circuits 4 and 5 are each configured to be able to output a signal having an intermediate value of the three input signals supplied to them, and Examples of configurations 4 and 5 are illustrated in FIG.

In FIG. 2, U, V, and W are three input terminals to which the three input signals supplied to the intermediate value extraction circuits 4 and 5 are applied individually, and
Q is the output signal of the intermediate value signal. The second mentioned above
When the intermediate value extraction circuit shown in the figure is used as the intermediate value extraction circuit 4, the signal x1 is supplied to its input terminal U, and the input terminal V
The signal y0 is supplied to the input terminal W, and the signal x0 is further supplied to the input terminal W.On the other hand, when the intermediate value extraction circuit shown in FIG. 2 is used as the intermediate value extraction circuit 5, is supplied with the signal x1 at its input terminal U, the signal y1 at its input terminal V, and the signal x0 at its input terminal W.

The intermediate value extraction circuit shown in FIG. 2 is used as either of the two intermediate value extraction circuits 4 and 5 as described above, and it is Since the same intermediate value extraction operation is performed even when used as the intermediate value extraction circuit 5 or as the intermediate value extraction circuit 5, the configuration and operation of the intermediate value extraction circuit shown in FIG. 2 will be described below. In the description, it is assumed that the signals supplied to the three input terminals U, V, and W described above are the signals U, V, and W, respectively. Therefore, when the intermediate value extraction circuit shown in FIG. 2 is used as the intermediate value extraction circuit 4, the three input signals U,
When V and W correspond to the three input signals x1, y0, and x0, respectively, and the intermediate value extraction circuit shown in FIG. 2 is used as the intermediate value extraction circuit 5, the following explanation will be applied. Three input signals U, V,
It is sufficient to consider that W corresponds to the three input signals x1, y1, and x0, respectively.

In the intermediate value extraction circuit shown in Fig. 2, blocks 11, 12, and 13 used as its constituent circuits are each two-input maximum value extraction circuits. As the circuit, for example, one having a configuration as shown in FIG. 3a can be used.

In the two-input maximum value extraction circuit illustrated in FIG. 3A, 19 is a comparator, 20 is a switch circuit, and
0 are supplied with two input signals A and B, respectively.

The above-described comparator 19 outputs a logic 1 signal as a comparison output signal when the two input signals A and B are A>B, and , when the two input signals A and B are A<B and A=B, the comparator 19 is configured to output a logic 0 signal as a comparison output signal. The comparison output signal from the switch circuit 20 is supplied to the switch circuit 20 as its switching control signal.

As mentioned above, the switch circuit 20 to which the switching control signal is supplied from the comparator 19 outputs the signal A when the switching control signal applied thereto is of logic 1; When the switching control signal is of logic 0, the circuit is configured to output signal B.

Two-input maximum value extraction circuits 11 to 1 as described above
3, the two-input maximum value extraction circuit 11 receives the signals U and B as the two input signals A and B.
V is given, and a two-input maximum value extraction circuit 1
2 is given the signals V and W as the two input signals A and B thereto, and furthermore, the two-input maximum value extraction circuit 13 receives the aforementioned two-input maximum value as the two input signals A and B thereto. Extraction circuit 1
Signals output from terminals 1 and 12 are supplied respectively.

Therefore, the maximum value extraction circuit 13 with two inputs outputs the maximum signal among the three input signals U, V, and W given to the intermediate value extraction circuit, and the output signal is obtained by subtraction of the three inputs. It is supplied to circuit 18 as one of its subtraction signals.

In the intermediate value extraction circuit shown in FIG. 2, blocks 14, 15, and 16 used as its constituent circuits are each two-input minimum value extraction circuits. As the circuit, for example, one having a configuration as shown in FIG. 3b can be used.

In the two-input minimum value extraction circuit illustrated in FIG. 3B, 21 is a comparator and 22 is a switch circuit. B is supplied.

The above-mentioned comparator 21 outputs a logic 1 signal as a comparison output signal when the two input signals A and B are A<B, and the two input signals supplied thereto are A and B. Furthermore, when the two input signals A and B are A>B and A=B,
The comparator 21 is configured to output a logic 0 signal as a comparison output signal, and the comparison output signal from the comparator 21 is sent to the switch circuit 22 as a switching control signal. Supplied.

As mentioned above, the switch circuit 22 to which the switching control signal is supplied from the comparator 21 outputs the signal A when the switching control signal applied thereto is of logic 1; If the received switching control signal is a logic 0, the signal B is output.

Two-input minimum value extraction circuits 14 to 1 as described above
6, the two-input minimum value extraction circuit 14 receives signals U and B as its two input signals A and B.
V is given, and a two-input minimum value extraction circuit 1
5 is given the signals V and W as the two input signals A and B thereto, and furthermore, the two-input minimum value extraction circuit 16 receives the aforementioned two-input minimum value as the two input signals A and B thereto. Extraction circuit 1
Signals outputted from 4 and 15 are supplied respectively.

Therefore, the 2-input minimum value extraction circuit 16 outputs the minimum signal among U, V, and W, and that output signal is sent to the 3-input subtraction circuit 18 as the other one of its subtraction signals. Supplied.

In the intermediate value extraction circuit shown in FIG. 2, the block 17 used as its constituent circuit is a three-input adder circuit. The three input signals U, V, and W are added together.

In addition, in the intermediate value extraction circuit shown in FIG. 2, the block 18 used as its constituent circuit is a 3-input subtraction circuit. From the output signal from the 3-input adder circuit 17, which is supplied as a signal, to the output signal from the 2-input maximum value extraction circuit 13 shown in block 13, that is, the output signal is supplied to the intermediate value extraction circuit. The maximum value signal among the three input signals U, V, and W, and the output signal from the two-input minimum value extraction circuit 16 shown in the block 16, that is,
The minimum value signal among the three input signals U, V, and W supplied to the intermediate value extraction circuit is subtracted.

Therefore, the output signal Q sent from the three-input subtraction circuit 18 to the output terminal Q is as follows: Q=U+V+W-MAX(U,V,W)-MIN(U,
This output signal Q is the intermediate value among the three input signals U, V, W supplied to the intermediate value extraction circuit shown in FIG. , that is, the intermediate value.

Therefore, when the intermediate value extraction circuit 4 is the intermediate value extraction circuit 4, the three input signals U, V, and W to it are x1, y0, x0, so that the line from the intermediate value extraction circuit 4 is The signal supplied to the minimum value extraction circuit 6 via 5 is an intermediate value signal among the above-mentioned signals x1, y0, x0, and when the above-mentioned intermediate value extraction circuit is the intermediate value extraction circuit 5. Since the three input signals U, V, W to it are x1, y1, x0, the signal supplied from the intermediate value extraction circuit 5 to the maximum value extraction circuit 6 via the line 6 is as described above. signal
This is a signal with an intermediate value among x1, y1, and x0.

As the above-mentioned minimum value extraction circuit 6, one having the configuration already described with reference to FIG. The smaller of the two signals is applied to the first memory device 8.

Therefore, the output signal Z from the above minimum value extraction circuit 6 is expressed as follows: Z=MIN{MID (x0, y0, x1), MID (x0, y1,
x1)} is the interpolated signal interpolated value).

As the first memory device 8, for example, as shown in FIG. 3c, a configuration in which two line memories (1H delay circuits) 23 and 24 are connected in parallel can be used. In the first memory device 8 described above, when the signal Z is written to one of the line memories, for example, the line memories 23 and 24, the signal Z is written from the other line memory, for example, the line memory 24 (23). The two line memories 23 and 24 sequentially and alternately perform an operation such that a signal Z written one horizontal scanning period ago is read out during a 1/2 horizontal scanning period. It is made possible to do so.

On the other hand, the signal output from the delay circuit 2 described above
In contrast, y0 is the time delay required by the delay circuit 7, that is, the time delay caused in the signal to be processed when the intermediate value extraction circuit performs signal processing in the intermediate value extraction circuits 4 and 5 and the minimum value extraction circuit 6. is written to the second memory device 9 after a time delay equal to .

The second memory device 9 has the same configuration as the first memory device 8 described above, and has two line memories 23 and 23 used in its configuration.
When the signal y0 is written to one of the line memories 24 (24), for example, the line memory 23 (24), the signal y0 is written from the other line memory 24 (23) one horizontal scanning period ago. The input signal y0 is read out during 1/2 horizontal scanning period. The two line memories 23 and 24 are arranged to sequentially and alternately perform such operations every horizontal scanning period.

1/ read out from the first memory device 8 described above.
The interpolated signal Z in a state where the time axis has been compressed to 2 and the second
The signal y0 read out from the memory device 9 and compressed to 1/2 on the time axis is supplied to the switching circuit 10, and is the signal y0 compressed to 1/2 on the time axis. The interpolated signal Z and the signal y0 compressed to 1/2 on the time axis are switching circuit 1.
0 sequentially and alternately, the switching circuit 1
From 0, the interpolated signal Z, which has been compressed to 1/2 on the time axis as described above, and the signal y0, which has been compressed to 1/2 on the time axis, are sequentially arranged alternately. A signal {d in FIG. 8} in the current state is sent to line 7.

A to D in FIG. 8 are schematic diagrams explaining the arrangement of the signals y1, y0, Z and the output signal from the switching circuit 10 on the time axis, and a in FIG.
In the images arranged every 1H of one horizontal scanning period, image information is shown as α1, α2, α3, . . . .
b in FIG. 8 is the signal y0, which is the signal y1 mentioned above.
is a signal delayed by one horizontal scanning period H.

Next, c in FIG. 8 is an interpolation signal Z, and image information β12 in the figure corresponds to image information α1, α2,
Also, image information β23 corresponds to image information α2 and α3,
Furthermore, image information β12, which corresponds to image information β34, corresponds to image information α3, α4, etc.
A state in which β23, β34, etc. are arranged sequentially on the time axis is shown.

d in FIG. 8 is the image information α1, α2, α3...
Image information α1′, α2′, α3′, etc. (original video signal) whose time axis has been compressed to 1/2, and the above-mentioned image information β12
，
Image information β12′, β23′, β34′… (interpolated signals) obtained by compressing the time axis of β23, β34… to 1/2 are sequentially and alternately arranged on the time axis every 1/2 horizontal scanning period. (In FIG. 8, illustration of time delays occurring during signal processing is omitted.)

The signal outputted from line 7 as described above is obtained by doubling the scanning line by the scanning line doubling interpolation method of the present invention, and the signal corresponds to the scanning standard of 2:1 interlaced scanning. The video signal conforming to the progressive scanning standard is converted into a video signal conforming to the progressive scanning standard.

In the embodiments described so far, the sample values x0, x1, y0, and y1 are all positive values including 0, and the signal processing is performed by positive logic sampling quantization. However, in implementing the scanning line doubling interpolation method of the present invention, it is of course possible to use negative logic sample data, and in that case, the sample data shown in FIG. When using the embodiment, it is sufficient to take the absolute value in advance and convert negative logic to positive logic.

In the description of the embodiment, the signals targeted by the scanning line doubling interpolation method of the present invention were luminance signals and color difference signals, but the signals targeted by the scanning line doubling interpolation method of the present invention In this case, it goes without saying that the signal content does not matter as long as the video signal conforms to the 2:1 interlaced scanning standard.

(Effects) As is clear from the above detailed explanation, the scanning line doubling interpolation method of the present invention converts a video signal conforming to the scanning standard of 2:1 interlaced scanning into a video signal conforming to the scanning standard of progressive scanning. When converting the format, a means for sampling a video signal according to the scanning standard of 2:1 interlaced scanning, and a sample value at an arbitrary time among the sample values obtained by the sampling means is set as y1,
In addition, the sample value 1 horizontal scanning period before the sample value y1 is set as y0, and further, for the sample value y1, "(1 field period) + (1/2 horizontal scanning period)"
The previous sample value is x0, and the sample value after "(1 field period) - (1/2 horizontal scanning period)" with respect to the sample value y1 is x1, and each sample value x0, a first intermediate value generating means for obtaining sample values representing intermediate values for x1 and y0; and a second intermediate value generating means for obtaining sample values representing intermediate values for each of the sample values x0, x1 and y1. a generating means;
The sample value obtained by the first intermediate value generation means described above,
Compare the sample values obtained by the second intermediate value generation means described above, and select the smaller absolute value of the sample values compared as the interpolated value for scanning line doubling interpolation. Therefore, according to the scanning line doubling interpolation method of the present invention, even when the original signal to which scanning line doubling interpolation is to be performed is a video signal of a still image, or Even if the original signal to which scanning line doubling interpolation is to be performed is a video signal of a moving image in which a part of the screen is made bright for a moment, or the original signal to which scanning line doubling interpolation is to be performed. Even if the signal is a video signal of a moving image in which the bright part moves from the top to the bottom of the screen, in any case, as shown in Figure 5 a to c}, the original Pixel array {a~ in Figure 9
According to the scanning line doubling interpolation method of the present invention, accurate interpolation processing is performed in the area having the same boundary line as the area boundary line in the area c}. and Figure 11 a~
The drawbacks of the conventional example explained with reference to c. can be satisfactorily eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the scanning line doubling interpolation method of the present invention, FIGS. 2 and 3 are block diagrams of an example of the configuration of component parts, and FIG. 4 is a scanning line doubling interpolation method of the present invention. Figure 6 is a block diagram of an example of the conventional scanning line doubling interpolation method, and Figure 7 is a diagram illustrating the conventional scanning line doubling interpolation method. A diagram for explaining the configuration principle and the operating principle. FIG. 8 is a diagram showing the arrangement of signals on the time axis. FIG. 5 and FIGS.
FIG. 3 is a pixel arrangement diagram for explaining doubling interpolation. 1, 2, 3, 7...Delay circuit, 4, 5...Intermediate value extraction circuit, 6, 14-16...2 signal minimum value extraction circuit, 8, 9...First, second memory device.

Claims (1)

[Claims] 1. A means for sampling a video signal by 2:1 interlaced scanning when converting a video signal by 2:1 interlaced scanning into a video signal by progressive scanning, and a sample obtained by the above-mentioned sampling means. The sample value at any time in the value is y1, and the sample value one horizontal scanning period before the sample value y1 is y0,
Furthermore, for the sample value y1, set the sample value "(1 field period) + (1/2 horizontal scanning period)" before to x0.
Furthermore, for the sample value y1, the sample value after "(1 field period) - (1/2 horizontal scanning period)" is set as x1, and each of the sample values x0, x1,
a first intermediate value generation means for obtaining a sample value representing the intermediate value of y0, and each sample x0,
A second intermediate value generation means for obtaining a sample value indicating an intermediate value between x1 and y1, a sample value obtained by the first intermediate value generation means described above, and a second intermediate value generation means described above. scanning line doubling comprising means for comparing the sample values obtained and determining the smaller absolute value of the sample values subjected to the comparison as an interpolated value for scanning line doubling interpolation; Interpolation method.