JPH0456500B2 - - Google Patents

Description

[Detailed description of the invention]

[Summary] In a system that monitors digital transmission paths by parity checking, in order to increase the operating margin of the circuit, the output of the counter immediately before receiving the relevant frame, and the output of the counter immediately after counting the number of data in the relevant frame. The result of counting the number of data in the corresponding frame is obtained by comparing the numbers. [Industrial Field of Application] The present invention relates to a parity counting circuit for parity checking used as a monitoring system for digital transmission lines, and in particular to a parity counting circuit for highly reliable transmission line monitoring even in high-speed digital transmission lines. This invention relates to a parity counting circuit that enables counting of all bits within a frame. Optical communication systems are being adopted as digital transmission systems, and technological development is actively underway to make them ultra-high-speed, and optical communication systems with a bit rate of 400 Mbps have already been put into practical use. FIG. 2 shows an example of such an optical communication system configuration, and FIG. 3 shows an example of a frame configuration. One frame consists of, for example, eight subframes, and at the beginning of each subframe there is a frame synchronization pulse F ₁ ,
F ₂ , ₁ , ₂ , supervisory control signal SC, parity check bit P, auxiliary data signal AUX, etc. are inserted into the pulse insertion section of the terminal relay devices 1 and 4 and the frame is inserted. Configure.
That is, the speed conversion sections 11 and 22 convert the input data signal to an appropriate speed, and the pulse insertion sections 12 and 2 convert the input data signal to an appropriate speed.
1, the various signals mentioned above are inserted, and the optical transmitter 1
3 and 20, the signal is converted into an optical signal and input into an optical fiber. The intermediate repeaters 2 and 3 amplify the signals transmitted within the optical fiber and relay them to the terminal repeater. Optical receiving section 17 of terminal relay device 1, 4,
The optical signal received at 16 is converted into an electrical signal, and pulse separators 21 and 15 extract the various signals inserted in pulse inserters 12 and 21, and send them to monitoring devices 5 and 9. Conversion part 1
The input data signals inputted to the speed converters 19 and 14 are transmitted to, for example, an exchange or the like. In the above system, the pulse separator 15 separates the frame synchronization pulses F ₁ , F ₂ , ₁ , ₂
Frame synchronization is achieved by , and parity bit P is extracted. Further, the number of data in the frame is counted by a parity counting circuit, and the counting result is compared with the contents of the parity bit P to perform a parity check. If the error rate of the transmission path is sufficiently low, if the content comparison results in an error, it can be estimated that one code error has occurred within the frame. Therefore, by monitoring the parity check results, it is possible to know the bit error rate of the transmission path. The parity check results are sent to monitoring devices 5 and 9. When the code error rate becomes worse than a predetermined value, the monitoring devices 5 and 9 determine that the quality of the transmission path has deteriorated, generate an alarm, and take measures such as switching to a backup system. . Such parity checks are usually performed at the terminal repeaters 1 and 4, but similar parity checks are also performed at the intermediate repeaters 2 and 3 in order to quickly detect the state of the transmission path and deal with failures. Since parity errors may be detected by the monitoring devices 7 and 8 by providing a check function, it is desirable to simplify the control. Furthermore, as mentioned above, there is a need for a parity counting circuit suitable for ultrahigh-speed digital transmission that can count one bit for each frame of data signals transmitted at a bit rate of 400 MHz or more. [Prior Art] FIG. 4 shows a configuration example of an intermediate repeater having a parity check function. The optical signal received by the optical receiver 23 is converted into an electrical signal, and the equalizing amplifier 24
The waveform is shaped and amplified to a certain level. The output signal of the equalization amplifier 24 is input to an identification circuit 25 and a timing extraction circuit 27. The timing extraction circuit 27 extracts a clock component, and based on this clock signal, the identification circuit 25 identifies the digital 11 data signal transmitted from the terminal relay device. The identified digital data signal is again converted into an optical signal by the optical transmitter 26 and input into the optical fiber. The data signal identified by the identification circuit 25 and the clock signal extracted by the timing extraction circuit 27 are input to a frame pattern detection circuit 28. Furthermore, the clock signal is inputted to a frame counter 32 via a gate circuit 31. The frame counter 32 has a frequency dividing function and outputs a frame synchronization pattern from the input clock signal at the insertion positions of frame synchronization pulses F ₁ , F ₂ , ₁ and ₂ shown in FIG. For example, the frame synchronization pattern is “1,”
1,0,0'' pattern is F ₁ , F ₂ , ₁ ,
This is inserted into _F2 . The frame synchronization pattern output by the frame counter 32 and the frame synchronization pattern detected by the frame pattern detection circuit 28 are compared in the comparator circuit 2. If the comparison results match, it means that frame synchronization is achieved. If the comparison results do not match, a signal indicating the mismatch is sent to the synchronization protection circuit 30,
By closing the gate circuit 31, the synchronization protection circuit 30 removes one bit from the clock signal input to the frame counter 32, thereby shifting the timing at which the frame counter 32 outputs the frame synchronization pattern by one clock. By repeating the above operations, frame synchronization of the received data signals is established. With frame synchronization established, frame counter 32 outputs various control signals, ie, signals indicating the bit position of the data signal. In the following explanation, it will be assumed that a frame counter generates a signal indicating the bit position. Although FIG. 4 only shows the configuration of the intermediate repeater, by connecting the output of the identification circuit 25 to the pulse separator shown in FIG. 2, the same configuration as the terminal repeater can be obtained. . Next, regarding the parity counting circuit shown in FIG. 4, the configuration of the conventional parity counting circuit is shown in FIG. 7, and its operation will be explained using the time chart of FIG. 8. The RZ waveform received data (a) is input to the NOR circuit 37 via the inverter together with the inhibit pulse (b) output from the frame counter.
A NOR37 output (c) from which various control signals inserted by the pulse insertion section of the terminal relay device are removed is generated. This is only the data signal extracted. The NOR37 output (c) is input to a binary counter 35 constituted by a D-type flip-flop, and the number of "1"s in the NOR37 output is counted. Therefore, the binary counter output (e) is "0" when its initial state is "0", "0" when the number of "1"s is an even number,
When the number is odd, it becomes "1", which corresponds to even parity. Conversely, when the initial state is "1", if the number of "1"s is even, it becomes "1", and if it is odd, it becomes "0", corresponding to odd parity. In this way, after counting up to just before the AUX bit of the nth frame, the frame counter inputs the read pulse (f) to the C terminal of the D-type flip-flop 36, and the frame counter inputs the read pulse (f) to the C terminal of the D-type flip-flop 36.
The output state immediately before the AUX bit is held in the D-type flip-flop 36. That is, the D-type flip-flop serves as a memory. When the counting result of the binary counter 35 is held in the memory 36 (position x ₂ in the counting result (g) in FIG _. 7), the frame counter generates a reset pulse ( d) is output to the binary counter 35, and the output state of the binary counter 35 is reset to the initial state. Thereafter, similar operations are repeated to count the number of "1"s after the data signal in each frame. The counting result held in the memory 36 is extracted by the parity bit extraction circuit 33 at the Pn bit position using the parity bit extraction pulse h output from the frame counter, and its output (j) (parity bit content) is extracted by the parity extraction circuit 33 at the Pn bit position. Pn) and EOR38 to perform a parity check. [Problems to be Solved by the Invention] In the above explanation, if there is no gap of several bits or more between the AUX bit and _F1 bit in the shaded part in Figure 8, that is, in the received data (a). Counter 35 cannot be operated. this is,
Read pulse between AUX bit and F bit
This is because after generating (f) and reset pulse (d) in succession and holding the counting results, it is necessary to return the binary counter to its initial state in order to count the number of data in consecutive frames. . In particular, the read pulse (f)
must be generated after the binary counter 35 has counted to just before the AUX bit, and must be delayed a little from the AUX bit position, as shown in FIG. Conventionally, this was dealt with by devising the frame structure, such as by providing a blank space of several bits between the AUX bit and the _F1 bit. In other words, if the operating speed of the circuit elements is increased to an ultra-high speed, it is possible to read the counting results and reset the binary counter 35 using only 2 bits, the AUX bit and the _F1 bit, but as mentioned above, it is possible to read the counting results and reset the binary counter 35. When it comes to bit rates,
Manufacturing circuit elements that operate faster than this is difficult and extremely expensive. An object of the present invention is to eliminate the need for manipulating the frame structure to provide blank spaces between counting intervals as in the past, and to enable data counting without using expensive high-speed circuit elements. It is in. [Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of the present invention.
As shown in the figure, the above problem is caused by a counter 100 that counts the number of received data.
and a comparison circuit 102 that detects whether the count value of the counter immediately before receiving the frame and the count value of the counter immediately after counting the number of data of the frame match. This problem can be solved by using the output of the comparison circuit as the counting result of the frame. [Operation] The counting result of the frame changes depending on the initial state when the counter 100 starts counting the frame. This initial state is determined by the output of the counter 100 immediately before receiving the frame, so by comparing this information with the output of the counter immediately after counting the frame, it is possible to determine the initial state of the frame. You can know the number of data. [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 5a is a circuit diagram of a parity counting circuit according to an embodiment of the present invention, and FIG. 6 is a time chart of various parts of the circuit of FIG. 5a. Note that in FIG. 5, parts corresponding to those in FIG. 1 are given the same symbols, and a, b, and c in FIG.
The bits are the same except for those between b, c, AUX bit and _F1 bit. In the parity counting circuit, a binary counter is used to count the number of data, but as described above, the output result of the binary counter differs depending on its initial state. Fig. 6 c' shows the binary counter 40 of Fig. 6 c.
In particular, the input data to the
It shows the break between the frame and the (n+1)th frame. 2 in the last m bits of the n-1th frame
The output state of the decimal counter 40 is “1” or “0”
can be taken. If the binary counter 40 is not reset and the next nth frame is counted in this state (initial state), the following four output states are possible for the final m bits of the nth frame.

〔Effect of the invention〕

As explained in detail above, according to the present invention,
Since the comparator circuit obtains the counting results for parity check by simply comparing the counting results of the n-1th frame and the nth frame,
There is no longer a need for complex processing such as reading out counting results and resetting binary counters at frame boundaries as in the past, and even for high-speed data, it is possible to count the number of data across all bits in a frame. becomes. Furthermore, with the above configuration, the number of data can be counted across all bits in a frame even in ultra-high-speed digital transmission, so the number of data can be counted without converting to low-speed data by speed conversion of the data signal. Since the configuration is simplified, intermediate repeaters and the like can also be actively provided with a parity check function.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is an example of a digital transmission system configuration, Fig. 3 is an example of a frame structure, Fig. 4 is a block diagram of an intermediate repeater having a parity check function, and Fig. 5 6 is a time chart of various parts of the circuit shown in FIG. 5, FIG. 7 is a conventional parity design circuit, and FIG. 8 is a time chart of various parts of the circuit shown in FIG. 7. . In the figure, 100 is a counter and 102 is a comparison circuit.

Claims (1)

[Scope of Claims] 1. A counter that inverts its output every time "1" of received data is input and counts the number of "1"s of the received data, and the counter immediately before receiving the frame. and a comparison circuit that detects whether the count value of the counter matches the count value of the counter immediately after counting the number of data of the frame, and the output of the comparison circuit is used as the counting result of the frame. A parity counting circuit characterized by: 2. The parity according to claim 1, further comprising a counter that inverts the output every time a "0" of the received data is input and counts the number of "0"s of the received data. Counting circuit.