JPH0458120B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to semiconductor memory integrated circuits.

(Prior Art) The degree of integration of semiconductor memory integrated circuits (hereinafter referred to as memory ICs) is increasing, and their reliability is also required to be higher and higher.

Generally, when testing a memory IC, it is checked whether normal operation is performed between one bit and all other bits, and this is performed for all bits, so the number of times that an N-bit memory is tested is proportional to ^N2 . Therefore, as the scale increases, the time required for inspection increases rapidly, and the efficiency of using expensive measuring instruments deteriorates. For this reason, it is desired to shorten the inspection time.

On the other hand, memory ICs are generally tested using external terminals, so even if there is some deterioration such as leakage in the elements that make up the memory unit, it often appears to be operating normally. ``Some deterioration'' becomes ``major deterioration'' over time, and there is a risk that it may malfunction. Therefore, in order to obtain high reliability, memory ICs having such "slightly deteriorated" elements must be detected and eliminated, but this has been difficult with conventional technology.

(Object of the Invention) An object of the present invention is to provide a semiconductor memory integrated circuit which can shorten test time and provide high reliability by eliminating the above-mentioned drawbacks.

(Structure of the Invention) The semiconductor memory integrated circuit of the present invention uses a memory circuit based on a flip-flop circuit in which the base and collector of two two-emitter type bipolar transistors are mutually orthogonally coupled as a memory unit, and the memory The unit connects the end of the load element on the collector side to one word line, one emitter is connected to one and the other digit line, respectively, and the other emitter is commonly connected to the other word line. In a semiconductor memory integrated circuit in which a plurality of memory units are arranged to form a column, and a plurality of the columns are arranged substantially in parallel to form a matrix of memory units,
an ohmic element is connected between at least one of the one word line and the highest potential power supply; an ohmic element is connected between the one and the other digit line and the lowest potential power supply; is connected to the anode of a diode, and the cathode of the diode is connected in series with the lowest potential power supply via one ohmic element.

(Function) According to the present invention, as shown in FIG. 1, the word line W _T forming the high potential side end of the memory unit C is connected to the highest potential power supply V _CC with a high resistance R _T that does not prevent normal operation. The word line W _B at the low potential end is connected to the lowest potential power supply V EE through a diode T _B and high resistance R′ _B , and the digit lines D _L and D _R are connected to the lowest potential power supply V _EE through high resistance R _L and R _R , respectively. Therefore, if there is a leak in even one of the memory units C, the leak can be directly observed between the external terminals of the power supply V _CC and V _EE . Most leaks occur between the base and emitter of a transistor or between the collector and emitter. A peripheral circuit for normal operation is connected between the power supplies V _CC and V _EE , but this peripheral circuit usually has a two-stage diode forward voltage (2xV _F ).
Current does not flow below approximately 1.4V.
Therefore, if a voltage lower than 2xV _F (for example, 1.0V) is applied between the power supplies V _CC and V _EE , only leakage from the memory element can be observed.

Thus, according to the present invention, since the total leakage of each element constituting a memory unit can be directly observed from the external power supply terminal, the above object can be achieved. That is, if there is a leak in even one bit, the leak can be observed from the outside, so it can be immediately determined that the product is defective. Therefore, the time required to reach a defective bit by testing one bit at a time in the past is no longer necessary, and the testing time can be shortened. Furthermore, since the size of the leak can be directly determined, leaks that are unfavorable in terms of reliability can be eliminated, so the present invention can improve reliability.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention, and represents a bipolar RAM with 4096 bits and 1 output.

In this embodiment, the memory unit C is a memory circuit based on a flip-flop circuit in which the bases and collectors of two two-emitter type bipolar transistors Q ₁ and Q ₂ are cross-coupled with each other. The end of the side load element is connected to one common word line W _Ti (i=0, 1,..., 63), one emitter is connected to each digit line D _Li and D _{Ri, and the other emitter is connected to the digit line D Li and D Ri} . The other word line W _Bi
A memory in which 64 memory cells are commonly connected to each other and arranged in a substantially straight line to form a column, and these 64 columns are arranged substantially in parallel to form a matrix of storage units.
In the IC, each word line W _Ti and the highest potential power supply V _CC
A resistor R _Ti is connected between each emitter of the memory unit C, and each emitter of the memory unit C is connected to the lowest potential power supply V _EE (here, ground potential) and the resistors R _Li and R _Ri and diodes, respectively.
It consists of being connected by T _Bi and resistor R′ _B. In this figure, I _Li , I _Ri , and I _Hi are constant current sources,
Q _W0i is the word line W _Ti driving transistor,
V _CC ′ and V _EE ′ are external power supply terminals for the power supplies V _CC and V _EE .

This embodiment is the same as the conventional one except for the resistors R _T , R _B , R _L , R _R and R' _B and the diode T _B. The structure of the memory unit is 64×64, and the holding current per memory unit is 10 μA, so the current for one word is 640 μA. In this example, a diode is used so that the holding current does not change much due to fluctuations in the power supply voltage.
Flow 40μA to T _Bi . Therefore, the constant current I _Hi in the circuit diagram is
Set it to 600μA, and resistor R′ _B to 1KΩ. Word line W _Ti
The side is kept at a nearly constant voltage at a high or low level by the word line driving transistor Q _Wi , but if the resistor R _Ti is too small, the voltage will shift to the higher side.
If the current flowing through the resistor R _Ti is less than one word of the holding current, this will not prevent operation, but if the current flowing through the transistor Q _Wi decreases too much, this is not desirable for high-speed operation. Therefore, here, the resistance R _Ti is set to 30KΩ. The current is approximately 60 μA. The resistances R _Li and R _Ri on the read/write side do not have much effect on the constant current sources I _Li and I _Ri or the read/write system.
Set to 200KΩ. The peripheral circuit is the same as before, and the voltage between the power supply terminals is equal to two stages of diode forward voltage V _F (approximately
Current does not flow below 1.4V).

FIG. 2a shows the voltage V-current I characteristic between the current terminal V _CC ' and the power supply terminal V _EE '. 4V to 5.5V is the normal operating range.

Figure 2b shows an enlarged view of the situation near 0V. The case where there is no leak in the storage unit is shown by a solid line, and the case where there is a leak is shown by a dotted line. In the case of the dotted line, I don't know whether it is on the word line W _Bi side, digit line D _L side, D _R side, between the base and emitter of the transistor, or between the collector and emitter, but in any case, there is a leak somewhere. I understand.

Therefore, an IC memory in which a leak is detected in this manner is easily rejected as a defective product.

In addition, as shown by the broken line in Figure 1, the diode
T _Bi is used to connect multiple word lines W _Bi to one resistor R′ _B
Since the number of resistive elements can be reduced by connecting the resistor to the resistor, leakage can be detected without sacrificing the integration density.

Furthermore, in the above embodiments, a resistor was connected between the word line W _Ti , the power supply V _CC , and the power supply V _EE for each emitter, but this may be limited to a particularly required location depending on the case. .

(Effects of the Invention) As described above in detail, according to the present invention, with the above configuration, leaks in the memory unit group can be directly observed using the external power supply terminal, and it is immediately possible to identify a defective product. Since it is possible to reduce the testing time for memory ICs, and to eliminate those that operate normally but have some leakage, it is possible to obtain a semiconductor memory integrated circuit that can improve the reliability of the product.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention, and FIGS. 2a and 2b are characteristic diagrams thereof. C...Memory unit, D _L0 , D ₆₃ , D _R0 , D _R63 ... Digit line, I _H0 , I _H63 , I _L0 , I _L63 , I _R0 , I _R63 ... Constant current source, Q ₁ , Q ₂ ... NPN transistor for memory, Q _W0 , Q _W63 ... NPN transistor for word line drive, R _B0 , R _B63 , R′ _B , R _L0 , R _R63 , R _T0 , R _T63
...Resistance, T _B0 , T _B63 ...Diode, V _EE , V _CC
...Power supply, V _CC ′, V _EE ′ ...External power supply terminal, W _B0 ,
W _B63 , W _T0 , W _T63 ...Word lines.

Claims (1)

[Claims] 1 The memory unit is a memory circuit based on a flip-flop circuit in which the base and collector of two two-emitter bipolar transistors are cross-coupled with each other, and the memory unit connects the end of the load element on the collector side to one word line. one emitter is connected to one and the other digit line, respectively, and the other emitter is commonly connected to the other word line, and a plurality of them are arranged in a substantially straight line to form a column, and the columns are substantially parallel. In a semiconductor memory integrated circuit formed by arranging a plurality of columns to form a matrix of the memory units, an ohmic element is connected between the one word line and the highest potential power supply, and the ohmic element is connected between the one and the other digit lines and the lowest potential. An ohmic element is connected between the power supplies, each of the plurality of other word lines is connected to an anode of a diode, and the cathodes of the plurality of diodes are collectively connected to the lowest potential power supply through one ohmic element. A semiconductor memory integrated circuit characterized by being connected in series circuit with.