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JPH0458903B2 - - Google Patents
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JPH0458903B2 - - Google Patents

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Publication number
JPH0458903B2
JPH0458903B2 JP61008390A JP839086A JPH0458903B2 JP H0458903 B2 JPH0458903 B2 JP H0458903B2 JP 61008390 A JP61008390 A JP 61008390A JP 839086 A JP839086 A JP 839086A JP H0458903 B2 JPH0458903 B2 JP H0458903B2
Authority
JP
Japan
Prior art keywords
gate
product
ram
bits
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61008390A
Other languages
Japanese (ja)
Other versions
JPS62168038A (en
Inventor
Junichi Matsuo
Sadashige Muto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Insulators Ltd
Original Assignee
NGK Insulators Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Insulators Ltd filed Critical NGK Insulators Ltd
Priority to JP61008390A priority Critical patent/JPS62168038A/en
Publication of JPS62168038A publication Critical patent/JPS62168038A/en
Publication of JPH0458903B2 publication Critical patent/JPH0458903B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • G01N21/89Investigating the presence of flaws or contamination in moving material, e.g. running paper or textiles
    • G01N21/8901Optical details; Scanning details
    • G01N21/8903Optical details; Scanning details using a multiple detector array

Landscapes

  • Engineering & Computer Science (AREA)
  • Textile Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は製品の表面欠陥を光学的に高速度で検
査することができる表面欠陥検査方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a surface defect inspection method capable of optically inspecting products for surface defects at high speed.

(従来の技術) 従来の板ガラスや鋼板等の表面欠陥の自動検査
方法としては、第3図に示すように製品の移動方
向に対して垂直方向にスチヤンされたライン像を
レンズ50によりCCDラインセンサ51上に結
像させてその出力信号をA/D変換回路52によ
り2値化し、これをクロツク信号発生器53から
のクロツク信号とアンド回路54で結んで出力す
るとともに、ロータリエンコーダ55等により欠
陥の位置情報を出力して両信号を同時にRAM5
6に取り込ませた後にマイクロコンピユータ57
で演算処理し、良否を判別させる方法が普通であ
つた。ところがこのようなCCDラインセンサ5
1のビツト数は検査精度及び検査視野の点から近
年では1024〜5000ビツトのものが使用されている
ので、RAM56の各行には第4図に示されるよ
うにスキヤン毎に1024〜5000ビツトの欠陥ビツト
情報と欠陥の位置情報が取り込まれることとな
り、情報量が膨大なものとなつて通常のマイクロ
コンピユータでは処理時間がかかり過ぎ、工場で
のオンライン検査に使用するには大型で処理能力
の大きい高価なコンピユータを用いざるを得ない
問題があつた。
(Prior Art) As shown in FIG. 3, in a conventional automatic inspection method for surface defects on plate glass, steel plates, etc., a line image that is stood perpendicular to the moving direction of the product is detected by a CCD line sensor using a lens 50. 51, and its output signal is converted into a binary signal by an A/D conversion circuit 52, which is connected to a clock signal from a clock signal generator 53 by an AND circuit 54 and output, and is detected by a rotary encoder 55 or the like. Outputs the position information and sends both signals to RAM5 at the same time.
6, the microcomputer 57
The usual method was to perform arithmetic processing and determine whether it was good or bad. However, such a CCD line sensor 5
In recent years, 1024 to 5000 bits have been used in terms of inspection accuracy and inspection field of view, so each row of the RAM 56 has 1024 to 5000 bit defects per scan, as shown in Figure 4. Bit information and defect position information are imported, and the amount of information becomes so huge that it takes too long to process on a normal microcomputer, and it is too large and expensive to use for online inspection at a factory. There was a problem that forced me to use a computer.

(発明が解決しようとする問題点) 本発明は上記のような従来の問題点を解決し、
通常のマイクロコンピユータを用いて、検査精度
の低下や検査視野の減少を生じさせることなく製
品の表面欠陥を高速度でオンライン検査すること
ができる表面欠陥検査方法を目的として完成され
たものである。
(Problems to be solved by the invention) The present invention solves the conventional problems as described above,
It was developed with the aim of creating a surface defect inspection method that allows for high-speed online inspection of surface defects on products using an ordinary microcomputer without reducing inspection accuracy or reducing the inspection field of view.

(問題点を解決するための手段) 本発明は製品の移動方向に対して垂直方向のラ
イン像をCCDラインセンサ上に結像させてその
出力信号をA/D変換回路により2値化した後パ
ルス化し、欠陥パルスの発生の都度最初のパルス
の立ち上がりから欠陥許容値を包含するに十分な
ビツト数のゲート信号を発生させて3個のゲート
を同時に開き、第1のゲートからは欠陥ビツト情
報を、第2のゲートからは製品の幅方向の位置情
報を、第3のゲートからは製品の移動方向の位置
情報をそれぞれRAMに取り込ませた後に演算処
理することを特徴とするものである。
(Means for Solving the Problems) The present invention focuses on forming a line image in a direction perpendicular to the moving direction of a product on a CCD line sensor, and converting the output signal into a binary value using an A/D conversion circuit. Each time a defective pulse occurs, a gate signal with a sufficient number of bits to include the defect tolerance value is generated from the rise of the first pulse, and three gates are simultaneously opened, and defective bit information is transmitted from the first gate. is characterized in that the positional information in the width direction of the product is loaded into the RAM from the second gate, and the positional information in the moving direction of the product is loaded into the RAM from the third gate, and then arithmetic processing is performed.

(実施例) 次に本発明を第1図及び第2図により詳細に説
明すると、1は検査される板状の製品であり矢印
方向に一定速度で移動されるものである。2はカ
メラの結像レンズであり、製品1の移動方向に対
して垂直方向のライン像をCCDラインセンサ3
上に結像させる。このCCDラインセンサ3によ
り得られたアナログビデオ信号はA/D変換回路
4により2値化された後、クロツク信号発生器5
から発生されるCCD駆動用のクロツク信号とア
ンド回路6により結合されてパルス化されること
は従来の方法と同様である。しかし従来方法にお
いては第4図に示すようにCCDラインセンサ3
の全ビツトにわたる情報を欠陥ビツト情報として
そのままRAMに取り込んでいたのに対して、本
発明では第2図に示すようにRAMに取り込まれ
る欠陥ビツト情報は大幅に減少させてある。この
理由は次のとおりである。
(Example) Next, the present invention will be explained in detail with reference to FIGS. 1 and 2. Reference numeral 1 indicates a plate-shaped product to be inspected, which is moved at a constant speed in the direction of the arrow. 2 is the imaging lens of the camera, which captures a line image in the direction perpendicular to the moving direction of the product 1 to the CCD line sensor 3.
image on top. The analog video signal obtained by this CCD line sensor 3 is binarized by an A/D conversion circuit 4, and then converted to a clock signal generator 5.
Similar to the conventional method, the signal is combined with the clock signal for driving the CCD generated by the AND circuit 6 and converted into a pulse. However, in the conventional method, as shown in Fig. 4, the CCD line sensor 3
In contrast, in the present invention, as shown in FIG. 2, the amount of defective bit information that is captured into the RAM is greatly reduced, as opposed to the case where the information covering all bits of the data is directly captured into the RAM as defective bit information. The reason for this is as follows.

即ち、一般に製品の外観上の欠陥は重欠陥と軽
欠陥とに区別され、重欠陥は品質特性に致命的な
影響を及ぼす欠陥と、大きさが欠陥許容値を越え
る欠陥であり、軽欠陥は大きさが欠陥許容値以下
であつても数がその種類毎に定められた許容個数
を越える欠陥である。従つて、RAMへ取り込ん
で演算処理すべき欠陥ビツト情報は上記の欠陥許
容値を包含するに必要かつ十分なビツト数を持て
ば十分であり、この欠陥許容値を越える欠陥ビツ
ト情報は一律に重欠陥を表すものとして処理され
てしまうのであるからRAMに取り込む意味が乏
しいことになる。但し、1本のライン像に複数の
軽欠陥が存在することがあるので、欠陥の個数は
正確にカウントする必要がある。
In other words, defects in the appearance of products are generally classified into major defects and minor defects. Major defects are defects that have a fatal impact on quality characteristics and defects whose size exceeds the defect tolerance value, and minor defects are defects that have a fatal impact on quality characteristics. A defect is a defect whose size exceeds the allowable number determined for each type even if the size is less than the allowable defect value. Therefore, it is sufficient that the defective bit information to be loaded into the RAM and processed has a necessary and sufficient number of bits to include the above defect tolerance value, and defective bit information that exceeds this defect tolerance value is uniformly weighted. Since it will be treated as a defect, there is little point in importing it into RAM. However, since a plurality of light defects may exist in one line image, it is necessary to accurately count the number of defects.

そこで本発明ではアンド回路6から欠陥パルス
が発生する都度、単安定回路7により最初のパル
スの立ち上がりから上記の欠陥許容値を包含する
に必要かつ十分なビツト数のゲート信号を発生さ
せ、3個のゲート8,9,10をゲート信号のビ
ツト数だけ同時に開かせる。そして第1のゲート
8からは欠陥ビツト情報をRAM11へ送り、第
2のゲート9からは製品の幅方向の位置情報を、
第3のゲート10からは製品の移動方向の位置情
報をそれぞれRAM11へ送る。この製品の幅方
向の位置情報はCCD駆動用のクロツク信号を分
周回路12で例えば1/64に分周させたうえカウン
タ13で計数して製品1の幅方向を16程度に区
分し、その第何番目の区分に欠陥が存在するかを
示すものである。また製品の移動方向の位置情報
はCCDラインセンサのスキヤンスタートパルス
発生器14からのスタートパルスを分周回路15
により必要に応じて分周し、カウンタ16で計数
して欠陥が第何回目あたりのスキヤンの際に検出
されたかを示す。このようにしてRAM11へ取
り込ませる各情報のビツト数は、通常欠陥許容値
の大きさはCCDラインセンサの全ビツト数の1/2
0以下であるので、例えば2048ビツトのCCDライ
ンセンサ3を使用したときには欠陥ビツト情報に
ついては128ビツトとすれば十分であり、また幅
方向の位置情報は16区分とすれば2進数で4ビツ
ト、移動方向の位置情報も10ビツト取れば十分で
あるから全部で142ビツトで済むこととなる。従
つてRAM11へ取り込ませる情報のビツト数は
従来方法に比較して7/100程度となり、マイクロ
コンピユータ17によつても十分に高速度で演算
処理して良否の判別を行わせることが可能とな
る。なお、1つのライン像の複数個所で欠陥パル
スが発生したときにはその都度情報の取り込みが
行われることは言うまでもない。また本発明は板
状の製品だけはなく、円形の製品の検査にもその
まま利用できるものである。
Therefore, in the present invention, each time a defective pulse is generated from the AND circuit 6, the monostable circuit 7 generates a gate signal with a necessary and sufficient number of bits to cover the above defect tolerance value from the rise of the first pulse. The gates 8, 9, and 10 are simultaneously opened by the number of bits of the gate signal. The first gate 8 sends defective bit information to the RAM 11, and the second gate 9 sends position information in the width direction of the product.
The third gate 10 sends position information in the moving direction of the product to the RAM 11, respectively. The position information in the width direction of this product is obtained by dividing the clock signal for driving the CCD into 1/64, for example, by a frequency dividing circuit 12, and counting it by a counter 13 to divide the width direction of the product 1 into about 16 parts. This indicates in which division the defect exists. In addition, the position information in the moving direction of the product is obtained from the start pulse from the scan start pulse generator 14 of the CCD line sensor by the frequency dividing circuit 15.
The frequency is divided as necessary, and counted by a counter 16 to indicate the number of scans in which a defect was detected. The number of bits of each piece of information that is loaded into the RAM 11 in this way is usually 1/2 of the total number of bits of the CCD line sensor.
For example, if a 2048-bit CCD line sensor 3 is used, 128 bits is sufficient for the defective bit information, and if the position information in the width direction is divided into 16 divisions, it will be 4 bits in binary. It is sufficient to obtain 10 bits of position information in the direction of movement, so a total of 142 bits is sufficient. Therefore, the number of bits of information to be loaded into the RAM 11 is about 7/100 compared to the conventional method, and the microcomputer 17 can perform arithmetic processing at a sufficiently high speed to determine pass/fail. . It goes without saying that when defective pulses occur at multiple locations in one line image, information is captured each time. Further, the present invention can be used as is for inspecting not only plate-shaped products but also circular products.

(発明の効果) 本発明は以上の説明からも明らかなように、
RAMへ取り込ませる情報のビツト数を従来法に
比較して大幅に減少させることができたので、通
常のマイクロコンピユータによつても工場のオン
ライン検査に十分利用できる速度で演算処理を行
わせることができ、しかも検査精度や検査視野の
点では従来法と何等変わるところのないものであ
る。よつて本発明は従来のこの種の表面欠陥検査
方法の問題点を解消したものとして、産業の発展
に寄与するところは極めて大きいものである。
(Effects of the Invention) As is clear from the above description, the present invention has the following advantages:
Since we were able to significantly reduce the number of bits of information loaded into RAM compared to conventional methods, it is possible to perform arithmetic processing at a speed sufficient for use in online factory inspections using a normal microcomputer. Moreover, it is no different from conventional methods in terms of inspection accuracy and inspection field of view. Therefore, the present invention can greatly contribute to the development of industry by solving the problems of conventional surface defect inspection methods of this type.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施に用いられる回路の一例
を示すブロツク図、第2図はRAMの1行に対す
るビツト情報の割付け例を示す図、第3図は従来
法の実施に用いられる回路を示すブロツク図、第
4図はそのRAMへのビツト情報の割付け例を示
す図である。 3……CCDラインセンサ、4……A/D変換
回路、8……第1のゲート、9……第2のゲー
ト、10……第3のゲート、11……RAM。
FIG. 1 is a block diagram showing an example of a circuit used to implement the present invention, FIG. 2 is a diagram showing an example of bit information allocation for one row of RAM, and FIG. 3 is a diagram showing a circuit used to implement the conventional method. The block diagram shown in FIG. 4 is a diagram showing an example of allocation of bit information to the RAM. 3...CCD line sensor, 4...A/D conversion circuit, 8...first gate, 9...second gate, 10...third gate, 11...RAM.

Claims (1)

【特許請求の範囲】[Claims] 1 製品の移動方向に対して垂直方向のライン像
をCCDラインセンサ上に結像させてその出力信
号をA/D変換回路により2値化した後パルス化
し、欠陥パルスの発生の都度最初のパルスの立ち
上がりから欠陥許容値を包含するに十分なビツト
数のゲート信号を発生させて3個のゲートを同時
に開き、第1のゲートからは欠陥ビツト情報を、
第2のゲートからは製品の幅方向の位置情報を、
第3のゲートからは製品の移動方向の位置情報を
それぞれRAMに取り込ませた後に演算処理する
ことを特徴とする表面欠陥検査方法。
1 A line image perpendicular to the moving direction of the product is formed on a CCD line sensor, and the output signal is binarized by an A/D conversion circuit and then converted into pulses, and the first pulse is generated every time a defective pulse occurs. From the rising edge of , a gate signal with a sufficient number of bits to cover the defect tolerance value is generated to simultaneously open three gates, and defective bit information is transmitted from the first gate.
From the second gate, position information in the width direction of the product is transmitted.
A surface defect inspection method characterized in that positional information in the moving direction of the product is loaded into RAM from the third gate and then subjected to arithmetic processing.
JP61008390A 1986-01-18 1986-01-18 Inspecting method for surface defect Granted JPS62168038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61008390A JPS62168038A (en) 1986-01-18 1986-01-18 Inspecting method for surface defect

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61008390A JPS62168038A (en) 1986-01-18 1986-01-18 Inspecting method for surface defect

Publications (2)

Publication Number Publication Date
JPS62168038A JPS62168038A (en) 1987-07-24
JPH0458903B2 true JPH0458903B2 (en) 1992-09-18

Family

ID=11691873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61008390A Granted JPS62168038A (en) 1986-01-18 1986-01-18 Inspecting method for surface defect

Country Status (1)

Country Link
JP (1) JPS62168038A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5354187B2 (en) * 2009-04-15 2013-11-27 Jfeスチール株式会社 Traveling material surface quality judging device and surface quality judging method

Also Published As

Publication number Publication date
JPS62168038A (en) 1987-07-24

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