JPH045993B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an image forming circuit including a shading circuit that causes blurring on a video screen of a video display device such as a video game machine. The screen of these video display devices is represented as a set of dots or pixels designated by a scanning line number Xi and a division number Yj provided along the scanning line. Fields, the sea, the sky, the aurora, the sun,
When expressing an explosion of light, etc., using a blurring technique can create a natural and soft change in color tone, making it possible to create an interesting screen. However, in order to create such a blur using a conventionally known method, the arithmetic unit had to handle multivalued logic that indicates multiple levels of intermediate brightness, which required a high-speed, large-scale circuit or a large amount of color data. This requires a large-capacity memory to store the information, and also requires a complicated program even to generate a simple luminance distribution, resulting in an expensive device. The present invention has been made in view of the above, and its purpose is to easily and reliably form an image including blur on a video screen using an extremely simple circuit and program. This paper relates to an image forming circuit in which the shaded circuit is visible. Therefore, the gist of the present invention is to decode a part of a plurality of clock pulse trains that are normally oscillated for addressing the screen in this type of video display device, and to determine the brightness for blurring. The purpose is to obtain control signals. This clock pulse train is a plurality of pulse trains oscillated to allocate video signals to addresses set on the video screen, and specifies the scanning line addresses determined according to the order in which they are scanned on the screen. This addressing pulse train consists of a set of parallel synchronizing pulse trains for specifying dot addresses, and a parallel synchronizing pulse train for specifying dot addresses determined according to the order in which they are scanned on the scanning line. According to the present invention, all or part of this addressing pulse train is converted into a brightness control signal, thereby producing a blurred pattern. Therefore, in order to specifically produce blurring, it is sufficient to configure the image forming circuit as set forth in claim 1 so that a part of the image appears by the brightness control signal itself. Alternatively, as described in claim 3, the brightness level of a part of the video signal sent from the main control circuit may be controlled by the brightness control signal. Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a video game machine equipped with an image forming circuit according to the present invention, and FIG.
5 through 5 are explanatory diagrams of video screens, FIG. 6 is a time chart illustrating the operation of the circuit shown in FIG. 1, and FIG. 7 is a video game machine equipped with the image forming circuit according to the present invention. FIG. 8 is a block circuit diagram showing yet another embodiment of the shading circuit in the image forming circuit according to the present invention. First, explanation will be given from FIG. 1. FIG. 1 shows an embodiment of a video game machine equipped with an image forming circuit according to claim 1. In FIG. 1, 1 is a game machine, 2 is a video display device, 3 is a control panel operated by the player, 4 is a main control circuit, 5 is a video signal output circuit, 6 is a shading circuit, and 7 is a A clock pulse oscillation circuit, 8 an AND circuit, and 9 a data bus. Output terminal 7-1 of clock pulse oscillation circuit 7,
7-2 and 7-3 respectively oscillate a vertical sweep pulse train P _V for video display, a horizontal sweep pulse P _H and a basic clock pulse H _O for circuit control. These pulse waveforms are shown in FIG. 6, P _V , P _H and H _O. The main control circuit 4 is loaded with programs, pattern data, etc. necessary for the development of the game, and when the player operates the push buttons 3a, 3a on the control panel 3, predetermined information processing is performed based on the operation information. A desired signal is generated in accordance with the pulse trains P _V and _PH . In this embodiment, the output terminal of the main control circuit 4
B ₁ , G ₁ and R ₁ transmit blue, green and red color signals, respectively, for background parts that do not need to be removed. In the illustrated example, this is a signal specifying the color of a uniformly colored background portion, such as the sky 2a, for example. It is assumed that the brightness in this part is 100%. Additionally, blue, green, and red pattern signals necessary for depicting various image patterns and characters are output from output terminals B ₂ , G ₂ , and R ₂ . For example, submersible 2c
This is a signal for making the depth charges and depth charges 2d appear, and these are also displayed at 100% brightness. These output terminals B ₁ , G ₁ , R ₁ and B ₂ , G ₂ ,
The output from R ₂ is sent to a known video signal output circuit 5. This output circuit 5 includes R, G, and B output circuits 5B, 5G, and 5R of the same shape and constant number corresponding to three-color electron guns, and an analog circuit that blanks the outputs of these color-specific output circuits during the retrace period. It consists of 50 switches. The B output circuit 5B includes a buffer register 51B,
Power supply 53B for pull-up, resistance 54B, 55
B, and diodes 56B and 57B.
As described above, the configurations of the other G and R output circuits 5G and 5R are also similar to this. Now, assuming that the sky 2a is represented by GR,
While empty 2a is scanned, buffer register 5
A video signal pulse in state 1 is transmitted from 1G and 51R. During this scanning, if it becomes necessary to make the depth charge 2d appear at B, the output terminal
Since the image signal pulse in state ₁ is transmitted only from B2 and B1, G1, R1 and G2, B2 are in state 0, the outputs of these G, R output circuits 5G, 5R are in state 0, while the outputs of B output circuit 5B generates a video signal pulse in state 1, and the depth charge 2d is displayed as B. The configuration and operation of the output circuit 5 are well known, and when configuring such a screen, in addition to the clock pulse H _O , vertical sweep pulse P _V , and horizontal sweep pulse P _H , the output circuit 5 must be synchronized with scanning. It is also known to generate an addressing pulse train capable of displaying the address of a pixel on a screen, and to perform calculations and scanning control in synchronization with these pulse trains. The addressing pulses consist of a scan line addressing pulse and a dot addressing pulse on the scan line. As shown in Figure 2, the screen displays the address of the scanning line.
The dots are displayed as a set of dots whose positions are designated by Xi and addresses Yj of divisions provided by dividing the screen in the scanning direction, and each of which has a specific three-color luminance designated. In FIG. 2, a scanning line X ₁₈ and a dot X ₁₂ Y ₂₀ are shown filled in black. For example, when the number of scanning lines is 2 ⁿ , the scanning line addressing pulses are n-column pulse trains V ₁ ,
V ₂ , V ₃ ...Vn, and the fastest V ₁ among these pulse trains has _a frequency half that of the clock pulse V ₀ for the scanning line (not shown).
It is assumed that V ₃ , ...Vn have frequencies that are sequentially decreased in binary, and during the period when the scanning line Xi is being scanned, the pulse trains Vn, Vn _-1 , Vn _-2 ...
As the state of V ₁ indicates the binary number corresponding to i,
The duty and phase of each pulse train are matched in advance. Similarly, when the number of dots per scanning line is 2 ^m , the dot addressing pulses are m pulse trains H ₁ , H ₂ , H ₃ . . . Hm, and the fastest among these pulse trains H ₁ has a frequency that is 1/2 of the basic clock pulse H ₀ for dot feeding, and the following:
H ₂ , H ₃ ...Hm have frequencies that are sequentially decreased in binary, and during the period in which the dot Yj is displayed, the above pulse trains Hm, Hm _-1 , Hm _-2
...Configure so that the code indicated by H ₁ indicates the binary number corresponding to j. A model of these pulse trains is shown in FIG. Accordingly, in the present invention, if the dot addressing pulse train is used, a blur having a difference in density in the scanning direction as shown in FIG. 3 can be obtained, and if the scanning line addressing pulse train is used, the The blurring in the direction perpendicular to the scan as shown in the figure can be obtained, and if the circuit is slightly modified so that both pulse trains can be used together, two-dimensional blurring as shown in Fig. 5 can be obtained. . These pulse trains are sent to the shading circuit 6 from the output terminals 1 to 8 of the main control circuit 4. Now, the pulse train sent from these output terminals 1 to 8 is
Dot addressing pulse train H ₁ shown in Figure 6
to _H8 . These pulse trains are all 0 at the end of one horizontal retrace period, but when the sweep begins and the beam is directed to Y ₁ , which is the starting point of the scanning line, H ₁ becomes 1, and the beam then becomes 0. _Y2 , _Y3 , _Y4 ...
As it moves, it changes as shown in Table 1.

[Table] In other words, the binary numbers H ₈ , H ₇ ...H ₁ indicated by the pulse train are:
It is the binary coded number j of dot Yj. In the embodiment shown in FIG. 1, these pulse trains are sent from the output terminals 1 to 8 of the main control circuit 4 to the shading circuit 6. A clock pulse H _O having twice the frequency of H ₁ is sent from the output terminal CP of the main control circuit 4 . The shading circuit 6 includes a decoder that accepts a portion of the addressing pulses oscillated from the output terminals 1 to 8 of the main control circuit 4 and converts it into a desired brightness control signal, and a decoder that converts the output of the decoder as necessary. It is comprised of a circuit that performs opening/closing control in response to a control signal output from terminal S of the main control circuit 4, and superimposes a portion of the video signal transmitted from the main control circuit. In this embodiment, the decoder consists of a latch 60, a ladder circuit 70, and an output circuit 80, and the gate circuit consists of an analog switch 9.
Consists of 0. Latch 60 consists of eight delay bistable elements 61-68. This latch 60
The purpose of using is for synchronous logic. However, this latch is not an essential component since the circuit of the present invention may be operated asynchronously without any particular problem. The ladder circuit 70 is a kind of D/A converter or decoder, and has one terminal connected to each of the output terminals of the D monostable elements 61 to 68 constituting the latch 60.
resistors R ₁ , R ₂ , R ₃ ... R ₈ , resistors r ₁ , r ₂ ... r ₇ connected between the other terminals of the adjacent ones among those resistors, and resistors R ₁ and It consists of a grounding resistor Rg inserted between the connection point of _r1 and the ground line. Thus, the connection point between resistors R ₃ and r ₇ is an output terminal. Therefore, the resistances R ₁ , R ₂ ...R ₃ , r ₁ , r ₂ , ... r ₇ , Rg
It is well known that if the input impedance of the output circuit 80 is appropriately determined, a linear conversion formula can be established between the code input to one terminal of the resistors R ₁ , R ₂ . . . R ₃ and the output current. be. The output circuit 80 is an amplifier circuit and includes a transistor 81, a power supply 82, resistors 83, 84, and a diode 85. Further, the circuit 90 is provided to cut off the output of the output circuit 80 as necessary, and is an analog switch 90 controlled by the output of the main control circuit 4. Main control circuit 4 output terminals B ₁ , G ₁ , R ₁ ; B ₂ ,
When displaying an image on the screen using the signals from G ₂ and R ₂ , the analog switch 90 is turned off by the signal from the output terminal S, and the output from the shading circuit 6 is cut off. The input to latch 60 is a binary code representing the dot address, and therefore the input to ladder circuit 70.
The output of is proportional to the number corresponding to the dot address. This output is amplified by the output circuit 80 and sent to the output circuit 5 via the analog switch 90.
It is superimposed on the output of B. When displaying an image using the output of the shading circuit 6, the outputs B ₁ , G ₁ , and R ₁ of the main control circuit 4 are stopped, and the output S makes the analog switch 90 conductive. Therefore, for example, a screen as shown in FIG. 3, in which the B luminance increases gradually in the scanning direction, can be obtained. In reality, for example, as shown in Figure 1,
The sky 2a and the sea 2b are divided at a certain point, and the sea 2b is displayed with a blurred image of B, and the sky 2a is displayed with a constant brightness.This switching is done by outputs S, B ₁ ,
Performed by G ₁ and R ₁ . That is, while the sea 2b is being scanned, the analog switch 90 is on, and the outputs B ₁ , G ₁ ,
and R ₁ is 0. However, when the sky 2a is scanned, the analog switch 90 is turned off and, for example, the outputs G ₁ and R ₁ are at a high level. On the other hand, when the submersible 2c appears in the area of the sea 2b, output S is generated to turn off the analog switch 90 when scanning the relevant area, and output terminals B ₂ , G ₂ , and R ₂ are turned off instead. Among them, a desired one, for example, one that makes _G2 a high level. When the depth charge 2d is generated in the sky 2a, the outputs G ₁ and R ₁ are cut off, and instead, for example, the output B ₂ is set to a high level. With the configuration of this embodiment, the brightness of the sea 2b increases slightly and linearly for each bit, so that an even and natural blur can be expressed. Next, FIG. 7 will be explained. FIG. 7 shows an embodiment of a video game machine equipped with an image forming circuit according to claim 3. The difference between the embodiment shown in FIG. 7 and the embodiment shown in FIG. The output is not used directly as a video signal, but is used to control the brightness level of the output _B1 of the main control circuit 4 via the brightness control circuit 100. In order to cause blurring in the direction perpendicular to the scanning direction in the sea 20b, the scanning line addressing pulse trains V ₁ ,
V ₂ , . . . V ₈ are sent out, and a clock pulse V ₀ having twice the frequency of V ₁ is sent out from the terminal CP. Also,
The clearing pulse of latch 60 is a vertical sweep pulse.
It is P _V. In this method, the output terminals B ₁ of the main control circuit 4,
From G _1, R _1, B _2, G _2, R ₂ , by a conventionally known method,
The necessary video signals are transmitted to produce a safe image without blur. In other words, sky 2
Assuming that 0a is represented by GR and the sea 20b is represented by B, while the sky 20a is being scanned, a video signal pulse in state 1 is transmitted from buffers 51G and 51R, and the output of buffer 51B is in state 0. When the sea 20b starts to be scanned, a video signal pulse in the state 1 is started to be transmitted from the buffer 51B, and the outputs of the buffer 51G and 51R become in the state 0. This embodiment differs from the embodiment shown in FIG. 1 in that, when scanning the sea 20b to be blurred, a signal for generating an image of the sea 20b is supplied from the main control circuit 4. Note that this signal is used when the brightness control described below is not performed.
The sea 20b can be expressed with 100% brightness of B. Further, since the method of generating the submersible 20c and the depth charge 20d is the same as that of the embodiment shown in FIG. 1, the explanation thereof will be omitted here. The brightness control circuit 100 includes a transistor 101, a power supply 102, and resistors 103, 104, and 10.
5 and 106. Also, Batsuhua 51B
shall be of open collector type. Further, in this embodiment, it is assumed that the scanning starts from the upper left corner of the video screen 20, the scanning lines run from left to right, the scanning lines sequentially move downward, and the scanning ends at the lower right corner. Therefore, the sky 20a is scanned in the first half of each frame, and the sea 20b is scanned in the second half. Therefore, during the scanning period of the sea 20b, the analog switches 90 are turned on except for the part where the submersible 20c is displayed, and the brightness control circuit 10 is turned on.
0 is activated and the B ₁ output goes to state 1.
This is the result. At the beginning of scanning, i.e. the top scan line
While X ₁ is being scanned, the output of the shading circuit 6 is almost 0, but as the scanning progresses with X ₂ , X ₃ . . . increases in proportion to However, since the analog switch 90 is off while the sky 20a is being scanned, this output has no effect on the video signal. When scanning of the sea 20b begins, the analog switch 90 is turned on, and the output of the shading circuit 6 is input to the brightness control circuit 100. On the other hand, the output of the main control circuit _B1 becomes high level, but since the output is grounded through the resistors 105 and 106, the output of the diode 56B is initially lowered to a relatively low level, but the scanning As it progresses, it rises little by little, almost linearly, scanning line by scanning line. Therefore, if the B-electron gun is controlled by this signal, it will be slightly lower, for example 50%, in the upper part of the sea 20b.
The brightness is set to the brightness level of
It is possible to achieve 100%. Therefore, in this embodiment, as in the embodiment shown in FIG. 1, natural and soft blurring can be obtained. Note that the configuration of the brightness control circuit 100 described above is almost the same as the output circuit 80 of the shaded circuit 6, so
In this embodiment, it is also possible to omit the output circuit 80. Note that the configuration of the present invention is not limited to the above-mentioned embodiments. First, in the embodiment described above, the entire dot addressing pulse train or scanning line addressing pulse train shown in _FIG . It is sufficient to use only _{H 6.} Furthermore, the same purpose can be achieved by using only H ₁ and a circuit as shown in FIG. Here, 600 is a counter and 700 is a decoder. In this example, it appears that only H ₁ is used, but in reality, H ₁ to _{H 8} are used.
This is an embodiment of the present invention. Also, as already mentioned, latch 60
is not essential, and the present invention does not necessarily require synchronization logic, so it is not necessary to use it.Also, even if synchronization logic is provided,
It is possible to freely employ latches, registers, buffers, etc. using circuit elements other than D-bistable elements. In addition, in the above embodiment, H ₁ to H ₈
is introduced directly into the latch 60, but it may be possible to insert an appropriate converter, adder, etc. in between, depending on the case. Furthermore, if the set output of each D bistable element of this latch 60 is configured to be fed back to its respective input section and self-maintained, the increase in brightness will no longer increase at a constant width for each dot, and the brightness and brightness will be The width of the constant area will now change in binary. More specifically, the correspondence between the input of the ladder circuit 70 and the dot address is as follows. Ladder circuit input dot address 00000001 1 00000011 2 to 3 00000111 4 to 7 00001111 8 to 15 : : : : 11111111 128 to 255 Therefore, with such a configuration, it is different from the case of linear luminance change described above. Different blur patterns can be created. In this case, the brightness change step can be freely set by appropriately changing the distribution of the resistances of the ladder circuit. Furthermore, the configuration of the decoder is not limited to only the ladder circuit 70, and any device such as a D/A converter, regardless of its name, can achieve the same effects within the scope of the purpose of the present invention. Everything can be used. Further, as the brightness control circuit 100, an amplifier such as an operational amplifier whose gain can be controlled, an attenuator, etc. can be used. Furthermore, in the embodiment described above, the shaded circuit 6
Although the output of is coupled only to the B output circuit 5B,
This can also be coupled to the G, R output circuits 5G, 5R, and in that case, the number of shaded circuits can also be not only one but a plurality. Further, the use and purpose of the display device embodying the present invention, the configuration of each part circuit, etc. are not limited to the above description, and the present invention can be applied to any known device. The invention encompasses all of them. Since the present invention is constructed as described above, it is possible to freely create complicated and brilliant blurring using extremely simple circuits and programs, and to construct an interesting and fantastic screen. It is possible.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a video game machine equipped with an image forming circuit according to the present invention, and FIG.
5 through 5 are explanatory diagrams of video screens, FIG. 6 is a time chart illustrating the operation of the circuit shown in FIG. 1, and FIG. 7 is a video game machine equipped with the image forming circuit according to the present invention. FIG. 8 is a block circuit diagram showing yet another embodiment of the shaded circuit in the image forming circuit according to the present invention. DESCRIPTION OF SYMBOLS 1... Game machine, 2... Video display device, 3... Control panel, 4... Main control circuit, 5... Video signal output circuit, 6... Shading circuit, 7... Clock pulse oscillation circuit, 8... AND circuit, 9...
data bus.

Claims (1)

[Claims] 1. A plurality of clock pulse trains oscillated in parallel, including a set of parallel synchronizing pulse trains specifying scanning line addresses determined according to the order in which they are scanned on the screen, and It has a circuit that oscillates a plurality of addressing pulse trains consisting of a set of parallel synchronous pulse trains that designate dot addresses determined according to the order of scanning, and a predetermined program according to input from the control panel 3. a main control circuit 4 for generating a desired video signal in accordance with the addressing pulse train and in synchronization with the addressing pulse train; and converting the video signal output from the main control circuit 4 into a signal necessary for producing an image on the video display device 2. An image forming circuit comprising an output circuit 5 and an output circuit 5, which is characterized by being provided with a shading circuit having the components described in (a) to (c) below. An image forming circuit that produces (a) A decoder 70 that receives at least a portion of the addressing pulse train and converts it into a desired brightness control signal. (b) An output circuit 80 connected to the output side of the decoder 70. (c) A circuit 90 for controlling the output of the output circuit 80 intermittently in response to the control signal output from the main control circuit 4 and superimposing it on a corresponding signal among the signals output from the output circuit 5. 2. A plurality of clock pulse trains oscillated in parallel, including a set of parallel synchronization pulse trains that specify scanning line addresses determined according to the order in which they are scanned on the screen, and It has a circuit that oscillates a plurality of addressing pulse trains consisting of a set of parallel synchronizing pulse trains that designate a predetermined dot address. a main control circuit 4 that generates a desired video signal in synchronization with the main control circuit 4; and an output circuit 5 that converts the video signal output from the main control circuit 4 into a signal necessary for producing an image on the video display device 2. An image forming circuit for a video display device comprising a blurred image on the screen of the video display device, characterized in that the image forming circuit is provided with a shading circuit comprising the components described in (a) to (d) below. An image forming circuit that produces (a) A latch 60 for receiving at least a portion of the addressing pulse train. (b) A decoder 70 connected after the latch 60 and receiving the addressing pulse train inputted through the latch 60 and converting it into a desired brightness control signal. (c) An output circuit 80 connected to the output side of the decoder 70. (d) A circuit 90 that performs intermittent control on the output of the output circuit 80 in response to a control signal output from the main control circuit 4 and superimposes it on a corresponding signal among the signals output from the output circuit 5. 3. The latch 60 is an N-bit latch, and the decoder 70 connects N parallel resistors R ₁ , R ₂ , R ₃ , each having one terminal connected to each of the N-bit output terminals of the latch 60. ...R _N , and the adjacent resistances R _i and R _i+1 of the above parallel resistances (however, i=
1, 2, 3,...N- ₁ ,), and the above parallel resistance.
A ladder circuit consisting of a grounding resistor Rg inserted between the connection point of R ₁ and series resistance r ₁ and the earth line, and an output terminal connected to the connection point of the parallel resistance R _N and series resistance r _N-1. 70. The image forming circuit according to claim 2, which is 70. 4. The image forming circuit according to claim 3, wherein the output circuit 80 amplifies the output of the ladder circuit 70, converts it into a desired brightness control signal sequence, and outputs the signal.