JPH0462091B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for displaying graphics on a video screen display device in a graphics mode, and the present invention relates to a system for displaying graphics on a video screen display device in graphics mode. The present invention relates to a system for displaying graphics by scanning frames line by frame and line by line.

Such systems typically include a composite memory with some paged memory, a central processing unit (CPU) to control the memory, the display element itself, input peripherals for the data to be displayed, and perform certain image processing functions. It also includes a video processor to match the processing speed of various peripheral devices with that of the central processing unit.

A disadvantage of conventional systems is that the speed at which images are constructed is dependent on the processing speed of a relatively slow central processing unit.

In configurations that use a microprocessor as the central processing unit, access to read-only memory (ROM) that stores programs or random access memory (RAM) that stores data is performed on two separate buses. It is carried out with One is for data and the other is for address. The control bus carries signals for access to the memory (drive, read, write, etc.). Such known configurations are particularly useful when a 16-bit data bus is used and address fields of 64K words or more are present, since the number of "pins" on the central processing unit becomes very large (e.g., more than 40 pins). It has serious drawbacks.

Advances in integration technology in terms of speed and density have improved the methods of accessing memory external to central processing units and reduced the number of "pins" on the integrated circuits that make up these devices.

Therefore, instead of using two buses to circulate data and addresses, time multiplexing has now made it possible to send data and addresses on one bus, allowing one cycle of external memory to be sent. However, in response to the manipulation of the address field and the subsequent manipulation of the data field, these are now controlled by control signals generated by the central processing unit.

The purpose of the present invention is to use this new technique to increase the processing speed of image synthesis signals, freeing the central processing unit from some tasks and freeing the central processing unit to handle other tasks. The aim is to make it possible to do these things at the same time.

It is therefore an object of the invention to provide a system for displaying on a video screen in a graphical mode, in which the information to be displayed is defined by point-by-point scanning of the frame on the screen. The information is provided from a page memory containing all the video information to be displayed at a given moment, and the system has one or more receiving channels for the video information to be displayed. It includes a central processing unit connected to peripheral devices and further connected to a video display processor, the video display processor itself being connected to a random access memory including the page memory mentioned above, and further connected to a display control unit for processing prepared images in memory. information on the screen into control signals for the screen, and the central processing unit
It is characterized in that it is connected to the video processor by a bus line, and addresses and data are transmitted on the bus line in a time-division manner.

The invention will be explained in more detail below with reference to the drawings.

Before examining the drawing in detail, let us briefly discuss the principle of displaying figures on the visualization screen.

Images are generated at a frame frequency, with each frame being generated by line scanning as is well known in the television art.

However, in conventional video systems, the electron guns (red, green, and blue) of the image pickup tube are controlled purely using analog signals, whereas the image synthesis system here uses binary signals to control the electron guns (red, green, and blue). 0, or in more advanced systems,
It is controlled by a digital circuit that provides a "color palette" with all possible phases of midtones.

In this way, each line of the frame is made up of a specific number of points (320 points in a typical example), and each of those points has three bits of three-color element information (R, G, B) requires a total of 120 bytes per line to be scanned on the screen,
If 8 hues were used, 30K bytes would be scanned per frame.

For each display of a frame, bytes containing data about each image point are transferred to a memory called "page memory" by the video display processor in synchronization with the video time axis.
It is read by the VDP and thereby drives certain display functions. This page memory is loaded to the central processing unit CPU as a function of input data, which can be described as a standard teletext broadcast, for example by a television channel or telephone line. VDP also allows changing the processing speed of the display device and CPU from one value to another, allows selecting the input data stream for magazines or flags for pages, and other similar allow the functionality of

FIG. 1 shows the general configuration of such a visualization system. It includes a central processing unit CPU1 coupled to one or more of the information sources to be displayed. These sources may be a telephone line 2 with information in the form of teletext, a local keyboard 3 or any other source, such as, for example, a video game device. CPU is VDP
It is connected to a processor 4, and the VDP processor itself is connected to a random access memory 5 having an area constituting a page memory. The VDP is connected to a display screen 6. The memory 5 communicates with the VDP 4 by an address bus 7 and a data bus 8. This data bus is connected to an adaptation circuit 9 (called "didon" in the literature) which performs the extraction of the video signal carried by a high-frequency television carrier, for example through an electromagnetic line. Here, the teletext information is multiplexed with the television signal of a conventional television channel (eg "Antiope"). The adaptation circuit 9 connects the receiver 1 to the antenna 11.
Receives input signal from 0. (“Anteiope”
A summary description of the system can be found in “La
Technique de 1 Inge′nieur” (industrial technology)
Given in E.3129. ) According to the present invention, the CPU 1 and the VDP 4 are connected by a common bus 12, and the address field and data field circulate on the bus in a time-sharing manner.
The allocation of these information fields is performed by the CPU 1 using a signal CM (mode control). This CM signal is the address latch AL transferred on control line 13, data drive (enable)
It is sent in addition to the conventional signals of EN and read/write R/W. When the signal CM is "1", the situation is as follows.
This occurs as the memory RAM 5 is directly connected to the CPU 1 and controlled by conventional signals AL, EN, R/W. When signal CM is "0", address fields loaded by normal signals are interpreted as instructions to processor 4.

FIG. 2 shows a time relationship diagram of memory cycles.
The signals on bus 12 are time multiplexed for each memory cycle and address field 14
and data field 15. Bus line 12
Assignment to an address field or a data field is indicated by reference numerals 16, 17, respectively.
It is controlled by signals AL, RW, and EN shown at 18.

The information from the CPU contained in address field 14 is used in two ways.

1 information may represent the address itself for storing the data field corresponding to the considered address field into the memory 5 while being transmitted through the VDP 4. and it is
Stored in the address contained in the address field that is allowed to be forwarded through VDP (if CM is 1).

2 Information may represent a particular display function by which the VDP is configured into a particular functional configuration. The read-behind data field is processed according to the function (if CM is 0).

FIG. 3 shows a general configuration of VDP 4 for processing address fields of CPU 1, such as display function instructions, and also shows a configuration of VDP 4 to employ a transparent configuration. In that case,
CPU 1 supplies the address and data fields, which are directed directly to memory 5, or the CPU supplies data from memory.
It is received as a function of the address that the CPU directly gives to this memory.

VDP4 has an internal bus 19, in which the CPU
1. All information exchanges occurring between the memory 5 and the display device body (screen 6) are circulated.

The internal bus 19 is bidirectional and will be referred to as DMA
The address field and data field are transmitted in a time-sharing manner under the control of a direct memory access device 20 called . This device was developed by the applicant.
It may be of the same type as described in French Patent Application No. 7731140 filed October 17, 1977. DMA
is the time axis circuit 2 synchronized with the scanning of the screen 6.
Operates in conjunction with 1.

The CPU 1 is connected to the VDP 4 by a bus 12. The bus 12 has four parallel registers 22,2
It is connected to groups 3, 24, and 25. Register 22 is a data register in which each data field is temporarily stored before being transmitted onto internal bus 19 leading to memory 5. This register also carries an address field for directly addressing this memory. It is a field that does not specify functionality for VDP4.

Register 23 is a mask register that stores a binary value, and the number is decremented each time a specific function is executed.

Register 24 is a control register. It is involved in performing other functions during VDP, as described below.

Register 25 is a transfer register for the function code represented by the address field provided by CPU 1, the contents of which represent the particular function to be performed. This register is
The address field in question makes VDP opaque and is only driven when the CPU indicates it is ready to perform the given function. The register 25 for the transfer of function codes is connected to a decoder 27 which, by receiving the given code, outputs an output 28.
selectively supplying a drive signal to the top, which signal is coupled to a register of VDP under the control of line 26;
A signal CM is transmitted on line 26. In other words, for each code received, it is allowed to send a drive signal on a particular number of outputs 28 that drives a register in the VDP, and that register
It intervenes in the process of executing the function represented by the code sent from CPU 1 through transfer register 25. The decoder has a specific output 29, which drives the DMA 20 if the internal control of the VDP or more particularly the time division of the bus 19 is to be guaranteed.

As well as the status register 30, a control register 24 and dual intermediate registers 31a, 31 contain the internal status of the VDP at each moment and the instructions in the execution process.
b are all connected to bus bar 12. Dual registers 31a, 31b are coupled to register stack 33 and associated arithmetic and logic unit ALU 32.

The mask register 23 is connected to a modification register 34 whose inputs and outputs form a loop on the internal bus 19. This bus line is connected to a data register 35 and an address register 36 on the memory 5 side, which are directly connected to the memory 5.

The output interface 37 adapts the display data sent on the internal bus 19 from all the circuits of the VDP, the CPU 1 and the memory 5 to the display circuit body of the screen 6.

Register stack 33 includes the following registers:

BAPA - first address of the page BAGT - first address of control memory BAMT - first address of buffer memory ACMT - buffer memory pointer assigned to Deidon circuit 9 (FIG. 1) BAMTF - pointer of end of buffer memory ACMP - CPU Buffer memory start pointer ACPA - Page memory read pointer ACGT - Control memory pointer PX, PY - CPU processing pointer The visualization device includes a composite memory 5 composed of page memory, control memory, and buffer memory. Preferably, the whole is a single integrated circuit. Furthermore, it is advantageous that the limits assigned to these memories in this integrated circuit are not physically defined, but only by the starting and/or ending addresses of the memories, thereby making it possible to Overall functional flexibility is increased. This limit therefore changes over the course of processing as a function of the amount of information storage required at any given time.

The buffer memory 5 (FIG. 1) adapts the processing speed of the Deidon circuit 9 to the speed of the CPU 1, as described in French Patent Application No. 80.26393 of December 12, 1980 by the inventor.

To explain the function of the VDP circuit 4 and its functional operation for displaying images on the screen 6, reference will be made successively to FIGS. 3 through 8. These drawings show connections that transmit information when performing the targeted compositing function.

A - Figure 3 - Direct access to memory 5 by the CPU (VDP transparency) This function allows the compositing of images under direct control of the CPU, the updating of the page memory during modification of the image to be displayed, without VDP intervention. Executes other instructions. Therefore, in the process of performing this function
VDP is transparent.

This cycle is performed as follows.

Driven by signals AL and CM being "1" and provided with an address field by the CPU, the decoder 27 issues an access request to the circuit 20, thereby causing this circuit 20 to access the internal bus. 19 access cycles, thereby making it transparent.
The VDP can access the memory 5 using the address given to the address field of the CPU and write the data contained in the data field.

Of course, this process can be reversed and the CPU can also read information from memory 5 during the execution of this function.

B - Figure 4 - Access to VDP's "program" register Figure 4 shows that the CPU accesses registers 23, 24, 30,
How to access 31a and 31b,
Indicates whether to set VDP to a predetermined functional state. In this case, the signal CM is "0".

When an instruction field is received from the CPU, the signal AL selects the instruction field from select register 2.
5 and from there the corresponding information is sent to decoder 2.
7, the output of which drives one or more of the program registers mentioned above.

The following directives are executed as a function of the contents of the address field:

Reading or writing the functional mode of LDRC, STRC-VDP from the instruction register 24.

LDA or LDB; STA or STP - registers 31a, 31b with values used by arithmetic and logic unit 32 to perform computational operations;
To read or write to.

LDST, STST - reading or writing the contents of status registers 30 reflecting different stages and functions of image processing.

LDMSQ, STMSQ - Reading or writing a value into the mask register 23 to determine instructions for modifying the displayed image; RRMSQ, RLMSQ - This signal shifts the position of the mask value to the left or right depending on the mask register. Decide to rotate.

During each of these operations, i.e. during each cycle of the CPU, the instruction field is followed by an adapted data field, while the data is transferred by the decoder 27 to the register driven at the given moment. or, on the other hand, place in this field the data that this register previously had. When a function is performed according to Figure 4, the VDP becomes opaque and the internal bus is No data or address is sent to 5.

C--FIG. 5--Accessing Register Stack 33 to Determine the Part of Memory 5 to Be Addressed This function of the registers in stack 33 has already been described. In the course of performing this function, only certain registers of this stack are active. These are indicated by stars in Figure 5.

As already mentioned, the instruction field sent by the CPU 1 is sent to the selection register 25, which transfers this field to the decoder 27. The data field immediately after that needs to cross the internal bus 19 in time division, so the decoder
Trigger the DMA circuit 20, which allocates transit time for this operation (signal CM is "0"). The decoder also drives arithmetic and logic unit 32, which remains transparent while recording a data field into one of the registers of stack 33. The device 33 thus achieves an operation F(EA) corresponding to transparency.

Reading a data field into one of the registers of stack 33 (considering transfer to CPU 1) is accomplished under the control of DMA circuit 20.
The contents of the target register are transferred to the data register 22 and placed in a waiting state for transfer to the CPU bus 12.

This VDP configuration allows various instructions to be executed. LPDA, STPA - Read and write the base address of the page being displayed; LDGT, STGT - Read and write the base address of the control memory used for display; LDMT, STMT, LDMTF, STMTF - Start and end of buffer memory. LDPX, STPX, LDPY, STPY - reading and writing of the current values temporarily stored in the pointers PX and/or PY used by the CPU for image processing, D- FIG. 6 - Control of access to addresses in memory 5 as a function of predetermined criteria.
b under the control of the CPU 1. This feature is useful for displaying specific image characteristics (such as a vertical bar of a particular color, a particular shape whose characteristics are included in the CPU, or a particular color that should be displayed on part or all of the screen). The signal CM remains at "0".

For example, if a vertical bar is to be displayed, an address corresponding to a specific distance from the left edge of the image will be given to the page memory 5, and the data will correspond to a specific color. This would place the same data at address locations that differ by 120 (number of bytes per line).

This feature is useful when displaying the same color on part or all of the screen. Referring to FIG. 7, the concept of using this functionality is illustrated in accordance with a particular embodiment of the present invention. This is the concept of "memory plane".

FIG. 7 shows a few bytes of the first line of a memory page contained in RAM 5, which line is presented on the screen as the first line of a frame at a given time.

The rectangle at the top of the diagram is the memory line (screen line) at address 01...06 etc. (hexadecimal number)
represents the first 6 bytes of . This byte also contains color information for the 8 points on the screen; a 1 bit in the byte means, for example, that one color is present, and a 0 means that it is present. Show that you do not.
Then, if you want to display red at all points on that line, the address of that byte will be incremented by 3, and the data field of that byte will be "1".
will be included. In this way, the "memory planes" indicated by the lower rectangles in Figure 7 are conceptually obtained, each plane representing a given color of the image (red, green, blue). . Many variations of such page memory configurations are possible, but they can be advantageously used in accordance with the present invention. The implementation of this function described below will be explained with reference again to FIG.

Arrival of address field (instruction to CPU,
CM=0), the decoder 27 drives the necessary registers according to the contents of this field.

One of the registers driven may be pointer PX or pointer PY. Internal bus 1 under the control of a circuit 20 that controls the time division of bus 19
Read the data field to the address contained in the selected pointer PX or PY on 9,
Writing is performed. The address thus obtained is transferred on bus 19 to register 36, thereby selecting the corresponding location in memory 5. During the same period, arithmetic and logic unit 32 executes the formula F=EA+A or F=EA+B depending on whether it is operating on the contents of register 31a or 31b enabled by decoder 27. The address of the next access is calculated by adding the value A or B to PX or PY according to either of the following:

During a second period, the data for the selected address is transferred by bus 19 to register 22 and loaded into memory through circuit 35, or conversely from RAM 5 through circuit 35 onto bus 19. and loaded into register 22 before being retrieved and read by CPU 1.

This function supports the following commands.

LDPX(A), STPX(A)− Read and write the data field to the memory address contained in the pointer or register PX, and
Transfer A to this register after access (in combination with register 31a).

Similar instruction LDPX(B) regarding register 31b
and STPX(B) are also executed.

E--FIG. 8--Repeated Accesses to Memory Planes The advantages and speed of implementation provided by the present invention will be particularly apparent with respect to the functionality illustrated in FIG. This instruction allows data constants to be loaded into one or more memory planes of page memory with very few execution cycles of CPU1 (CM=0).

During the preceding operation, after the processing of the instruction field by the selection register 25 and the decoder 27,
Subsequent data fields from CPU 1 are loaded into mask register 23. This data field contains multiple iterative loads to perform.

The address field and the following data field, including the address and data to be loaded into this address, are performed by pointer PX or PY, arithmetic and logic unit 32, register 31a or 31b, as described above. All of these are performed under the control of a circuit 20 that controls the internal bus 19 in a time-sharing manner (function
LDPXA ⁿ ).

Without CPU intervention, the internal cycle is repeated n times as described above. n is the preceding CPU
This is the value loaded into register 23 during the cycle.

For each memory access, DMA20 connects the conductor DC
and the register 23 decrements the value n until it becomes zero. The conductor carrying the value n=0 is connected to a decoder 27, whereby the decoder
Line 2 for requesting access to DMA20
Suppress the control signal on 9.

This process allows for very fast loading of memory. The memory surface of 10K bytes is approx.
Requires a load time of 1.5ms, and when sequential loading is used, the load time to each address is
for the same number of bytes before CPU intervention
100ms is required.

F--FIGS. 9, 10, 11a, 11b--Format Transfer or Modification For an understanding of this function, it is useful to refer to FIG. 9, which shows the modification element 34 in detail.
This element includes a logic processing circuit 38 in which it is possible to perform logic functions on two input signals, both in 16-bit form, for example for 16 bits. These functions are, for example, "true" 38a, OR 38b, AND 38c, negative-AND 38d, and "invert" 38e.

This selection is made by control line 39,
It produces the output of decoder 27 (9th
figure).

A first input 40a of the processing circuit is connected to a mask register 23, which provides information to this circuit regarding the eight images to be displayed on the screen. This information is (signal in Figure 11b)
MSQ or) for example from a format memory, character generator or other similar signal source forming part of the memory 5.

The input 40b of the processing circuit is connected to a storage register or read memory 41, into which the contents of the two bytes of the page memory (memory 5) to be modified are loaded. It is pointed out again that each bit of this page memory controls which point is to be displayed on the screen, and that the memory is preferably organized in the form of a "memory plane" as described above.

The individual outputs of the logic processing circuit 38 in 16-bit format are coupled to a multiplexer 42 whose multiplexed output is coupled to the internal bus 19.

The implementation of this modification function will now be described for a specific example. An example of this would be the letter A above the information appearing here, as shown in Figure 11a.
This includes superimposing and displaying the images at a given position on the display image. Here, only the overlapping display of the upper horizontal bars will be explained. This operation, as described herein, can be performed on all of the image regions in question. It should be noted that this modification can be performed in the page memory portion of the memory 5 for data stored therein.

For simplicity, we will explain eight points on the screen, and the color is rectangle C1 in Figure 11a,
It is defined by 3 bytes 01, 02, 03, and 01, 02, 03 are respectively surface R,
They belong to G and B, and their combination creates 8 points on the screen having the following colors. Magenta cyan, red, white, blue, green,
black. The upper bar of letter A is rectangle 04 in Figure 11a.
It is assumed that the 8 points of C1 are superimposed and displayed in red.

When an instruction field is applied from the CPU on bus 12, register 25 is driven by the signal AL on line 26, and decoder 27 drives the registers necessary to perform this operation and outputs it on internal bus 19. Circuit for assigning time intervals
Drive DMA20 (CM=0). precede
During a CPU cycle, the address of byte 01 of the red R plane (FIG. 11b) for the image point to be modified is introduced into register PX.

The information in byte 01, which is 1011.0000, is read into memory and passed on the internal bus 19 to the correction circuit 34.
is transferred to the register 40 (FIG. 9).

The data field following the address or instruction field in question is sent to mask register 23 (bytes 04-0011.1100).
The logic function OR is selected by the control field through register 25 and decoder 27, the signal crosses line 39, and logic processing circuit 38 performs a logic operation on bytes 01 and 04 bit by bit.
Perform OR and result in byte 05-1011.1100
is obtained. This result is written back to address PY on the register stack. All this takes place under the control of circuit DMA20.

After that, the information on the memory surfaces green G and blue B is processed in the same way, but the signals ML and MSQ are AND
The operations are applied, resulting in bytes 06 and 07, respectively.

After this, while the combination of bytes 05 and 07 is displayed on the screen, the 11a
Image points are found whose midpoints are all red, as shown in rectangle C2 in Figure 11b.

Of course, during operations on memory planes R, G, B, CPU 1 performs modification operations on the addresses contained in pointer PY. This modification includes instruction and data fields.
Executed by CPU cycles. The data field contains the difference between the original PY address and the new address PY. Adding this difference to the previous address PY is performed by register 31a or 31b and arithmetic and logic unit 32, as described with respect to FIG.

After processing the bytes in the three memory planes R, G, B corresponding to image point C1 (which has become C2), the system performs the same process on the eight image points located below image point C1. This can be done for groups, and subsequently the sum of the points of the letter A can be superimposed on the displayed points. (Note that here, "image point" means one point drawn from the three guns R, G, and B of the image tube.) One registers the number of repeated executions, If there is a double mask register 23, the other registering the 16 bits of the figure to be added to or superimposed on the image, then the process described so far is repeated n times, as described with respect to FIG. be able to.

Furthermore, by using the function "inversion" 37e of the logic processing circuit 38 in FIG. 9, it is easy to invert the colors of the image.

According to the above description, the present invention has the advantage that all of the image processing functions in the VDP itself can actually be performed using only the instructions provided to the CPU by the program. ing. The CPU can thus be freed of most of its functions and can be assigned to other tasks while performing its functions. Furthermore, the relatively long CPU cycles allow considerable time to be spent on processing image information, allowing display to occur very quickly, in fact instantaneously to the screen viewer. .

Finally, programming the magazines to be displayed can be done fairly easily.

In FIG. 12, CPU 1 and VDP 4 are connected to data bus 12A and address bus 12B, and information from the CPU is stored using data drive signal EN, read/write signal R/ It is controlled by CPU 1 using W. According to the invention, the CPU can also generate an assignment signal CM for a certain address on bus 12B. This signal is either "1" or "0"
Depending on the situation, it is interpreted whether these addresses are the addresses themselves of the memory 5 or instructions to the VDP 4. In other words, when the signal CM is "1", the memory RAM5 is as if the CPU1
as if it were connected directly to and controlled by the normal signals EN and R/W. On the other hand, when the signal CM is "0", the addresses loaded by these normal signals are interpreted as instructions for the VDP4.

FIG. 13 shows a timing diagram of this memory cycle. Data 15 and address 14 passing through buses 12A and 12B are connected to signals R/17 and 18, respectively.
Controlled by W and EN.

The information represented by address 14 coming from the CPU can be used in two ways.

1 the information represents the address itself, through which the data associated with the address in question passes through the VDP 4 and is stored in the memory 5 and stored in the address transmitted via the bus 12B and the address register 36 (if the CM is 1” (see Figure 3).

2 Information may represent specific display function instructions by which the VDP is configured for a particular configuration for that function. The data associated with this address is then processed according to the corresponding function (if CM is "0").

Regarding the above description, the following sections are further disclosed.

(1) A device for visualizing on a video screen 6 in graphical mode, point by point in a field or frame from a page memory containing all the video information to be displayed at a given time on the screen. a video display processor 4 connected to a random access memory including said page memory and a display controller 37 for converting information about the video formed from said memory 5 into control signals for a video screen 6; the central processing unit 11 is connected to the video display processor 4 by a single bus 12 transmitting address fields 14 and data fields 15 in a time-sharing manner; It further includes a control and interpretation circuit 27 capable of interpreting the address field as its own address field or as a control field for a video display processor in response to an assignment signal CM issued by said central processing unit. The above-mentioned visualization device is characterized in that:

(2) The visualization device according to item 1, wherein the control field determines a compositing function for images to be displayed on the video screen 6.

(3) In the visualization device according to item 2, the control and interpretation circuit 27 includes a decoder having a plurality of drive outputs 28 for transmitting function signals for driving the image synthesis function in the video display processor 4. This decoder further includes the above allocation signal CM
The above-mentioned visualization device is connected to the central processing unit 1 by a selection conductor 26 that transmits.

(4) The visualization device according to item 3, wherein the decoder is driven by an address latch signal AL applied from the central processing unit 1 to a single bus 12 connecting the central processing unit 1 to the video display processor 4. The above-mentioned visualization device is characterized in that the visualization device is connected by a register 15.

(5) In the visualization device according to any one of paragraphs 1 to 4, the video display processor 4 connects the central processing unit 1 to the memory 5 bidirectionally through the video display processor 4.
and the transmission of data and addresses on this bus is controlled in a time-sharing manner.

(6) The visualization device according to item 5, wherein the video display processor 4 includes a time division control circuit 20 that controls circulation of information on the internal transfer bus 19.

(7) The visualization device according to paragraph 6, in which the time division control circuit 20 is connected to the control and interpretation circuit 27 so that the information is transmitted on the internal transfer bus 19 in a time division manner. The above-mentioned visualization device is characterized in that it is capable of allocating cycle time to the internal transfer bus 19.

(8) The visualization device according to any one of paragraphs 1 to 7, wherein the video display processor includes a stack of registers 33 containing an address defining an area of the memory, The arithmetic and logic unit 32 is assigned to perform predetermined functions for these addresses, and also performs predetermined calculations and video display processors for modifying the composition of the image to be displayed. Display interface 3 providing communication between 4 and video screen 6
7, the register stack 33 and the arithmetic and logic unit 32 are connected to the internal transfer bus 19 and the control and interpretation circuit 27 to be interpreted as instructions and sent to the central processing unit 1.
The above-mentioned visualization device is adapted to be driven by an address field given from the above.

(9) The visualization device according to item 8, wherein the video display processor includes a control register 24, a status register 30, and at least one buffer register 3.
1a, 31b, all of which are connected to a single busbar 12 of the central processing unit 1;
Buffer registers 31a, 31b are coupled to an arithmetic and logic unit 32 which allows the latter to perform logical operations on the current address and the preceding address stored in a register (PX or PY) of register stack 33. The above-mentioned visualization device is characterized in that:

(10) The visualization device according to paragraph 9, in which the register stack 33, the arithmetic and logic unit 32, the control register 24, the status register 30, and the buffer registers 31a and 31b are connected to the drive output of the control and interpretation circuit 27. The above-mentioned visualization device is characterized in that:

(11) The visualization device according to any one of paragraphs 3 to 10, wherein the video display processor 4 further comprises:
The CPU 1 includes a mask register 23 connected to the single bus bar 12 of the central processing unit 1, in which a number corresponding to the repetition of the image compositing mechanism to be displayed by the video display processor 4 is stored; A visualization device as described above, characterized in that it is further coupled to a control and interpretation circuit 27 and, if appropriate, driven by the interpretation circuit.

(12) The visualization device according to any one of paragraphs 6 to 10, wherein the video display processor 4 further comprises:
It includes a mask register 23 connected to the single bus bar 12 of the central processing unit 1, in which a number corresponding to the repetition of the image compositing function to be displayed by the video display processor 4 is stored; is further connected to a control and interpretation circuit 27 and, if appropriate, driven by the interpretation circuit, and said mask register 23 is connected to said time-sharing control circuit 20.
, the control circuit 20 is adapted to subtract the number contained in the register on each completion of a repeat cycle or on each completion of a cycle of a similar synthesis function;
Furthermore, said mask register 23 is connected to said control and interpretation circuit 27 to output the output 28 of said interpretation circuit.
The above-mentioned visualization device is characterized in that the drive signal is canceled when the contents of the mask register 23 reach zero.

(13) In the visualization device according to any one of paragraphs 3 to 11, the video display processor 4 uses image data already stored in the memory;
Means 3 for modifying the composition of images to be displayed by logical combination with image modification data given from the central processing unit 1;
4. The visualization device described above includes:

(14) The visualization device according to item 13, wherein the correction means 34 is connected to a first
an input 40a of the video display processor 4 and a second input connected to the internal bus 19 of the video display processor 4, the output of which is also connected to the bus; having a logic function selection input 39 connected to said control and interpretation circuit 27, adapted to perform a logic function on the addresses provided on the two inputs while performing the modification function; The above-mentioned visualization device is characterized by:

(15) A video display processor 4 for the system for visualization by field or frame scanning on a video screen 6 in graphical mode, a central processing unit connected to this processor by an address bus 12b and a data bus 12a. Under the control of the device 1, a screen image is displayed line by line or point by point from data stored in the random access memory 5.
is an interpretation in which the content of the address bus 12b is interpreted as an address itself for the random access memory 5 or an instruction for executing an image compositing function to be executed by the video display processor 4. Means 26,
27. A display processor comprising: 27.

(16) The video display processor according to item 15, wherein the command determines a function for compositing images to be displayed on the video screen 6.

(17) The video display processor according to item 16, wherein the interpretation means 26, 27 include a decoder 27 including a plurality of drive outputs 28 for transmitting signals for driving an image synthesis function in the processor. The decoder 27 is further connected to the central processing unit by a mode control conductor 26, and an address assignment signal CM from the central processing unit 1 is transmitted on the conductor. The processor is characterized in that the address specifies either an address function for the memory 5 itself or a control function for the video display processor 4.

(18) A video display processor according to paragraph 17, which includes an internal transfer bus 19 that bidirectionally connects the central processing unit 1 to the random access memory 5 through the video display processor. The circulation of data from the central processing unit and addresses processed within the processor for execution of the synthesis function is controlled in a time-division manner on this internal transfer bus 19. A processor characterized by:

(19) The video display processor according to item 18, characterized in that it includes a time division control circuit 20 that controls time division on the internal bus.

(20) In the video display processor according to paragraph 19, when the time division control circuit 20 is connected to the interpretation means 26, 27 which circulates information on the internal transfer bus 19 in a time division manner, the internal A processor characterized in that a cycle time can be assigned to a transfer bus 19.

(21) The video display processor according to any one of paragraphs 15 to 19, which has a register stack 33 for containing an address that limits the area of the memory allocated to the predetermined function. , an arithmetic and logic unit 32 for performing predetermined calculations for modifying the composition of the images to be displayed for these addresses, establishing communication between the video display processor 4 and the video screen 6; including a display interface 37 for the register stack 3.
3 and said arithmetic and logic unit 32 are connected to said internal transfer bus 19 and said interpretation means 27 so as to be driven by addresses given by said central processing unit 1 and interpreted as instructions. Characteristic processor.

(22) A processor according to paragraph 21, which includes a control register 24, a status register 30, and at least one buffer register 31a, 31b, all of which are connected to the data display processor 4 to the central processing unit 1. Being connected to the bus bar 12a and the buffer register 31
a, 31b are further connected to the arithmetic and logic unit 32 which stores the current address and the register PX or
A processor characterized by being able to perform logical operations on preceding addresses stored in PY.

(23) The video display processor of paragraph 22, comprising a register stack 33, an arithmetic and logic unit 32,
A processor characterized in that a control register 24, a status register 30, and buffer registers 31a and 31b are all connected to a drive output 28 of the decoder 27.

(24) The video display processor according to any one of paragraphs 17 to 23, wherein the data bus 12a is further connected to the central processing unit 1.
It includes a mask register 23 connected to the decoder 27, which register is adapted to store a number corresponding to the number of repetitions of the image synthesis function to be performed by the video display processor 4, and the mask register 23 is further connected to the decoder 27. , a processor characterized in that it can be driven by a decoder if appropriate.

(25) The video display processor according to any one of paragraphs 5 to 9, wherein the data bus 12a is further connected to the central processing unit 1.
It includes a mask register 23 connected to the decoder 27, which register is adapted to store a number corresponding to the number of repetitions of the image synthesis function to be performed by the video display processor 4, and the mask register 23 is further connected to the decoder 27. , adapted to be driven by a decoder, if appropriate, such that said mask register subtracts the number contained in said register on each execution cycle of an iteration or other similar composition function. and the mask register 23 is further connected to the decoder 27 to suppress the drive signal on the decoder output 28 when the contents of the register reach zero. A processor characterized by:

(26) The video display processor according to any one of paragraphs 17 to 25, which combines and corrects the image to be displayed with the image data already stored in the memory 5 and the central processing unit 1. A processor characterized in that it comprises means 34 adapted to perform by a logical combination of modified image data provided by.

(27) The video display processor according to paragraph 26, wherein the modifying means 34 includes a first input 40a connecting them to the central processing unit 1, a second input connecting them to the internal bus 19, and The output of the processor is also connected to the busbar, and the
coupled to said decoder 27 and characterized in that it includes a logic function selection input 39 for performing a logic function on the binary values applied to its two inputs in the course of performing a modification function. processor.

[Brief explanation of the drawing]

FIG. 1 is a highly simplified diagram of a visualization system according to the invention. FIG. 2 is a time multiplexed signal diagram of data fields and address fields circulating on a time division bus. FIG. 3 is a simplified diagram of a video display processor used in the system of the present invention. 4 to 6 show a system similar to that of FIG. 3, and are diagrams showing other functional configurations of the display processor. FIG. 7 is a diagram illustrating the organization of the page memory of the visualization system into "memory planes". FIG. 8 is a diagram showing another configuration of the display processor. 9th
The figure is a schematic diagram of image modification elements used in a display processor. FIG. 10 is a diagram showing another configuration of this processor. Figures 11A and 11
FIG. B is a diagram showing the functions performed by the display processor having the configuration of FIG. 10. FIG. 12 is a highly simplified diagram of a dual busbar visualization system according to the present invention. Figure 13 shows the 12th
FIG. 3 is a signal diagram of a data field and an address field in the figure. (Symbol), 1...Central processing unit, 3...Keyboard, 4...VDP processor, 5...Random access memory, 6...Display screen, 7...
Address bus, 8... Data bus, 9... Applicable circuit, 12... Common bus, 13... Control line, 1
9... Internal bus, 20... Direct memory access device, 22... Data register, 23... Mask register, 24... Control register, 25... Transfer register, 27... Decoder, 30... Status register, 32 ... Arithmetic and logic unit, 33 ... Register staff, 34 ... Modification register, 35 ... Data register, 36 ... Address register, 37
...Output interface, 38...Logic processing circuit, 39...Control line, 41...Storage register, 42...Multiplexer.

Claims (1)

[Scope of Claims] 1. A device for displaying a graphic visible image on a video screen, comprising: a video display unit including a video screen for displaying the graphic visible image; and a device connected to the video display unit. , a display control unit for receiving a display control signal and controlling the video display unit according to the received display control signal; and a page storing therein video information defining the graphical visible image to be displayed. a central processing unit to which is connected a memory, a single bus on which address fields and data fields are transmitted in a time-sharing manner, and a control line on which assignment signals provided by the central processing unit are transmitted; said display control unit; a video display processor connected to the page memory and retrieving video information stored in the page memory and converting the retrieved video information into corresponding display control signals for supply to the display control unit; the central processing unit is connected to the video display processor by the single bus over which the address field and the data field are transmitted in a time-sharing manner; 2. A video display device comprising: a control and interpretation circuit for interpreting data on said single bus as an address field or as a control field for said video display processor in response to said assignment signal generated by said video display processor. 2. The display device of claim 1, wherein the control and interpretation circuit of the video display processor includes a decoder, the decoder receiving on the single bus and responsive to the assignment signal. A video display device comprising a plurality of drive outputs for transmitting function signals for driving said video display processor to perform data processing functions on data fields interpreted as control fields. 3. A device for displaying a graphic visible image on a video screen, comprising: a video display unit including a video screen for displaying the graphic visible image; and a device connected to the video display unit and receiving a display control signal. , a display control unit for controlling the video display unit according to the received display control signal; a page memory storing therein video information defining the graphical visual image to be displayed; and a central processing unit. , an address bus on which the address field is transmitted, a data bus on which the data field is transmitted,
A control line through which an allocation signal is transmitted is connected to the display control unit and the page memory, and is used to call up video information stored in the page memory and supply the called out video information to the display control unit. a video display processor for converting display control signals into corresponding display control signals for the display, the central processing unit is connected to the video display processor by the address bus, the data bus, and the control line; interpreting the data as an address field or as a control field to control the function of the video display processor in response to the assignment signal on the control line;
the video display processor includes control and interpretation circuitry for driving the video display processor to perform data processing functions on data fields received on the data bus; A video display device, characterized in that said functionality corresponds to said data interpreted by said control and interpretation circuit as a control field in response to a signal.