JPH0463572B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a timing circuit, and particularly to a timing circuit that can switch and select timing times.

(B) Prior Art Generally, when a timing circuit is constructed using an IC or the like, a CR time constant circuit is used as a circuit for determining timing. In this type of timing circuit, when switching to a different timing, the time constant CR is switched, but conventionally, multiple resistors with different resistance values are connected in parallel to a capacitor, and only one of the resistors is made conductive to set the time constant. change or
Multiple sets of CR circuits with different time constants are provided, and these are switched using the same number of analog switches and comparators.

(c) Problems to be Solved by the Invention However, in the method of switching the resistance, the time constant is determined only by the resistance value, so adjusting the resistance value is troublesome, and the method using multiple sets of analog switches and comparators The problem was that the circuit became complicated and the number of elements increased.

The present invention has been made by focusing on the above-mentioned problems, and provides a timing circuit which eliminates the drawbacks of the above-mentioned conventional circuits, has a timing time switching function, is easy to adjust, and has a simple configuration. The purpose is to

(d) Means and operation for solving the problem The timing circuit of the present invention has resistors Ra,
Consisting of Rb,... and capacitors Ca, Cb,..., resistance
One end of Ra, Rb,... is connected to the power supply Vcc, the other end is connected to individual terminals P1, P2,..., and one end of the capacitor Ca, Cb,... is connected to the terminal P1, P2,...
A plurality of charging circuits 1, 2, .
are provided for each of the charging circuits 1, 2, . . . , and each collector is connected to the terminal P1, P2, .
are connected to each other, the emitter is connected to ground,
A plurality of discharging transistors Q that discharge the charge of the charging circuits 1, 2, . . . when an input pulse is applied to the base and are turned on in response to the input pulse.
1, Q2, ... and each of the charging circuits 1, 2, ..., each base is individually connected to the terminal P1, P2, ..., and receives and outputs the charging voltage Buffer transistors Q3, Q4, ..., the only output terminal to which the outputs of these buffer transistors Q3, Q4, ... are commonly connected, and a comparison circuit 3 that compares the output of this only output terminal with a reference voltage. , the collectors of each of them are connected to the bases of the corresponding discharging transistors Q1, Q2, . Charging circuit 1,
2, ... and stops the functions of each of the unselected discharging transistors and buffer transistors in response to the selection signal indicating non-selection in order to input it to the comparison circuit 3. It is composed of a plurality of selection transistors Q5, Q6, . . .

In this timing circuit, when a selection signal is applied to one of the plurality of selection transistors, for example transistor Q ₅ , and a non-selection signal is applied to the other selection transistor, only transistor Q ₅ is turned off and the others are turned off. The selection transistor is turned on,
The bases of other discharge transistors become grounded, and their operations are inhibited. On the other hand, since the selection transistor _Q5 is OFF, the discharging transistor Q1 is turned ON when the input signal is input, and the charge in the capacitor Ca of the charging circuit 1 is instantly discharged through the discharging transistor Q1, and then the resistor Ra The capacitor Ca is charged with the time constant of the capacitor Ca, and the potential of the terminal P1 increases. Eventually, the potential reaches the reference voltage and the comparison circuit outputs. The output from this comparator circuit becomes a timing signal after the input signal is input, with a time interval corresponding to the time constant of the charging circuit.

(E) Examples The present invention will be explained in more detail below with reference to Examples. The drawing is a connection diagram of a timing circuit showing one embodiment of the present invention. In the drawing, 1
2 is a first charging circuit consisting of a resistor Ra and a capacitor Ca, and 2 is a second charging circuit consisting of a resistor Rb and a capacitor Cb. A resistor Ra of the first charging circuit 1 is connected to a power supply Vcc and a terminal P1 of the IC, and is connected to a capacitor Ca between the terminal P1 and ground. Similarly, the resistor Rb of the second charging circuit 2 is
A capacitor Cb is connected between Vcc and terminal P2, and between terminal P2 and ground.

One end of the resistor Ra of the first charging circuit 1, that is, between terminal P1 and the ground, and the resistor Rb of the second charging circuit 2
, that is, between terminal P2 and ground, respectively.
NPN type transistors Q1 and Q2 are connected. The transistors Q1 and Q2 are provided to discharge the charges of the first and second charging circuits, respectively.

Q3 and Q4 are emitter-follow-connected buffer transistors, and the transistors Q1 and
The collector of Q2 is connected to transistors Q3 and Q, respectively.
4, and further connected to the base of transistor Q
The emitters of Q3 and Q4 are commonly connected to the (+) input terminal of the comparator circuit 3. Note that the buffer transistors Q3 and Q4 are of the pnp type.

The comparator circuit 3 receives the reference voltage VB at the (-) input terminal, and the voltage input to the (+) input terminal is the reference voltage.
When VB is reached, a timing signal is output from the output terminal 4 to a logic circuit (not shown).

A discharge pulse DP is input to the bases of transistors Q1 and Q2 for the discharge circuit via resistors R1 and R2, and a voltage is connected between the bases of these transistors Q1 and Q2 and ground, respectively.
NPN type transistors Q5 and Q6 are connected. At the bases of these transistors Q5 and Q6,
Selection signals for selecting the first charging circuit 1 and the second charging circuit 2, respectively, are resistors R3 and R4.
It is now input via . When selecting the first charging circuit 1, the selection signal A is inputted as low and high, and conversely, when selecting the charging circuit 2, it is inputted as high and low. .

Next, the operation of the embodiment circuit configured as described above will be explained.

As an example, a case where the first charging circuit 1 is selected will be described. In this case, the signal is input as low and the signal as high. In addition, capacitors Ca and Cb of charging circuits 1 and 2 are connected to respective charging circuits 1 and 2.
It is charged with a time constant of 2.

Since the signal is high, transistor Q6 is on, so the base of transistor Q2 is low, transistor Q2 remains off, and terminal P2 is held at a potential of approximately Vcc. Therefore, the base of buffer transistor Q4 is in an open state, and buffer transistor Q4 is cut off.

On the other hand, since the signal is low, transistor Q5 is off. Therefore, when the discharge pulse DP is input to the bases of transistors Q1 and Q2, transistor Q1 turns on, and the charge stored in the capacitor Ca of the first charging circuit is transferred to the transistor Q
Discharge through 1. However, as mentioned above, the base of transistor Q2 is forcibly held low, so even if the discharge pulse DP is input, transistor Q2 remains off, the charge in capacitor Cb is not discharged, and terminal P2 remains at the potential of Vcc.

When the discharge pulse DP is removed, the transistor Q1 turns off and the capacitor of the first charging circuit 1
Charging of Ca starts again, and the potential of terminal P1 increases. The potential of this terminal P1 is input to the comparator circuit 3 through the buffer transistor Q3. As charging progresses, the potential of the terminal P1 rises, and when the voltage input to the (+) input terminal of the comparator circuit 3 reaches the reference voltage, the comparator circuit 3 outputs a timing signal at that point. The timing at which this timing signal is output is when the discharge pulse DP is input.
After the capacitor Ca is discharged, the first charging circuit 1
when a time that depends on the time constant of
A timing signal corresponding to the time constant of the first charging circuit 1 can be obtained from the output terminal 4.

If it is desired to obtain a timing signal corresponding to the time constant of the second charging circuit 2, the signal may be set to high and the signal may be set to low. Operation is transistors Q1 and Q
2, transistor Q3, Q4, transistor Q
By reversing Q5 and Q6, it is possible to think in exactly the same way as when selecting the first charging circuit.

In the above embodiment, switching between two timings was explained as an example, but by adding a discharging circuit, a buffer transistor, and a selection circuit each time a charging circuit, that is, a time constant circuit, is added, multiple timings can be changed. switching is possible.

(f) Effects of the Invention According to the timing circuit of the present invention, the buffer transistor can also be used as a switching means for switching between a plurality of charging circuits, and can also be used as a selection circuit for stopping the function of a transistor for a discharging circuit. Since we only need to provide a transistor of
Compared to the case where a conventional analog switch is provided, the circuit configuration is simpler and costs can be reduced. Furthermore, since each charging circuit is provided completely independently, the degree of freedom in timing setting is increased and adjustment can be simplified compared to the conventional system in which only the resistors are switched.

Furthermore, one charging circuit can be selected from a plurality of charging circuits using the corresponding discharging transistor, buffer transistor, and selection transistor, and many timing signals with different times can be output by switching.

[Brief explanation of drawings]

The drawing is a connection diagram of a timing circuit showing an embodiment of the present invention. 1, 2...Charging circuit, 3...Comparison circuit, Q1,
Q2...transistor (discharge circuit), Q3, Q4
...Buffer transistor, Q5, Q6...Transistor (selection circuit), P1, P2...Terminal,
Ra, Rb...resistance, Ca, Cb...capacitor.

Claims (1)

[Claims] 1. Each of resistors Ra, Rb, ... and capacitors Ca,
Cb,..., and one end of the resistor Ra, Rb,... is the power supply.
Connected to Vcc and the other end is a separate terminal P1, P2,...
a plurality of charging circuits 1, 2, . . . each having a different time constant, the capacitors Ca, Cb, . . . being connected to the terminals P1, P2, . A charging circuit is provided for each of the charging circuits 1, 2, . . . , each collector is connected to the terminal P1, P2, . a plurality of discharging transistors Q1, which discharge the charge of the charging circuits 1, 2, . . . when turned on;
Q2, ... and each of the charging circuits 1, 2, ... are provided, and each base is individually connected to the terminal P.
1, P2, . . . and receive the charging voltage and output the buffer transistors Q3, Q4, respectively.
..., the only output terminal to which the outputs of these buffer transistors are commonly connected, a comparator circuit 3 that compares the output of this only output terminal with a reference voltage, and the discharge transistor Q1 whose collector corresponds to each one. , Q2, ..., the emitter is connected to ground, and the base is connected to input a selection signal indicating selection or non-selection,
In order to select the charging voltage of one of the charging circuits 1, 2, . . . and input it to the comparison circuit 3, the unselected discharge transistor and buffer transistor are Multiple selection transistors Q that stop each function
A timing circuit consisting of 5, Q6, and so on.