JPH0213489B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse generation circuit, and more particularly to a CR pulse generation circuit that uses a resistor and a capacitor to generate a pulse signal having a predetermined pulse width in response to a trigger pulse.

In the CR pulse generation circuit, a pulse signal is generated by discharging a capacitor by applying a trigger pulse, starting charging the capacitor via a resistor by stopping the trigger pulse, and comparing the charging voltage with a desired reference voltage. It is occurring.

When the CR pulse generation circuit is used as a timing circuit for a sequence circuit that determines the processing order and time allocation in a digital circuit or pulse circuit, it generates not only one pulse signal but multiple pulse signals. required to occur. In such a case, a plurality of pulse signals can be generated by preparing a plurality of reference voltages and comparing the charging voltage of the capacitor with each reference voltage. Here, the rising edge, falling edge, or pulse width of each of the plurality of generated pulse signals needs to be determined with high precision in order to determine the processing order and time allocation. On the other hand, the capacitor is discharged by applying a trigger pulse, and the discharge voltage is also compared with each reference voltage, so the inversion edge and pulse width of each pulse signal may deviate from the intended ones. There is.

Therefore, an object of the present invention is to provide a pulse generation circuit that generates a plurality of pulse signals in response to a trigger pulse using a CR time constant circuit, which substantially disables the pulse generation operation during the application period of the trigger pulse. It is an object of the present invention to provide a pulse generation circuit capable of generating a plurality of pulse signals having desired inversion edges and pulse widths.

The pulse generating circuit according to the present invention will be explained with reference to the numbers shown in FIG. 1 and FIG. A connected capacitor 3, a resistor 2 connected between the circuit node and the power supply point V _S , a semiconductor switch 1 connected in parallel with the capacitor and conducting to discharge the capacitor in response to a trigger pulse, and a common point with the power supply point. A plurality of voltage drop means 31 to 34 are connected in series between the two connection points to the first and second voltage drop means.
a reference voltage generation circuit that generates reference voltages V _A and V _C ;
a first comparing the voltage at the circuit node with a first reference voltage;
a comparator 5, a second comparator 10 for comparing the voltage at a circuit node with a second reference voltage, provided between the output terminal of the first comparator and a common point and conductive in response to a trigger pulse; A first clamp transistor 7 clamps the output terminal to the potential of the common point, and a first clamp transistor 7 provided between the output terminal of the second comparator and the common point and conducts in response to a trigger pulse to connect the output terminal to the common point. It is provided with a second clamp transistor 13b that clamps the voltage to the potential of .

According to this configuration, the first and second clamp transistors are connected to the first clamp transistor during the application period of the trigger pulse.
Since the output terminals of the second comparator and the second comparator are clamped to the common point potential, the output of each comparator is prevented from reaching the power point potential during the same period. That is, the pulse generation operation during the trigger pulse application period is invalidated. Moreover, since the output of each comparator is individually controlled by the corresponding clamp transistor, the first and second reference voltages can be obtained from a common generating circuit.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a time chart of FIG. 1, and FIG. 3 is a circuit diagram of the specific embodiment of FIG.

In FIG. 1, a resistor 2 and a capacitor 3 constitute a time constant circuit, and a trigger pulse φa (pulse width ta) at a in FIG. 2 is input from input terminal a to the base of transistor 1 through resistor 14a. , when the trigger pulse φa is at a high level, the accumulated charge is discharged into the capacitor 3. At the point when the trigger pulse φa ends, the voltage at the intersection point b between the capacitor 3 and the resistor 2 is zero, and starting from this point, the time function output voltage waveform at the intersection point b changes from the power supply From voltage V _S through resistor 2,
The capacitor 3 is charged with electric charge, forming a so-called charging curve. When the voltage at the intersection b is between zero and the voltage V _A of the reference potential 4, the output C of the comparator 5
is at a high level, and the output of inverter 6
The voltage of C' is at a low level as shown in FIG. 2 C'.
The portion where this output C' is at a low level is the first pulse _φ1 .

The pulse width t1 of the first pulse φ ₁ is the trigger pulse width
ta, the time constant determined by resistor 2 and capacitor 3,
It is determined by the voltage V _A of the reference potential 4 of the comparator 5 and the power supply voltage V _S. The pulse width t1 is determined by the following formula t1=RC 1n V _S /(V _S −V _A )+ta・α (1). R is the resistance value of the resistor 2, and C is the capacitance value of the capacitor 3. Here, the second term on the right side of equation (1) overlaps with the trigger pulse φ _a , and by adding the trigger pulse a to the transistor 7 through the resistor 14b, when the trigger pulse φ _a is at a high level, the comparator 5 The output C of is a low level as wired OR logic, so the second term is set to 0.
It can be done. At this time, the pulse width t1 is uniquely determined by the values of the resistor 2 and capacitor 3, the voltage V _A , and the power supply voltage V _S. Similarly, for other pulses such as pulse φ ₂ , by applying trigger pulse φ _a to transistors 13a and 13b via resistors 14C and 14d, the influence of the trigger pulse width can be eliminated. By eliminating the influence of the trigger pulse φ _a on the output pulse width in this way, the ratio of the pulse widths of the respective output pulses can be freely controlled.

Next, in FIG. 1, when the voltage at the intersection b is between the voltage V _B of the reference potential 9 of the comparator 8 and the voltage V _C of the reference potential 11 of the comparator 10,
Output voltage d of comparator 8 and comparator 10
The output voltage e of both NAND
The output voltage f of the circuit 12 is at a low level, as shown in FIG. 2f, and the portion where this output voltage f is at a low level is the second pulse φ ₂ . Here, in FIG. 1, when there is no transistor 13a or 13b, the portion where the output voltage f is at a low level is as follows.
In the interval where the trigger pulse φ _a is at a high level, that is, the dotted line portion in _FIG . This is the part corresponding to the second term ta・α on the right side of 1). Therefore, in FIG. 1, in the portion where the trigger pulse φ _a is at a high level, the transistor 13a lowers the output voltage d of the comparator 8 to a low level, or the output voltage e of the comparator 10 is lowered to a low level by wire-OR operation. . By adding the transistor 13b, it is possible to delete the unnecessary low level portion of the output voltage f of the NAND circuit 12, that is, the dotted line portion in FIG. 2 f, and obtain the necessary second pulse φ ₂ . Can be done. transistor 13
It suffices to use only one of the transistor 13a and the transistor 13b. The beginning of the second pulse _{φ 2} is RC 1n V _S /(V _S
−V _B ), the end of the second pulse is RC 1n V _S /
After (V _S −V _C ), the pulse width t2 is determined by t2=RC 1n(V _S −V _B )/(V _S −V _C ) (2). Further, the interval t ₁₂ between the first pulse and the second pulse is determined by t ₁₂ =RC 1n (V _S −V _A )/(V _S −V _B ). Therefore, t ₁ , t ₂ , and t ₁₂ are all proportional to the time constants of capacitor 3 and resistor 2.

Now, when the third and subsequent pulses φ ₃ are needed,
By adding the circuit portion A that generates the second pulse φ ₂ for the required number of pulses and applying a predetermined voltage to the voltages corresponding to V _B and V _C , the third and subsequent pulses φ ₃ can be obtained. Also, the beginning of the first pulse φ ₁ is
When necessary after the end of the trigger pulse φ _a , a circuit can be created in which the first pulse generating portion is also replaced with a circuit A that generates the second pulse φ ₂ .

The first and second and subsequent pulses obtained above are negative polarity pulses, but the circuit for obtaining positive polarity pulses can be easily constructed by changing the polarity of the transistor, the polarity of the input of the comparator, or exchanging NAND and AND. This is what you get.

Next, a specific circuit of the embodiment shown in FIG. 1 will be explained using FIG. 3.

Trigger pulse φ _a is applied to input terminal a and applied to the base of transistor 1 through resistor 14 a. The resistor 2 and the capacitor 3 form a time constant circuit, and the collector and emitter of the transistor 1 are connected to both ends of the capacitor 3 to control charging and discharging of the capacitor 3. Transistors 15, 16, 19, 20 and resistors 17, 18 form a comparator 5. The base of transistor 15 is connected to the potential at intersection b, and the base of transistor 20 is connected to the voltage divider of resistors 31 to 34. The resulting voltage at the intersection of resistors 33 and 34 is given as voltage V _A. The collector and emitter of the transistor 7 are connected to both ends of the load resistor 18, so that the trigger pulse φ _a applied through the resistor 14b is not output to the resistor 18. The output of this resistor 18 is connected to the transistor 39 and the load resistor 38.
The first pulse φ ₁ is outputted from the input terminal c' via the inverter 6 of FIG.

Transistor 15 and transistors 21, 23,
25 and resistors 22 and 24, the reference voltage V _B at the intersection point b and the voltage divider resistors 32 and 33 is compared and output to the base of the transistor 37. By applying a trigger pulse φ _a to this output from a resistor 14c to the transistor 13a, the influence of the trigger pulse φ _a is prevented. Similarly, a comparator 10 consisting of a transistor 15, transistors 26, 29, 30, and resistors 27, 28 is connected to the voltage at the intersection b and the resistors 31 and 3 of the voltage divider.
The reference voltage V _C at the intersection of the two is compared and outputted to the base of the transistor 36. The trigger pulse φ _a is applied to the base of the transistor 13b through a resistor 14d so that the trigger pulse φ _a does not affect this output. transistors 36 and 3
7 and the resistor 35 form a NAND circuit 12, which outputs the second pulse φ ₂ from the output terminal f.

The comparators 5, 8, and 10 have a Darlington configuration so that the base current does not affect the time constant circuit of the resistor 2 and capacitor 3 and the reference voltage provided by the voltage divider, and is set to several μA. Reference voltage
V _A , V _B , V _C are proportional to the power supply voltage V _S , comparator 5,
Since 8 and 10 also have a differential configuration, even when the power supply voltage, temperature, etc. change, the pulse widths of the first and second pulses φ ₁ and φ ₂ that are obtained are determined by the time constants of resistor 2 and capacitor 3, and the resistor. It is determined by the resistance ratio of 31 to 34. The specific values are: resistor 2 is 100KΩ, capacitor 3 is 0.0068μF, resistor 31 is 4.7KΩ, resistor 32 is
is 4.7KΩ, the resistor 33 is 1KΩ, and the resistor 34 is 3KΩ, the pulse width of the first pulse _φ1 is approximately 160 μsec,
The pulse width of the second pulse φ ₂ is approximately 520 μsec.

In this way, according to this embodiment, a plurality of pulse signals are generated from one set of CR time constant circuits,
Moreover, the output of each comparator 5, 10 is provided with a clamp transistor 7, 1 which is turned on by a trigger pulse.
3b is provided and each output is set to zero potential during the trigger pulse application period (see Figure 2 c, e), undesired pulse output may occur or the inversion edge or pulse width may change. This will be prevented. Furthermore, since each of the reference voltages V _A and V _C is generated from a common circuit, the circuit configuration is also simplified.

FIG. 4 is a block diagram showing another embodiment of the present invention, FIG. 5 is a time chart of FIG. 4, and FIG. 6 is a specific circuit diagram of the embodiment of FIG. 4. . The same parts as in Figures 1-3 have the same reference numerals. In FIG. 4, the polarity of the comparator 8 is relative to the input connected to one end b of the capacitor 3. The RS flip-flop 40 is for eliminating unnecessary pulses shown by the dotted line in FIG. 2f, and has a function corresponding to the transistors 13a and 13b in FIG. 1. Therefore, if only for this purpose, the transistors 41a to 41c shown in FIGS. 4 and 6 are unnecessary. That is, even without these transistors 41a to 41c, when the discharge voltage _Vb of the capacitor reaches the reference voltage _Vc due to the application of the trigger pulse _φa , the output voltage h of the comparator 10 is inverted from a high level to a low level. Since flip-flop 40 maintains its previous state, its output voltage i remains at a low level and output pulse φ ₂ also remains at a high level. The state of the flip-flop 40 is the discharge voltage V _b
is held until it reaches the reference voltage _VB . Therefore, by providing the flip-flop 40, it is possible to eliminate unnecessary pulses during the period in which the discharge voltage _Vb in FIG. 2 is between the reference voltages _VC and _VB . However, when the discharge voltage V _b reaches the reference voltage V _B , unnecessary whisker-like pulses may occur as shown by the dotted line in FIG. 5 . That is, when the discharge voltage _Vb reaches the reference voltage _VB , one output voltage g of the comparator 8 is inverted to a high level, setting the flip-flop 40, and its output i is inverted to a high level. Before this inversion timing, comparator 8
If the other output voltage d is inverted to a low level, the output pulse φ ₂ will remain at a high level, but if the timing of inverting the output voltage d to a low level is delayed, both output voltages d and i will be at a high level. As a result, an unnecessary whisker-like pulse is generated in the output pulse _φ2 . In order to prevent such unnecessary pulses, transistors 41a to 41c are provided. When the trigger pulse φ _a is applied, transistors 41 a to 41 c become conductive during the application period, clamping each output voltage d, g, and i to a low level. Therefore, the whisker-like unnecessary pulses shown in FIG. 5 are reliably prevented. Thus, in this embodiment as well, transistors 7 and 41a or 4
1b disables the pulse generation operation of the comparators 5 and 8 during the trigger pulse application period.

Next, regarding the specific circuit of another embodiment shown in FIG. 6, only the portions that are different from the specific circuit of the embodiment shown in FIG. 3 will be described. The load resistance 42 is the negative output terminal load resistance of the comparator 8 shown in FIG. 4, and the load resistance 43 is the output terminal load resistance of the comparator 10 shown in FIG.
Resistors 44, 47, 48, 50 and transistor 4
5, 49 is the R-S flip-flop 40 in FIG.
, respectively. The resistor 50 is connected to the connection point between the collector of the transistor 49 and the resistor 48.
When connecting the base of transistor 37 directly,
This is to prevent the resistor 48 from applying a self-bias to the transistor 37 and making it constantly conductive. Transistors 41c and 41
Only one c' corresponds to the transistor 41c in FIG. 4. In this way, transistor 7
and 41a (or 41c), the pulse generation operation during the trigger pulse application period is disabled, so a plurality of pulse signals each having the desired inversion edge timing and pulse width can be generated.

The circuit in Figure 6 has a larger number of elements and multiple circuits than the circuit in Figure 3, but it is functionally the same as Figure 3, and when integrated. , are considered equivalent.

As another embodiment of the invention, it is also possible to create two or more pulses that overlap each other by combining logic circuits. What is required is to use a CR time constant circuit and a plurality of comparators, the output of which can be logically synthesized arbitrarily.

As described above, according to the present invention, clamp transistors are provided at the outputs of the first and second comparators, and these are made conductive in response to a trigger pulse to clamp each output to a common point potential. ,
The pulse generation operation during the application period of the same pulse is disabled, making it possible to generate multiple pulse signals each having the desired inversion edge timing and pulse width, and furthermore, it is also possible to generate two reference voltages from a common circuit. becomes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart of voltages at various parts in FIG. 1, FIG. 3 is a circuit connection diagram showing a specific embodiment of FIG. 1, and FIG. This figure is a block diagram of another embodiment of the present invention, FIG. 5 is a time chart of voltages at various parts of FIG. 4, and FIG. 6 is a circuit connection diagram showing a specific embodiment of FIG. 4. V _S ...Power supply voltage, 5, 8, 10...Comparator, 6...Inverter circuit, 12...NAND
Circuit, 4, 9, 11...Reference potential, 40...RS
Flip-flop, 1, 7, 13a, 13b, 1
5, 16, 19, 20, 21, 23, 25, 2
6, 29, 30, 36, 37, 39, 41a, 4
1b, 41c, 41c', 45, 49...transistor, 2, 14a, 14b, 14c, 14d, 1
4e, 14f, 14g, 14g', 17, 18, 2
2, 24, 27, 28, 31, 32, 33, 3
4, 35, 38, 44, 45, 46, 47, 4
8, 50...Resistor, 3...Capacitor.

Claims (1)

[Claims] 1. A capacitor connected between a circuit node and a common point, a resistor connected between the circuit node and a power supply point, and a resistor connected in parallel to the capacitor and turned on in response to a trigger pulse. a semiconductor switch for discharging the capacitor; a plurality of voltage drop means connected in series between the power supply point and the common point; first and second standards from two points of connection between the voltage drop means; a reference voltage generating circuit that generates a voltage; a first comparator that compares the voltage at the circuit node with the first reference voltage; and a first comparator that compares the voltage at the circuit node with the second reference voltage.
a second comparator for comparing the output terminal of the first comparator with a reference voltage, the second comparator being provided between the output terminal of the first comparator and the common point and conducting in response to the trigger pulse; a first clamp transistor that clamps to the potential of the common point; and a first clamp transistor that is provided between the output terminal of the second comparator and the common point and conducts in response to the trigger pulse;
A pulse generation circuit comprising a second clamp transistor that clamps the output terminal of the comparator to the potential of the common point. 2. The first comparator has third and fourth transistors connected in a differential manner, and the second comparator has fifth and sixth transistors connected in a differential manner. , the first reference voltage is supplied to the base of the third transistor via an emitter follower type seventh transistor, and the second reference voltage is supplied to the base of the fifth transistor via an emitter follower type eighth transistor. , and the bases of the fourth and sixth transistors are connected in common and their common connection point is connected to the circuit node via a ninth transistor of the emitter follower type. The pulse generation circuit described in .