JPH0465550B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a vertical channel type insulated gate semiconductor device (hereinafter referred to as an insulated gate semiconductor device) using a semiconductor on a substrate.

[Conventional technology]

Conventionally, when providing a flat solid state display device, a liquid crystal display device is known in which a pair of electrodes are provided in parallel light-transmitting substrates, such as glass or plastic plates, and liquid crystal is injected between the electrodes.

In order to obtain a configuration in which this display section is made up of a plurality of picture elements, arranged in a matrix, and controlled to turn on or off any given picture element by a logic circuit of a decoder and driver provided around the picture element, it is necessary to It was necessary to manufacture insulated gate type semiconductor devices, inverters, resistors, etc. corresponding to picture elements using the same process and structure. In this format, a control signal is given to an insulated gate type semiconductor device provided corresponding to each pixel to turn on or off the corresponding picture element.

In this case, the liquid crystal display or electrochromic display element can be represented by a capacitor (hereinafter referred to as C) as its equivalent circuit.

For example, the insulated gate type semiconductor device and C are arranged in a 2×2
The matrix configuration 40 is shown in Figure 1A.
Shown below.

In FIG. 1A, one address of the matrix 40 constitutes one picture element by one insulated gate type semiconductor device 10 and one C31. These are arranged in rows 51 and 52 and connected to bit lines, and on the other hand, gates are connected to form columns 41 and 42 (words).

Then, for example, 51 and 41 are set as "1", and 5
When 2 and 42 are set to "0", the insulated gate semiconductor device 10 is turned on, and other insulated gate semiconductor devices such as the insulated gate semiconductor device 10' are turned off. Then, only the address 2,1 can be selected and turned on, and the display section electrically equivalently shown as C31 can be selectively turned on.

[Problems with conventional technology]

There were structural problems and manufacturing process problems in realizing the structure shown in FIG. 1A.

Structural problems include leakage between the source and drain, parasitic capacitance, and low operating speed due to long channel length.

Further, the problem in the manufacturing process is the problem of low yield due to the complexity of the manufacturing process.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing process for obtaining an insulated gate type semiconductor device that operates stably at high speed up to high frequencies and is not difficult to manufacture.

[Structure of the invention]

The present invention includes a first semiconductor, an insulating material, and a second semiconductor having the same conductivity type as the first semiconductor, each having a convex side portion on a substrate or a first conductive film on the substrate. a step of forming a third semiconductor constituting a vertical channel forming region adjacent to the side portion; a step of forming an insulator on the surface of the semiconductor; By forming the conductor or semiconductor constituting the gate electrode and performing vertical anisotropic etching on the conductor or semiconductor, the gate electrode can be formed without leaving its upper end above the second semiconductor. The gist of the present invention is a method for manufacturing an insulated gate semiconductor device, which is characterized by comprising a step of forming an electrode.

The present invention relates to a method for manufacturing an insulated gate type semiconductor device that can operate at high speed up to a higher frequency by providing the upper end of a gate electrode without extending above a convex semiconductor.

This invention provides a non-single crystal semiconductor that forms a channel around two sides of such a convex body, and uses this semiconductor to fabricate two insulated gate type semiconductor devices, thereby converting circuit elements such as an inverter into one. The aim is to achieve high integration by providing a stacked structure.

An object of the present invention is to provide a composite semiconductor device in a matrix structure on a substrate using such an insulated gate type semiconductor device, and to provide a liquid crystal display type display device.

The semiconductor used in the present invention, particularly the semiconductor No. 4 constituting the channel forming region, is a non-single crystal semiconductor whose main component is silicon doped with hydrogen or fluorine.

This non-single-crystal semiconductor has a major feature of being easy to manufacture, but has the drawback that its carrier mobility is extremely small compared to that of a single-crystal semiconductor.

In the present invention, the channel length can be determined by the thickness of the insulator material formed on the first semiconductor, and by setting the film thickness of the insulator material to 1 μm or less, the channel length can be determined by the thickness of the insulator material formed on the first semiconductor. , a short channel length can be easily formed, and a cutoff frequency of 10 MHz or more can be provided.

〔Example〕

FIG. 2 shows a vertical cross-sectional view and manufacturing process of a vertical channel type insulated gate type semiconductor device of the present invention. Although this drawing shows an example of manufacturing one insulated gate type semiconductor device, the same applies to the case where a plurality of devices are manufactured on the same substrate.

In FIG. 2A, a first conductive film 2 is provided as a lower electrode and a lead on an insulating substrate 1 made of quartz glass, transparent plastic, or borosilicate glass. In this example, a transparent conductive film containing tin oxide as a main component is formed to a thickness of 0.2 μm. This is subjected to selective etching, and a first non-single crystal semiconductor 3 (hereinafter simply referred to as the first semiconductor) having a P or N type conductivity is formed on the upper surface.
1000 to 3000 Å, second insulator or semi-insulator insulator material 4 of 0.3 to 3 μm, second non-single crystal semiconductor 5 having the same conductivity type as the first semiconductor (hereinafter simply referred to as second semiconductor) A convex body (stack, ie, referred to as S) was provided by stacking the wafers to a thickness of 0.1 to 0.5 μm. This lamination provided a NIN, PIP structure (I is an insulator or a semi-insulator).

Furthermore, TiSi ₂ 6 was laminated as a conductive film on the upper surface to a thickness of 0.2 μm using the PCVD method. This conductive film is made of ITO (indium tin oxide), MoSi ₂ ,
A heat-resistant metal conductive laminate such as TiSi ₂ , WSi ₂ , W, Ti, Mo, etc. can be used.

Further, a silicon oxide film 7 with a thickness of 0.3 to 1 μm was formed by LPCVD (low-pressure vapor phase method), PCVD, or optical CVD. This silicon oxide film functions as an insulating film. In this step, a plasma gas phase reaction between N ₂ O and SiH ₄ was performed at a reaction temperature of 250°C.

Let these N and P be N ⁺ N or P ⁺ P
It was effective to lower the contact resistance between P or N and the electrode by using N ⁺ NINN ⁺ , P ⁺ PIPP ⁺ (I is an insulator or semi-insulator).

In FIG. 2B, the second patterning is performed using a selective etching method to form an insulating film (SiO ₂ ).
7 was removed. Furthermore, this insulating film (SiO ₂ film) 7
Using this as a mask, the conductor 6, second semiconductor 5, insulator material 14, and first semiconductor 3 underneath were removed, and the remaining laminates were formed into approximately the same shape as each other. All of the above steps were performed using the same mask using plasma vapor phase etching, such as HF gas or a mixed gas of CF+0. Note that this etching was performed at a pressure of 1 to 0.5 torr, an RF power of 30 W, and an etching rate of 500 Å/min.

In this way, convex bodies having approximately the same shape were provided.

Here, if the insulator material 14 is a semiconductor, impurities between the first semiconductor 13 and the second semiconductor 15 are likely to leak, and between the first semiconductor 13 and the insulator material 14, the insulator material 14, second semiconductor 1
It becomes difficult to obtain good bonding characteristics between the two.

However, in this embodiment, an insulating material 14 is used to prevent abnormal diffusion of impurities in the first semiconductor 13 and the second semiconductor 15. As a result, the insulation between the source and drain can be improved, and an insulated gate type semiconductor device that does not generate leakage current and has heat resistance can be realized.

Furthermore, the third semiconductor 25 is the first semiconductor 13, the insulator material 14, and
The second insulator 15, the conductor 23, and the insulator 24 were covered and laminated. This third semiconductor 25 is manufactured using a silane glow discharge method (PCVD method, photo CVD method, LT CVD method).
(also referred to as the HOMO CVD method) at temperatures ranging from room temperature to 500°C.

In this example, the PCVD method was used, the deposition temperature was 250℃, the deposition pressure was 0.1torr, the RF input power was 30W,
It was set up under the condition of RF frequency 13.56MHz.
A non-single crystal silicon semiconductor having an amorphous, semi-amorphous or polycrystalline structure was formed.

Examples using an amorphous or semi-amorphous semiconductor will be shown below.

Further, a silicon nitride film 16 is formed on the top and side surfaces of the silicon nitride film 16.
A third semiconductor surface was formed in the same reactor without exposing it to the atmosphere.

Here, a film with a thickness of 300 to 2000 Å was formed by activating silane (disilane may also be used) and ammonia by a mercury excitation method using a photoCVD method.

This insulating film is prepared by immersing it in a nitrogen or ammonia atmosphere at a temperature of 100 to 400°C activated by electromagnetic energy at a frequency of 13.56MHz to 2.45GHz.
It may also be obtained by performing a solid phase gas phase reaction to form silicon nitride.

Alternatively, a method of forming silicon nitride using a PCVD method may be used.

In this way, around the sides of the insulator materials 14, 14, the channel forming regions 9, 9' (see FIG. 2C)
A third semiconductor 25 constituting the third semiconductor 25 and an insulator 16 as a gate insulating film thereon were formed. The third semiconductor, the first semiconductor, and the second semiconductor form a diode junction on their side surfaces.

In FIG. 2B, holes for electrodes are formed in a third patterning step, and then a second conductive film 1 is formed to cover the silicon nitride film 16 on this stacked body.
7 was formed to a thickness of 0.3 to 1 μm.

This conductive film 17 is made of ITO (indium oxide).
Transparent conductive film such as tin) or TiSi ₂ ,
A heat-resistant conductive film such as MoSi ₂ , WSi ₂ , W, Ti, Mo, etc. may be used. Here, a silicon semiconductor doped with a large amount of impurity imparting P or N type was fabricated using the PCVD method. That is, a microcrystalline (grain size 50 to 300 Å) non-single crystal semiconductor with a thickness of 0.5 μm and 1% phosphorus added thereto was fabricated by PCVD.

After that, a resist 18 was formed on this upper surface.

Then, as shown in FIG. 2B, anisotropic etching was performed in the vertical direction using a fourth photolithography technique. This anisotropic etching method involves turning a reactive gas such as CF ₄ , HCl, CF ₄ +O ₂ , HF, etc. into plasma, and then applying this plasma vertically from above the substrate as shown by arrow 28. I went.

As a result of this anisotropic etching, the plane part (thickness 0.5 μm) of the conductor 17 is etched, but the side surface has a thickness of 2 to 3 μm in the vertical direction. It remains unetched as shown at 38'. thus,
It was possible to leave the conductor 17 in areas other than the area where the mask 18 is located. As a result, it was possible to selectively provide gate electrodes only on the side periphery of the laminate. Furthermore, this gate electrode does not exist above the second semiconductor, and as a result, the parasitic capacitance between the second semiconductor and the gate electrode can be made substantially equal to zero.

Thus, Figure 2C was obtained.

A plan view of FIG. 2C viewed from above is shown as FIG. 2D. As shown in this figure, gate electrodes 20, 20' are formed on the entire outer periphery of this laminate.
Unnecessary parts were removed by a photoetching process. The numbers in FIG. 2D correspond to each other.

As shown in FIGS. 2C and 2D, the insulated gate type semiconductor device (1) 10 has two channels indicated by 9 and 9', a source or drain 13, a drain or source 15, and gates 20 and 20'.

The second semiconductor electrode 19 extends into a lead 21 and the first semiconductor lead is provided by 22.

The drawing shows a configuration in which two insulated gate type semiconductor devices are provided as a pair.

This takes advantage of the fact that the insulator material 14 has a resistance of several tens of MΩ between the channels of two insulated gate semiconductor devices, and can substantially eliminate mutual electrical influence.

Such a configuration was not possible with conventional crystalline semiconductors.

The third semiconductor 25 in this embodiment uses a non-single crystal semiconductor containing amorphous silicon. This non-single crystal semiconductor uses hydrogen to neutralize the dangling bonds in it. In addition, since the substrate, semiconductor, and electrode leads are made of different materials, all treatments are carried out at temperatures below 600°C and preferably at temperatures below 300°C to reduce the stress caused by their thermal expansion.
It is useful to keep the temperature below ℃.

Furthermore, the gate electrodes 20 and 20' are connected to the first semiconductor 1.
3. An insulating material 14 and a semiconductor similar to the second semiconductor 15 are provided as electrically floating, and a second gate is used as a control gate with an insulating film placed on the upper surface of the insulating material 14 to form a nonvolatile memory. You can also do it.

In this way, the source or drain is formed by the first semiconductor 13, the third semiconductor 25 having the channel forming regions 9, 9', the drain or source is formed by the second semiconductor 15, and the gate insulator 16 is formed on the side surface of the channel forming region. A stacked insulated gate type semiconductor device 10 with gate electrodes 20, 20' provided on its outer surface could be manufactured. The channel length of this insulated gate semiconductor device is determined by the thickness of the insulator material 14. In this example, it is possible to set it to 0.1-3 micrometers, but here it was set to 0.5 micrometers.

The reason why the channel length is shortened to 0.5 μm is because the mobility of the non-single crystal semiconductor that makes up the channel formation region is only 1/5 to 1/100 of that of a single crystal.
This is to shorten the channel length and improve frequency characteristics as an insulated gate semiconductor device.

Furthermore, when forming the third semiconductor 25, it is effective to add a small amount (0.1 to 10 ppm) of boron impurity to control the threshold voltage as an intrinsic, P or N type semiconductor.

In this example, an N-channel insulated gate type semiconductor device is formed, and its characteristics are V _DD =5V,
We were able to obtain V _GG = 5V and an operating frequency of 15.5MHz.

The insulated gate type semiconductor device of the present invention will be described below regarding a resistor inverter which is a basic element of complex integration.

A longitudinal cross-sectional view of the inverter 60 shown in FIG. 1 is shown in FIG. 3.

In FIGS. 3A and 3B, the numbers of the insulated gate semiconductor devices correspond to those in FIG. 2. Third
In the figure, an insulated gate type semiconductor device 61 on the left side
indicates a driver, and the insulated gate type semiconductor device 64 on the right side indicates a load.

FIG. 3A shows the gate electrode 20 of the load.
FIG. _3B shows a depletion type insulated gate semiconductor device in which the output 62 and the gate electrode 20 are continuous.

The output of the inverter 60 shown in FIG.
This corresponds to 62 in Figure B.

The example shown in FIG. 3 is also characterized in that two insulated gate type semiconductor devices 61, 64 on a substrate are provided in a composite manner in the same semiconductor stack 13, 14, 15 without being separated from each other. The manufacturing process is the same as that shown in FIG.

In the inverter shown in FIG. 3A, the lower electrode is arranged in the front-rear direction of the drawing, and the first square is used to form the lead electrode. Furthermore, a part of it is removed by etching using a second mask to form the same shape as the laminate. At this time, since the lower electrode 12 is covered with the third semiconductor 25,
It has the feature of not colliding with the gate electrode. In addition, in FIG. 3A, the upper electrode is connected to two insulated gate field effect transistors (6
1, 64), it was set as 19, 19'.
In this way, one insulated gate type semiconductor device 64
(load) to the electrode 19, the drain 15, the channel 9, the source 13, the electrode 12, that is, the output 62, and the electrode 1 of the other insulated gate semiconductor device (driver).
2, drain 13, channel 9', source 15,
It was provided as an electrode 66.

In the manner described above, it was possible to integrate two insulated gate type semiconductor devices with one block of first to second semiconductors to form an inverter.

Further, in FIG. 3B, the lower electrode is divided into two parts and arranged in the front and back direction of the drawing. Further, a first mask is used for patterning this lower electrode, and furthermore, when forming a laminate, this electrode is covered with a third semiconductor so as to be electrically insulated from the gate electrodes 20, 20'. Other manufacturing steps are the same as those shown in FIG.

In FIG. 3B, one insulated gate type semiconductor device 64 (load) is composed of a V _DD 65, a lower electrode 12, that is, an output 62, a drain 13, a channel 9, and a source 15.

Another insulated gate type semiconductor device (driver) 61 includes a drain 15, a channel 9', a source 13, an electrode 12, and a V _SS 66.
to the gate electrode 20', and the output 62 was drawn out from the second semiconductor.

Note that the resistor 70 in FIG. 1 can be replaced by using a load in FIGS. 3A and 3B.

As described above, the insulated gate type semiconductor device of this embodiment is of the vertical channel type, and the gate electrode is not provided over the second semiconductor.
It has the great advantage that the parasitic capacitance between the gate electrode of the insulated gate semiconductor device and the second semiconductor can be reduced. Further, since the insulating material 14 is insulating, there is no possibility of shorting even if a large voltage of 30 to 100 V is applied between the first semiconductor and the second semiconductor. Further, regardless of which of the first semiconductor and the second semiconductor acts as a drain, the outside thereof is insulated, so that the most ideal insulated gate type semiconductor device can be constructed.

Further, since the portions in contact with the channels 9 and 9' are also made of the insulating material 14, a structure contributing to improvement of frequency characteristics can be adopted.

In addition, it is sufficient to use the manufactured mask 5 times,
We were able to obtain many features such as not requiring mask precision. In particular, the channel length could be made extremely short to 0.2 to 1 μm.

In this example, an insulated gate type semiconductor device having a breakdown voltage of 20 to 30V could be obtained.

In particular, because the channel length is short, less than 1 μm, we were able to obtain frequency characteristics of more than 10 MHz, which is 50 times that of conventional lateral channel type insulated gate type semiconductor devices using non-single crystal semiconductors. Furthermore, by increasing the insulation properties of the insulator material 14, it was possible to have a withstand voltage of 4 to 50 V and a cut-off frequency of 50 MHz or more.

Also, reverse leakage occurs when the first semiconductor or the second
Si _X C _1-X (0<X<1 e.g. X=0.2)
In addition, by making the insulating material 14 highly insulating, it is possible to prevent impurities of the first semiconductor and the second semiconductor from flowing into the insulating material 14, and the N-I
Even when 10 V was applied, the reverse leakage of the junction or P-I junction could be reduced to 10 nA/cm ² or less.

This reverse leakage was two to three orders of magnitude smaller than the reverse leakage in the case of a single crystal, and was preferable due to active use of the physical properties unique to non-single crystal semiconductors.

Furthermore, when operating at high temperatures, the metal of the electrode is likely to mix into the non-single crystal first _and second semiconductors, resulting in _defects . <X<1 (for example, X=0.2).
As a result, the device was operated at 150°C for 1,000 hours, and no malfunctions were found after evaluating 1,000 devices.
This is because if the first semiconductor or the second semiconductor were formed from only amorphous silicon in close contact with this electrode, it would not be able to withstand 150°C for 10 hours.
This was an extremely high improvement in reliability.

The insulated gate semiconductor device shown in this example is
Because it has a stacked vertical channel structure, it is possible to create multiple insulated gate type semiconductor devices, resistors, and capacitors on a substrate, especially an insulating substrate, without using conventional high-precision photolithography technology. Summer. It became possible to develop it into a liquid crystal display.

As the semiconductor in the present invention, silicon, germanium _, or silicon carbide ( _Si can be used. However, as a semiconductor
-Compound semiconductors such as InP, BP, and GaAs may also be used.

〔Effect of the invention〕

As is clear from the explanation using the above embodiments, in the present invention, a non-single crystal semiconductor constituting a channel forming region is provided on the side surface of a stacked body, and a gate insulating film and a gate electrode are further formed.
Therefore, it was possible to obtain a feature that the interface (insulating film-third semiconductor, insulating film-gate electrode) of the insulated gate type semiconductor device is not contaminated with impurities.

Furthermore, since anisotropic etching is performed, the direction of the plasma is applied parallel to the interface, which has the advantage that new recombination centers are not generated due to damage to the insulator interface caused by the plasma.

Then, the convex semiconductor composed of the first semiconductor, the insulator material, and the second semiconductor is covered with the third semiconductor, thereby realizing a configuration in which the source and drain electrodes and the gate electrode are difficult to shoot. did it.

In particular, the first region constituting the source region and drain region
Since the structure is such that an insulating material is sandwiched between the first semiconductor and the second semiconductor, a remarkable feature can be obtained in that the withstand voltage between the source and drain can be improved.

[Brief explanation of the drawing]

FIG. 1 shows an equivalent circuit of a matrix structure in which an inverter, a resistor, a capacitor using an insulated gate semiconductor device, or an insulated gate semiconductor device and a capacitor are used as picture elements. FIG. 2 is a longitudinal sectional view showing the manufacturing process of a stacked insulated gate type semiconductor device manufactured using the present invention. FIG. 3 shows an inverter structure of a stacked insulated gate semiconductor device manufactured using the present invention.

Claims (1)

[Claims] 1 on the substrate or on the first conductive film on the substrate.
forming a semiconductor, an insulator material, and a second semiconductor of the same conductivity type as the first semiconductor with convex side portions, and forming a vertical channel forming region adjacent to the side portions; a step of forming an insulator on the surface of the semiconductor; a step of forming a conductor or semiconductor constituting a gate electrode adjacent to the insulator; forming the gate electrode without leaving an upper end thereof above the second semiconductor by performing vertical anisotropic etching on the gate electrode. Fabrication method.