JPH0465991B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC testing device for testing an IC that exchanges signals with multiple parts using multi-valued logic signals.

"Prior Art" IC test equipment that tests digital ICs generally has a DC test that measures the voltage-current characteristics and current-voltage characteristics of each input terminal and output terminal, and a function that tests whether the functions operate normally. We are conducting an exam. Therefore, as shown in FIG. 8, an IC testing device for testing a digital IC is equipped with a DC testing device 1 and a functional testing device 2, both of which are switched by a switching circuit 4 provided near the IC under test 3. The structure is such that it can perform both DC tests and functional tests.

In other words, the DC test is based on the current flowing into IC3 when a predetermined voltage is applied to each terminal of IC3 under test.
There is a voltage application current measurement mode that measures the current flowing out of IC3 and determines whether this current value is within a specified range. There is a current applied voltage measurement mode in which the voltage generated at the terminal is measured and it is determined whether or not the voltage value is a specified voltage value.

This DC test verifies that the input/output terminals of IC3 are normal, and if it passes, then a functional test is performed.

For the functional test, the switching circuit 4 is switched to the functional testing device 2, various pattern signals are applied from the functional testing device 2 to the input of the IC under test 3, and the pattern signals are applied.
At the same time, the output of the IC under test 3 is compared with the expected value pattern output from the functional test device 2 in the logic comparator 5, and a match or mismatch is detected. When a mismatch is detected, it is determined to be defective. to display defects. Reference numeral 7 indicates a controller that sequence-controls the entire operation.

"Problems to be Solved by the Invention" Conventional digital ICs mainly operate using binary logic signals. Therefore, the IC testing equipment, particularly the functional testing equipment 2, is structured to output a binary logic signal.

In response, there is a trend toward reducing the number of IC terminals and downsizing the IC. One way to reduce the number of IC terminals is to use multi-value logic signals. In order to test an IC that uses multi-value logic signals, the functional test device 2 must have a structure that can output multi-value logic signals. Functional testing equipment has traditionally been expensive. However, if a function for outputting a multivalued logic signal is added on top of that, the cost will become even more expensive.

"Means for Solving Problems" The DC testing device 1 has a structure that can output various DC voltages as an original function. In other words, it has a multi-value DC voltage generation function. The present invention is configured to utilize the multi-value voltage output function of the DC testing device 1 to output a multi-value logic signal for functional testing.

In other words, the output circuit of DC test equipment 1 has a conventional
Equipped with a DA converter, a digital signal corresponding to the voltage value or current value to be applied to the terminal of the IC is applied to the DA converter, and the digital signal is converted to DA to generate a voltage or current of a predetermined value to the IC under test. The structure is such that it gives

In this invention, the DC test device 1 is provided with
The structure is such that the DA converter is given a digital signal that generates a pattern signal of multi-valued logical values used for functional testing, and the output circuit of the DC test device 1 is used as the output circuit of the functional testing device, and the multi-valued logical signal is used. It is configured so that IC testing equipment can be manufactured at low cost.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In this figure, the logic comparator and pass/fail indicator are omitted. 11A, 11B, 11C...1 shown in Figure 1
1N indicates the output circuit of the DC test device.
These output circuits 11A to 11N include a DA converter 12, an excitation driver 13, and a voltage-current output switching circuit 1.
It is composed of 4 and 4. The voltage-current output switching circuit 14 is a circuit that switches between a voltage application current measurement mode and a current application voltage measurement mode during a DC test. The structure is such that a voltage or current is applied to each terminal of the device under test 3 through this voltage-current output switching circuit 14.

In this invention, memories 16A, 16B, 16C...16 are provided in each preceding stage of output circuits 11A to 11N.
DC test data used in the DC test is transferred from the sequence controller 7 to the memories 16A to 16N, and the DC test is performed using the data. During a functional test, digital data defining each logic level of the multi-value logic signal used in the IC 3 under test is stored in each of the memories 16A to 16N, and which of the logic levels is selected and given to the DA converter 12. The pattern memory 17 provides an address signal for determining the address. The logic level selected by this address signal is outputted from each output circuit 11A to 11N.

Address data A for generating a pattern signal is transferred from the sequence controller 7 to the pattern memory 17 and written therein. The address data written in the sequence controller 7 is read out using the address signal B. Address signal B is an address signal output from the sequence controller 7
_B1 and the continuous address signal _B2 generated by the address counter 18 are sent to the multiplexer 19.
It has a structure that can be selected.

As shown in FIG. 2, the pattern memory 17 has a plurality of areas A ₁ , A ₂ , A ₃ . . . An, and each channel CH _{1 ,} CH _{2 ,} CH _{3 ,} . …
Address data for generating a pattern signal is written for each CHn. The arrow X shown in FIG. 2 indicates the address direction. In other words, each storage area A ₁ ~ An
Reading is performed using a common address signal.

Operation During a DC test, the memories 16A to 16N are fixed at one address, and the sequence controller 7 supplies digital data necessary for the DC test to this one address, and this digital data is sequentially supplied to the DA converter 12. Therefore, memory 16A
~16N is used as a latch circuit during DC testing. In the DC test, the IC under test is
Apply the desired voltage value V _H (or current) to terminal 3,
In this state, the current or voltage flowing through the terminal is measured and its quality is determined. The DC test is performed on each terminal in either a voltage application current measurement mode or a current application voltage measurement mode.

During the function test, memory 16A to 16N is tested.
Contains data that defines the multi-value logic level used in IC3.

In other words, for example, as shown in Figure 4, 0 volt is L.
Logic level, +5 volts as H logic level,
If a ternary signal with +2.5 volts in between is used as M logic, memories 16A to 16
As shown in Fig. 5, each start address _D1 is
Digital data for outputting zero volts from the DA converter 12 is stored, and the second address _D2 is
Digital data for outputting +2.5 volts from the DA converter 12 is stored, and the third address _D3 is
It stores digital data for outputting +5 volts from the DA converter 12.

On the other hand, when outputting pattern signals in the order of L, H, M, L, L, H, M, L from the output circuit 11A as shown in FIG. A ₁ with 16A memory
The address data of D _1, D _3, D _2, D _1, D _1, D _3,
Write D _{2 and} D ₁ in this order.

In this way, address data for generating a desired pattern signal is stored in each of the storage areas A ₁ to An of the pattern memory 17, and each output circuit 11A to 11A is accessed by accessing each memory 16A to 16N using this address data. A multivalued logic pattern signal can be output from 11N.

The pattern memory 17 can be read in a continuous read mode for each address by the address counter 18, or in a random access mode by an address signal given from the sequence controller 7. It is thus possible to generate various applied voltage or current combinations.

``Effects'' According to the present invention, the output circuits 11A to 11N of the DC test equipment are used to output multi-value logic signals, so that the test equipment for ICs that use multi-value logic signals can be made at low cost. can be made to

"Modified Embodiment of the Invention" In the above, we have explained the case where three-value signals of L, M, and N are generated as multi-value logic signals, but it is also possible to generate multi-value logic signals not only with three values but also with four values or more. You can also do it.

Furthermore, as shown in FIG. 7, memories 16A to 16N
The storage capacity of the memories 16A to 16N is made relatively large, pattern data defining multi-value logic levels is written in the memories 16A to 16N, and the pattern data read from the memories 16A to 16N is used to directly convert the DA converter 12.
It is also possible to generate a pattern signal having multiple logic levels.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the internal structure of a pattern memory used in this invention, and FIG. 3 is a diagram for performing a DC test using an IC testing apparatus according to this invention. Figures 4 and 6 are waveform diagrams showing the waveforms of the output signals in the case of
The figure is a waveform diagram for explaining an example of a multivalued logic signal waveform, FIG. 5 is a block diagram for explaining the operation of the main part of this invention, and FIG. 7 is for explaining another embodiment of this invention. Figure 8 shows the block diagram for the conventional
FIG. 2 is a block diagram for explaining an IC test device. 1: DC test equipment, 2: Functional test equipment, 3: IC under test, 4: Switching circuit, 5: Logic comparator, 6:
Pass/fail indicator, 7: Sequence controller, 8,
9: Driver group, 11A to 11N: Output circuit, 1
2: DA converter, 13: driver, 14: voltage -
Current output switching circuit, 16A to 16N: Memory, 1
7: Pattern memory, 18: Address counter,
19: Multiplexer.

Claims (1)

[Scope of Claims] 1. A: a number of DA converters corresponding to the number of terminals of the IC under test; B: a driver that supplies the output of this DA converter to each terminal of the IC under test; and C: each of the above DA converters. A memory provided on the input side, and D. Through this memory, data for DC testing is given to each of the above DA converters, and data specifying a multi-value logic level is written to the above memory, and this data is selected. An IC testing device comprising: a sequence controller that outputs a multi-valued logic pattern signal from each of the above-mentioned DA converters by sequentially outputting a multi-valued logic pattern signal.