JPH0467071B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a duty valve control system, and particularly to a control signal generation system thereof.

[Conventional technology]

In the conventional duty valve control method, a method of supplying an overexcitation current when power is supplied from off to on of the duty valve is disclosed in Japanese Patent Application Laid-open No. 61-228602 and Japanese Patent Application Laid-open No. 61-263103. However, when controlling a plurality of duty valves, the signal generation method has not been improved. Third
The figure is a circuit diagram showing a control method for such a plurality of duty valves. In the figure, 1a, 1
b, 1c are overexcitation transistors, 2a, 2b,
2c is a holding current transistor, 3a, 3b, 3
c is a current limiting resistor; 4a, 4b, and 4c are duty valves; 5 is overexcitation signal generation means and duty control signal generation means for each of these duty valves _4a to 4c; D01, _D02 , and _D03 are the overexcitation signals;
D ₁₁ , D ₁₂ , and D ₁₃ are duty control signals. Further, 6a, 6b, 6c and 7a, 7b, 7c are base resistances of overexcitation transistors 1a to 1c and holding current transistors 2a to 2c, respectively.

In the duty valve control circuit configured as described above, the overexcitation transistors 1a to 1c are driven by the respective overexcitation signals D ₀₁ to _{D 03} , and the holding current transistors are driven by the duty control signals D ₁₁ to _{D 13} . 2a to 2c are driven to control duty valves 4a to 4c, respectively.

_Figure 4a _{shows the} overexcitation _signal D ₀ The timing is shown for one duty valve. The subscript _X takes any integer from 1 to 3, and the duty control signals D ₁₁ , D ₁₂ , D ₁₃
For example, in FIG. 4a, the falling point of the signal is the duty valve 4a~
Each phase differs depending on the signal 4c, and the duty ratio of the signal also generally differs. Furthermore, the phase at which the overexcitation signals D ₀₁ , D ₀₂ , and D ₀₃ change from OFF to ON, for example, the falling point in FIG. 4A, differs depending on the duty valves 4a to 4c.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional duty valve control method, when controlling a plurality of duty valves 4a to 4c, the duty control signal and the overexcitation signal are each required independently for the number of duty valves, which simplifies the circuit and reduces the size of the device. However, it has been difficult to reduce costs and reduce costs.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a duty valve control system that can reduce the size and cost of the device.

[Means for solving problems]

The duty valve control method according to this invention is as follows:
In controlling a plurality of duty valves, the overexcitation signal is shared by synchronizing the transition points of each duty control signal from OFF to ON in the same phase.

[Effect]

In this invention, each duty control signal is synchronized in phase, and the overexcitation control signal is shared to control a plurality of duty valves.

〔Example〕

FIG. 1 is a circuit diagram showing a duty valve control system according to an embodiment of the present invention. In the figure, 1
a, 1b, 1c to 4a, 4b, 4c and 6a to
6c, 7a to 7c have structures corresponding to those in FIG. 3, so the same reference numerals are given and the explanation thereof will be omitted. 50
are overexcitation signal generating means and duty control signal generating means 8a to 8c which output respective duty control signals D ₁₁ , D ₁₂ , D ₁₃ and a single overexcitation signal D ₀ for each duty valve 4a to 4c;
is an OR circuit, 9a to 9c are duty control signals
An inverter that inputs D ₁₁ , D ₁₂ , and D ₁₃ , and its output is connected to the second input terminal of the OR circuits 8 a to 8 c, and the overexcitation signal D ₀ is connected to the first input terminal of the OR circuits 8 a to 8 c. is connected, and the output terminal is connected to the overexcitation transistor 1a via base resistors 7a to 7c.
~1c is connected to the base.

The duty valve control circuit configured in this manner uses the same duty control signal at the initial point of energization for each of the duty valves 4a to 4c, so that the same overexcitation signal _D0 can be generated.

FIG. 4b shows the timing of the overexcitation signal _D0 , the duty control signals _D11 to _D13 , and the currents _I4a to _I4c flowing through the duty valves 4a to 4c, and changes the duty control signals _D11 to _D13 from OFF to ON. It can be seen that the change point (indicated by a broken line) is in-phase synchronized. Therefore, it is understood from FIG. 4b that the overexcitation signal D ₀ can be shared among the duty valves 4a to 4c.

FIG. 2 shows another embodiment, in which the overexcitation signal generation means and duty control signal generation means 50 in the first embodiment are replaced by duty control signal generation means 51 and overexcitation signal generation means 5.
It is separated into two parts. The overexcitation signal generating means 52 makes at least each phase of the duty control signal in phase and obtains a monostable pulse width from the initial point of energization of the duty control signal, and the overexcitation signal D ₀ that is the output thereof is the same as that of the above embodiment. Similar to OR circuit 8a
~8c is connected to the first input terminal.

〔Effect of the invention〕

As described above, according to the present invention, in controlling a plurality of duty valves, the duty control signals of each phase are synchronized in phase, so that the overexcitation signal can be shared, and therefore the overexcitation signal can be generated. Since the circuit does not require the same number of duty valves as in the past, only one circuit is required, so the circuit can be simplified and the device can be downsized, which has the effect of reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a duty valve control method according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a duty valve control method according to another embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional duty valve control method. The circuit diagram and FIG. 4 are signal waveform diagrams showing signal timings of the conventional example and the first embodiment, respectively. 1a to 1c...transistors for overexcitation, 2a to 2
c... Holding current transistor, 4a to 4c... Duty valve, 50... Duty control signal generating means and overexcitation signal generating means, 51... Duty control signal generating means, 52... Overexcitation signal generating means,
8a to 8c, 9a to 9c...logic circuits. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 a plurality of duty valves, overexcitation signal generation means for generating an overexcitation signal, duty control signal generation means for generating a duty control signal for determining the on/off ratio of each of the duty valves, and the and a duty valve drive circuit that controls the current of the duty valve on and off in response to the on and off of the duty valve control signal, and also supplies an overexcitation current to the duty valve based on the overexcitation signal during this control, A duty valve control method characterized in that the overexcitation signal is shared by the plurality of duty valves by in-phase synchronizing the transition point of the duty control signal from OFF to ON.