JPH0467373B2 - - Google Patents
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- Publication number
- JPH0467373B2 JPH0467373B2 JP63212798A JP21279888A JPH0467373B2 JP H0467373 B2 JPH0467373 B2 JP H0467373B2 JP 63212798 A JP63212798 A JP 63212798A JP 21279888 A JP21279888 A JP 21279888A JP H0467373 B2 JPH0467373 B2 JP H0467373B2
- Authority
- JP
- Japan
- Prior art keywords
- switching
- power semiconductor
- gate
- semiconductor
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
- H03K17/691—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、スイツチング電源装置のスイツチン
グ素子などに用いられる電力用のMOSFET、
IGBなどの絶縁ゲート型電力用半導体の駆動回路
に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a power MOSFET used in a switching element of a switching power supply device, etc.
Related to drive circuits for insulated gate power semiconductors such as IGBs.
従来、この程絶縁ゲート型電力用半導体の駆動
回路には、第３図に示すように、前記半導体のオ
ン、オフ制御の制御信号を出力する信号処理回路
と前記半導体とをパルストランスを用いて絶縁分
離したものがある。
Conventionally, as shown in FIG. 3, a drive circuit for an insulated gate type power semiconductor uses a pulse transformer to connect the semiconductor and a signal processing circuit that outputs a control signal for turning on and off the semiconductor. Some are insulated and separated.
第３図は絶縁ゲート型電力用半導体としての電
力用MOSFET１の駆動回路を示し、同図におい
て、２はFET１のオン、オフの制御信号の入力
端子、３はFET１のスイツチング周波数より十
分高い数ＭHzで発振する発振回路、４は制御信号
と発振回路３の周力信号とが入力されるアンドゲ
ートであり、オン制御期間Tonのハイレベルの制
御信号によつてオンする。 Figure 3 shows a drive circuit for power MOSFET 1 as an insulated gate power semiconductor. In the figure, 2 is an input terminal for the on/off control signal of FET 1, and 3 is an input terminal of several MHz, which is sufficiently higher than the switching frequency of FET 1. An oscillation circuit 4 oscillates at , and 4 is an AND gate into which a control signal and a peripheral force signal of the oscillation circuit 3 are input, and is turned on by a high-level control signal during the on-control period Ton.
５は巻線比１：１の絶縁用のパルストランスで
あり、１次巻線５ａの巻始めの一端が正電圧Vc
の直流電源６に接続されている。７は制御用スイ
ツチング素子を形成する小信号用MOSFETであ
り、ドレインが１次巻線５ａの他端に接続される
とともにソースがアースされ、かつ、ゲートにア
ンドゲート４の出力が印加される。 5 is an insulating pulse transformer with a winding ratio of 1:1, and one end of the beginning of the primary winding 5a is connected to a positive voltage Vc.
is connected to a DC power supply 6. Reference numeral 7 designates a small signal MOSFET forming a control switching element, whose drain is connected to the other end of the primary winding 5a, whose source is grounded, and whose gate is applied with the output of the AND gate 4.
８，９はトランス５の２次巻線５ｂの巻始めの
一端とFET１のゲートとの間に直列接続された
２個の整流ダイオード、１０は放電路用スイツチ
ング半導体を形成するPNP型のトランジスタで
あり、ベースがダイオード８，９の接続点に接続
され、エミツタがダイオード９、FET１のゲー
トの接続点に接続され、かつ、コレクタが２次巻
線５ｂの他端に接続されている。１１はトランジ
スタ１０のベース、コレクタ間に設けられたバイ
アス用の抵抗である。 8 and 9 are two rectifier diodes connected in series between one end of the beginning of the secondary winding 5b of the transformer 5 and the gate of the FET 1, and 10 is a PNP type transistor forming a switching semiconductor for the discharge path. The base is connected to the connection point between the diodes 8 and 9, the emitter is connected to the connection point between the diode 9 and the gate of the FET 1, and the collector is connected to the other end of the secondary winding 5b. 11 is a bias resistor provided between the base and collector of the transistor 10.
なお、２次巻線５ｂの他端はFET１のソース
に接続されている。 Note that the other end of the secondary winding 5b is connected to the source of the FET1.
そして、制御信号は第４図ａに示すように、
FET１のオン制御期間Tonにハイレベルになる
とともに、FET１のオフ制御期間Toffにローレ
ベルになる。 Then, the control signal is as shown in Fig. 4a,
It becomes high level during the on control period Ton of FET1, and becomes low level during the off control period Toff of FET1.
一方、発振回路３は第４図ｂに示すように、数
ＭHzの一定周波数の発振信号を出力する。 On the other hand, the oscillation circuit 3 outputs an oscillation signal with a constant frequency of several MHz, as shown in FIG. 4b.
そして、制御信号のハイレベルにもとづき、オ
ン制御期間Tonにのみアンドゲート４がオンし、
その間、第４図ｃに示すように発振回路３の出力
信号がFET７のゲートに印加され、発振回路３
の出力信号に周波数でFET７がスイツチングす
る。 Then, based on the high level of the control signal, the AND gate 4 is turned on only during the on control period Ton,
Meanwhile, as shown in FIG. 4c, the output signal of the oscillation circuit 3 is applied to the gate of the FET 7, and the oscillation circuit 3
FET7 switches according to the frequency of the output signal.
さらに、FET７のスイツチングにもとづき、
１次巻線５ａに直流電源６が間欠的に印加され、
トランス５がパルス駆動されて２次巻線５ｂに
FET１のゲート制御電力のパルスが発生する。 Furthermore, based on the switching of FET7,
A DC power supply 6 is intermittently applied to the primary winding 5a,
The transformer 5 is pulse driven and the secondary winding 5b
A pulse of gate control power for FET1 is generated.
そして、２次巻線５ｂの出力パルスがダイオー
ド８，９を介してFET１のゲートに印加されて、
このとき、出力パルスの間隔がトランジスタ１０
のオフからオンへの回復期間より短いため、トラ
ンジスタ１０がオフに保持され、しかも、FET
１のゲート、ソース間容量Cgsによつてパルスが
積分充電されて平滑されるため、FET１のゲー
ト電圧が第４図ｄに示すようにほぼ一定のオン電
圧に保持され、FET１がオンに保持される。 Then, the output pulse of the secondary winding 5b is applied to the gate of the FET 1 via the diodes 8 and 9.
At this time, the interval between output pulses is
The off-to-on recovery period of FET 10 is shorter than the off-to-on recovery period of FET
Since the pulse is integrally charged and smoothed by the gate-source capacitance Cgs of FET 1, the gate voltage of FET 1 is maintained at a nearly constant on voltage as shown in Figure 4d, and FET 1 is kept on. Ru.
つぎに、オン制御期間Tonからオフ制御期間
Toffに切換わる第４図ａのt1時になると、２次巻
線５ｂの出力パルスの遮断にもとづき、トランジ
スタ１０がオフからオンに反転し、容量Cgsの蓄
積電荷がトランジスタ１０を介して放電し、
FET１が迅速にオフに反転する。 Next, from the on control period Ton to the off control period
At time t 1 in FIG. 4a when the state is switched to Toff, the transistor 10 is turned from off to on based on the cutoff of the output pulse of the secondary winding 5b, and the accumulated charge in the capacitor Cgs is discharged through the transistor 10. ,
FET1 quickly flips off.
以降、制御信号のレベル反転にもとづき、前述
と同様の動作がくり返され、制御信号の周波数、
たとえば100KHz程度でFET１がスイツチングす
る。 After that, the same operation as described above is repeated based on the level inversion of the control signal, and the frequency of the control signal,
For example, FET1 switches at around 100KHz.
前記第３図の駆動回路において、電源６の電圧
Vcを15Vとした場合、第５図ａに示す発振回路
３の出力信号によつてFET７がオフするときの
１次巻線５ａとFET７との接続点の電圧、すな
わちFET７のドレイン、ソース間電圧Vdsは、ト
ランス５のインダクタンスの逆起電圧にもとづ
き、同図ｂに示すように、そのピーク値が電圧
Vcの２倍以上の約40Vにもなる。
In the drive circuit shown in FIG. 3, the voltage of the power supply 6 is
When Vc is 15V, the voltage at the connection point between the primary winding 5a and the FET7 when the FET7 is turned off by the output signal of the oscillation circuit 3 shown in Figure 5a, that is, the voltage between the drain and source of the FET7. Vds is based on the back electromotive force of the inductance of the transformer 5, and its peak value is the voltage
It reaches about 40V, which is more than twice Vc.
そして、発振回路３がFET７などの動作に無
関係に一定周波数で動作するため、電圧Vdsがほ
ぼ前記ピーク値のときに、発振回路３の出力信号
の立上りによつてFET７がターンオンする事態
も発生し、この場合、前記ピーク値の電圧で充電
されたFET７のドレイン、ソース間容量Cdsの大
きな蓄積エネルギ（＝１／２CdsVds2）がFET７で
消費され、FET７の熱損失が大きくなつてFET
７の温度が著しく上昇する。 Since the oscillation circuit 3 operates at a constant frequency regardless of the operation of the FET 7, etc., a situation may occur where the FET 7 is turned on due to the rise of the output signal of the oscillation circuit 3 when the voltage Vds is approximately at the above-mentioned peak value. In this case, the large stored energy (=1/2CdsVds 2 ) of the drain-source capacitance Cds of FET7 charged with the voltage of the peak value is consumed in FET7, and the heat loss of FET7 increases, causing the FET
7 temperature rises significantly.
そのため、熱暴走によるFET７の破損が発生
し易く、信頼性を向上できない問題点がある。 Therefore, there is a problem that the FET 7 is easily damaged due to thermal runaway, and reliability cannot be improved.
本発明は、パルストランスの駆動に用いられる
制御用スイツチング半導体の熱暴走を防止し、信
頼性の高い絶縁ゲート型電力用半導体の駆動回路
を提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable insulated gate power semiconductor drive circuit that prevents thermal runaway of a control switching semiconductor used to drive a pulse transformer.
前記目的を達成するために、本発明の絶縁ゲー
ト型電力用半導体の駆動回路においては、絶縁ゲ
ート型電力用半導体をオン、オフ制御する制御信
号にもとづき、前記電力用半導体のオン制御期間
に、絶縁用のパルストランスの１次巻線に直列接
続された制御用スイツチング半導体を高周波駆動
し、前記パルストランスの２次巻線の出力パルス
を前記電力用半導体のゲートに印加し、前記電力
用半導体の端子間容量の積分充電によつて前記電
力用半導体をオンに保持し、かつ、前記出力パル
スが遮断されるオフ制御への切換え時、前記出力
パルスの遮断によつてオンする放電路用スイツチ
ング半導体により、前記電力用半導体の端子間容
量の蓄積電荷を放電し、前記電力用半導体をオフ
に反転する絶縁ゲート型電力用半導体の駆動回路
において、
前記制御信号の入力により前記オン制御期間に
のみオンするアンドゲートと、
前記アンドゲートの出力信号の立上がりによつ
てトリガされ、高周波駆動用の微小パルス幅のス
イツチング制御信号を前記スイツチング半導体に
供給する単安定マルチバイブレータと、
前記スイツチング半導体のスイツチングにもと
づく前記１次巻線と前記スイツチング半導体との
接続点の電圧の高周波変動を抽出する高域フイル
タと、
前記フイルタの出力信号をオフ電圧の低下検出
のしきい値で２値化して反転し、前記接続点の電
圧が前記しきい値に低下したときに立上るトリガ
信号を前記アンドゲートに出力するインバータと
を備えるという技術的手段を講じている。
In order to achieve the above object, in the insulated gate power semiconductor drive circuit of the present invention, based on a control signal that controls on and off the insulated gate power semiconductor, during the on control period of the power semiconductor, A control switching semiconductor connected in series to the primary winding of an insulating pulse transformer is driven at a high frequency, and an output pulse of the secondary winding of the pulse transformer is applied to the gate of the power semiconductor. a discharge path switching device that holds the power semiconductor on by integral charging of the capacitance between the terminals of the switch and turns on when the output pulse is cut off when switching to off control in which the output pulse is cut off; In an insulated gate power semiconductor drive circuit that discharges accumulated charge in a capacitance between terminals of the power semiconductor by a semiconductor and turns off the power semiconductor, only during the on control period by inputting the control signal. an AND gate that is turned on; a monostable multivibrator that is triggered by the rise of the output signal of the AND gate and supplies a switching control signal with a minute pulse width for high-frequency driving to the switching semiconductor; a high-frequency filter for extracting high-frequency fluctuations in the voltage at the connection point between the primary winding and the switching semiconductor; and binarizing and inverting the output signal of the filter at a threshold for detecting a drop in off-voltage; A technical measure is taken to include an inverter that outputs a trigger signal that rises when the voltage at the connection point drops to the threshold value to the AND gate.
以上のように構成された絶縁ゲート型電力用半
導体の駆動回路においては、オン制御期間に、単
安定マルチバイブレータから出力されたスイツチ
ング制御信号によつて制御用スイツチング半導体
がスイツチングし、このとき、制御用スイツチン
グ半導体がオフする毎に、高域フイルタの出力信
号にもとづくインバータの動作により、パルスト
ランスの１次巻線と制御用スイツチング半導体と
の接続点の電圧がオフ直後のピーク値からしきい
値に低下した後、単安定マルチバイブレータがト
リガされるため、制御用スイツチング半導体のタ
ーンオンが前記ピーク値より低い電圧になつてか
ら行われ、制御用スイツチング半導体の熱損失が
低下して熱暴走が防止される。
In the insulated gate power semiconductor drive circuit configured as described above, the control switching semiconductor is switched by the switching control signal output from the monostable multivibrator during the on-control period, and at this time, the control switching semiconductor is switched by the switching control signal output from the monostable multivibrator. Each time the control switching semiconductor turns off, the inverter operates based on the output signal of the high-pass filter, and the voltage at the connection point between the primary winding of the pulse transformer and the control switching semiconductor changes from the peak value immediately after the switch off to the threshold value. Since the monostable multivibrator is triggered after the voltage drops to the peak value, the control switching semiconductor is turned on after the voltage drops to a voltage lower than the peak value, reducing heat loss in the control switching semiconductor and preventing thermal runaway. be done.
〔実施例〕
１実施例について第１図及び第２図を参照して
以下に説明する。[Example] One example will be described below with reference to FIGS. 1 and 2.
第１図において第３図と同一記号は同一のもの
を示し、１２はFET７のドレインとアースとの
間にコンデンサ１２ａと抵抗１２ｂとを直列接続
して形成された高域フイルタ、１３は入力端子が
抵抗１３′を介してコンデンサ１２ａ、抵抗１２
ｂの接続点に接続されたインバータ、１４は入力
端子２の制御信号とインバータ１３の出力信号と
が入力されるアンドゲート、１５はアンドゲート
１４の出力信号の立上りによつてトリガされる単
安定マルチバイブレータであり、制御用スイツチ
ング半導体を形成するFET７のゲートに高周波
駆動用の微小パルス幅のスイツチング制御信号を
供給する。 In Fig. 1, the same symbols as in Fig. 3 indicate the same things, 12 is a high-pass filter formed by connecting a capacitor 12a and a resistor 12b in series between the drain of FET 7 and the ground, and 13 is an input terminal. is connected to the capacitor 12a and the resistor 12 via the resistor 13'.
an inverter connected to the connection point b; 14 an AND gate into which the control signal of the input terminal 2 and the output signal of the inverter 13 are input; 15 a monostable which is triggered by the rise of the output signal of the AND gate 14; It is a multivibrator and supplies a switching control signal with a minute pulse width for high frequency driving to the gate of FET 7 which forms a switching semiconductor for control.
そして、第２図ａに示すようにta時に制御信号
がハイレベルになり、オン制御期間Tonに移行す
ると、制御信号のハイレベルによつてアンドゲー
ト１４がオンする。 Then, as shown in FIG. 2a, the control signal becomes high level at time ta, and when the on-control period Ton begins, the AND gate 14 is turned on by the high level of the control signal.
このとき、FET７がオフして１次巻線５ａと
FET７との接続点の電圧、すなわちFET７のド
レイン、ソース間電圧Vdsが第２図ｂに示すよう
に電圧Vcに保持され、コンデンサ１２ａ、抵抗
１２ｂの接続点の電圧、すなわちフイルタ１２の
出力信号の電圧が同図ｃに示すようにOVに保持
されている。 At this time, FET7 is turned off and the primary winding 5a
The voltage at the connection point with FET 7, that is, the drain-source voltage Vds of FET 7, is held at voltage Vc as shown in FIG. The voltage is maintained at OV as shown in c of the figure.
また、オフ電圧の低下検出のしきい値を形成す
るインバータ１３の入力しきい値がOVに設定さ
れ、インバータ１３の出力信号の電圧が第２図ｄ
に示すようにハイレベルに保持されている。 In addition, the input threshold of the inverter 13, which forms the threshold for detecting a drop in the off-voltage, is set to OV, and the voltage of the output signal of the inverter 13 is
It is maintained at a high level as shown in the figure.
そのため、制御信号のハイレベルの立上によつ
てアンドゲート１４の出力信号がハイレベルに立
上り、マルチバイブレータ１５がトリガされ、マ
ルチバイブレータ１５がらFET７のゲートに、
たとえば100nsecの微小パルス幅のハイレベルの
スイツチング制御信号が出力され、FET７がオ
ンして１次巻線５ａ、FET７に電源６からの電
流が流れる。 Therefore, as the control signal rises to a high level, the output signal of the AND gate 14 rises to a high level, the multivibrator 15 is triggered, and the multivibrator 15 outputs a signal to the gate of the FET 7.
For example, a high-level switching control signal with a minute pulse width of 100 nsec is output, FET 7 is turned on, and current from power supply 6 flows through primary winding 5a and FET 7.
このとき、コンデンサ１２ａの放電にもとづ
き、フイルタ１２の出力信号の電圧は第２図ｃに
示すように、電圧−Vcに低下する。 At this time, due to the discharge of the capacitor 12a, the voltage of the output signal of the filter 12 decreases to the voltage -Vc, as shown in FIG. 2c.
つぎに、マルチバイブレータ１５のスイツチン
グ制御信号がローレベルに立下つてFET７がオ
フすると、１次巻線５ａの通電遮断により、トラ
ンス５のインダクタンスの逆起電圧にもとづく高
電圧がFET７に印加され、電圧Vdsが過渡的に電
圧Vcの２倍以上の高電圧になり、その後、前記
逆起電圧の消失によつて電圧VdsがVcに低下し
始め、電圧Vdsが第２図ｂに示すように高周波変
動する。 Next, when the switching control signal of the multivibrator 15 falls to a low level and the FET 7 is turned off, the primary winding 5a is cut off, and a high voltage based on the back electromotive force of the inductance of the transformer 5 is applied to the FET 7. The voltage Vds transiently becomes a high voltage that is more than twice the voltage Vc, and then, due to the disappearance of the back electromotive force, the voltage Vds begins to decrease to Vc, and the voltage Vds becomes high frequency as shown in Figure 2b. fluctuate.
このとき、電圧Vdsの変動にしたがつてコンデ
ンサ１２ａが充放電され、フイルタ１２によつて
電圧Vdsの高周波変動が抽出され、フイルタ１２
の出力信号が電圧Vdsの変動に追従して変化す
る。 At this time, the capacitor 12a is charged and discharged according to the fluctuation of the voltage Vds, and the high frequency fluctuation of the voltage Vds is extracted by the filter 12.
The output signal of changes to follow the fluctuation of voltage Vds.
そして、電圧VdsがVcに低下すると、フイル
タ１２の出力信号の電圧がインバータ１３の入力
しきい値のOVに低下し、トリガ信号を形成する
インバータ１３の出力信号が第２図ｄに示すよう
にハイレベルに立上る。 Then, when the voltage Vds decreases to Vc, the voltage of the output signal of the filter 12 decreases to the input threshold value OV of the inverter 13, and the output signal of the inverter 13 forming the trigger signal becomes as shown in FIG. 2d. rise to a high level.
さらに、インバータ１３の出力信号に立上りに
よつてアンドゲート１４の出力信号が立上り、マ
ルチバイブレータ１５が再びトリガされ、マルチ
バイブレータ１５からFET７にハイレベルのス
イツチング制御信号が供給され、FET７が再び
オンする。 Furthermore, the output signal of the AND gate 14 rises due to the rise of the output signal of the inverter 13, the multivibrator 15 is triggered again, a high-level switching control signal is supplied from the multivibrator 15 to the FET 7, and the FET 7 is turned on again. .
そして、前述の動作のくり返しにもとづき、制
御信号がハイレベルに保持されるオン制御期間
Tonには、FET７がオフして電圧Vdsがピーク値
からVcまで低下する毎に、マルチバイブレータ
１５がトリガされてFET７がオンし、FET７が
高周波駆動される。 Then, based on the repetition of the above-mentioned operation, an on-control period in which the control signal is held at a high level.
At Ton, every time the FET 7 is turned off and the voltage Vds drops from the peak value to Vc, the multivibrator 15 is triggered, the FET 7 is turned on, and the FET 7 is driven at high frequency.
そのため、オフによつて電圧Vdsがピーク値に
なるときにはFET７がオンされず、電圧Vdsがピ
ーク値の1/2〜1/3程度のVcに低下した後にFET
７がターンオンし、このとき、電圧Vdsの２乗に
比例するFET７のドレイン、ソース間容量Cdsの
蓄積エネルギがピーク値のときの1/4〜1/9に低下
し、FET７の発熱が抑えられる。 Therefore, when the voltage Vds reaches its peak value due to being turned off, FET7 is not turned on, and after the voltage Vds drops to Vc, which is about 1/2 to 1/3 of the peak value, the FET7 is turned off.
7 turns on, and at this time, the accumulated energy of the drain-source capacitance Cds of FET 7, which is proportional to the square of the voltage Vds, decreases to 1/4 to 1/9 of its peak value, suppressing the heat generation of FET 7. .
なお、スイツチング駆動によるFET７の熱損
失は、一般に、１／２×Cds×Vds2×ｆ（ｆはスイツ
チング周波数）で示される。 Note that the heat loss of the FET 7 due to switching drive is generally expressed as 1/2×Cds×Vds 2 ×f (f is the switching frequency).
また、FET７の駆動にもとづく２次巻線５ｂ
の出力パルスは、第３図の場合と同様、ダイオー
ド８，９を介してFET１に供給され、このとき、
FET１のゲート、ソース間容量Cgsの平滑によ
り、FET１のゲート電圧は第２図ｅに示すよう
に、ほぼ一定のオン電圧に保持される。 In addition, the secondary winding 5b based on the drive of FET7
The output pulse of is supplied to FET 1 via diodes 8 and 9 as in the case of Fig. 3, and at this time,
Due to the smoothing of the capacitance Cgs between the gate and source of FET 1, the gate voltage of FET 1 is maintained at a substantially constant on-voltage as shown in FIG. 2e.
さらに、制御信号がローレベルに変化するオフ
制御期間への切換時には、放電路用スイツチング
半導体を形成するトランジスタ１０のオンによ
り、前記容量Cgsの蓄積電荷が放電されてFET１
が迅速にオフする。 Furthermore, when switching to the off control period in which the control signal changes to low level, the transistor 10 forming the switching semiconductor for the discharge path is turned on, so that the accumulated charge in the capacitor Cgs is discharged and the FET 1 is switched on.
turns off quickly.
ところで、前記実施例では制御用スイツチング
半導体にFETを用いたが、制御用スイツチング
半導体にバイポーラ型のトランジスタを用いても
よく、この場合も実施例と同様の効果が得られ
る。 Incidentally, in the above embodiment, an FET is used as the control switching semiconductor, but a bipolar transistor may be used as the control switching semiconductor, and the same effects as in the embodiment can be obtained in this case as well.
また、絶縁ゲート型電力用半導体がIGBなどで
あつてもよいのは勿論である。 Furthermore, it goes without saying that the insulated gate type power semiconductor may be an IGB or the like.
本発明は以上説明したように構成されているた
め、以下に記載するような効果を奏する。
Since the present invention is configured as described above, it produces the effects described below.
制御用スイツチング半導体のスイツチングにも
とづくパルストランスの１次巻線と制御用スイツ
チング半導体との接続点の電圧の高周波変動を高
域フイルタで抽出し、高域フイルタの出力信号に
もとづき、オン制御期間には、前記接続点の電圧
が制御用スイツチング半導体のオフにもとづくピ
ーク値から低下検出のしきい値に低下する毎に、
インバータからアンドゲートを介して単安定マル
チバイブレータにトリガ信号を供給し、単安定マ
ルチバイブレータから制御用スイツチング半導体
に、微小パルス幅のスイツチング制御信号を供給
したことにより、制御用スイツチング半導体のタ
ーンオンが前記ピーク値より低い電圧に低下して
から行われ、制御用スイツチング半導体の熱損失
が低下して熱暴走が防止され、信頼性を著しく向
上することができる。 High-frequency fluctuations in the voltage at the connection point between the primary winding of the pulse transformer and the control switching semiconductor based on the switching of the control switching semiconductor are extracted by a high-pass filter, and based on the output signal of the high-pass filter, the high-frequency fluctuations are detected during the on-control period. Each time the voltage at the connection point decreases from the peak value based on the turning off of the control switching semiconductor to the threshold for detecting a decrease,
By supplying a trigger signal from the inverter to the monostable multivibrator via the AND gate, and supplying a switching control signal with a minute pulse width from the monostable multivibrator to the control switching semiconductor, the turn-on of the control switching semiconductor is as described above. The switching is performed after the voltage has been lowered to a level lower than the peak value, and the heat loss of the control switching semiconductor is reduced, thermal runaway is prevented, and reliability can be significantly improved.
第１図は本発明の絶縁ゲート型電力用半導体の
駆動回路の１実施例の結線図、第２図ａ〜ｅは第
１図の動作説明用のタイミングチヤート、第３図
は従来の絶縁ゲート型電力用半導体の駆動回路の
結線図、第４図ａ〜ｄ、第５図ａ，ｂは第３図の
動作説明用のタイミングチヤートである。
５……パルストランス、５ａ，５ｂ……１次、
２次巻線、１２……高域フイルタ、１３……イン
バータ、１４……アンドゲート、１５……単安定
マルチバイブレータ。
FIG. 1 is a wiring diagram of one embodiment of the insulated gate power semiconductor drive circuit of the present invention, FIGS. 2 a to e are timing charts for explaining the operation of FIG. 1, and FIG. 3 is a conventional insulated gate power semiconductor drive circuit. The wiring diagrams of the drive circuit for the type power semiconductor, FIGS. 4a to d, and 5a and 5b are timing charts for explaining the operation of FIG. 3. 5...Pulse transformer, 5a, 5b...1st order,
Secondary winding, 12... High-pass filter, 13... Inverter, 14... AND gate, 15... Monostable multivibrator.
Claims (1)
する制御信号にもとづき、前記電力用半導体のオ
ン制御期間に、絶縁用のパルストランスの１次巻
線に直列接続された制御用スイツチング半導体を
高周波駆動し、前記パルストランスの２次巻線の
出力パルスを前記電力用半導体のゲートに印加
し、前記電力用半導体の端子間容量の積分充電に
よつて前記電力用半導体をオンに保持し、かつ、
前記出力パルスが遮断されるオフ制御への切換え
時、前記出力パルスの遮断によつてオンする放電
路用スイツチング半導体により、前記電力用半導
体の端子間容量の蓄積電荷を放電し、前記電力用
半導体をオフに反転する絶縁ゲート型電力用半導
体の駆動回路において、 前記制御信号の入力により前記オン制御期間に
のみオンするアンドゲートと、 前記アンドゲートの出力信号の立上りによつて
トリガされ、高周波駆動用の微小パルス幅のスイ
ツチング制御信号を前記スイツチング半導体に供
給する単安定マルチバイブレータと、 前記スイツチング半導体のスイツチングにもと
づく前記１次巻線と前記スイツチング半導体との
接続点の電圧の高周波変動を抽出する高域フイル
タと、 前記フイルタの出力信号をオフ電圧の低下検出
のしきい値で２値化して反転し、前記接続点の電
圧が前記しきい値に低下したときに立上るトリガ
信号を前記アンドゲートに出力するインバータと を備えたことを特徴とする絶縁ゲート型電力用半
導体の駆動回路。[Claims] 1. A controller connected in series to the primary winding of an insulating pulse transformer during the ON control period of the power semiconductor based on a control signal that controls on/off the insulated gate power semiconductor. The power semiconductor is turned on by driving the switching semiconductor at high frequency, applying the output pulse of the secondary winding of the pulse transformer to the gate of the power semiconductor, and integrally charging the capacitance between the terminals of the power semiconductor. held in, and
When switching to off control in which the output pulse is cut off, the discharge path switching semiconductor, which is turned on by the cutoff of the output pulse, discharges the accumulated charge in the capacitance between the terminals of the power semiconductor, and the power semiconductor In a drive circuit for an insulated gate power semiconductor that turns off and inverts, the AND gate is turned on only during the on control period by the input of the control signal, and the high frequency drive is triggered by the rising edge of the output signal of the AND gate. a monostable multivibrator that supplies a switching control signal with a very small pulse width to the switching semiconductor; and extracting high-frequency fluctuations in voltage at a connection point between the primary winding and the switching semiconductor based on switching of the switching semiconductor. a high-pass filter; the output signal of the filter is binarized and inverted at a threshold for detecting a drop in off-voltage; and a trigger signal that rises when the voltage at the connection point drops to the threshold is set to the AND An insulated gate power semiconductor drive circuit characterized by comprising an inverter that outputs to a gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63212798A JPH0260318A (en) | 1988-08-26 | 1988-08-26 | Driving circuit for insulated gate type semiconductor for electric power |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63212798A JPH0260318A (en) | 1988-08-26 | 1988-08-26 | Driving circuit for insulated gate type semiconductor for electric power |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0260318A JPH0260318A (en) | 1990-02-28 |
| JPH0467373B2 true JPH0467373B2 (en) | 1992-10-28 |
Family
ID=16628556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63212798A Granted JPH0260318A (en) | 1988-08-26 | 1988-08-26 | Driving circuit for insulated gate type semiconductor for electric power |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0260318A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677797A (en) * | 1992-08-26 | 1994-03-18 | Sansha Electric Mfg Co Ltd | Power switching semiconductor module |
| JP4712489B2 (en) * | 2005-08-29 | 2011-06-29 | 三洋電機株式会社 | Mute circuit |
| JP2008160347A (en) * | 2006-12-22 | 2008-07-10 | Matsushita Electric Works Ltd | Semiconductor relay device |
-
1988
- 1988-08-26 JP JP63212798A patent/JPH0260318A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0260318A (en) | 1990-02-28 |
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