JPH0469391B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active matrix display body suitable for large-capacity display of television images, etc. The purpose of the present invention is to provide the display body with a display data reading function so that calculations and storage can be performed based on the display data. It is an object of the present invention to provide a highly functional active matrix display body that enables the above operations.

In recent years, information devices such as televisions and computers have become smaller and even portable devices have appeared. Displays are essential for such portable information devices, but conventional CRT-type displays are difficult to handle due to volume and power consumption limitations, and recently large-capacity displays using liquid crystals have been proposed. ing.

Among them, the active type developed for TV display.
Matrix display bodies have almost reached the level of practical use. However, current active matrix displays simply display images based on video signals obtained by reception, etc. For example, they may digitally store TV images in memory, or perform calculations based on images. It was not possible to do so. This is because the active matrix display has a capacitor for each pixel, and although it has a memory function, it does not have a data reading function. Regarding television broadcasting, teletext is expected to begin soon, and it is thought that the data obtained from broadcasting will further expand.

Further, even when an active matrix display body is used in a display section of an electronic computer, if each bit (pixel) of the display body can be arbitrarily accessed, the display body itself can be used as a RAM.

As mentioned above, by providing the active matrix display with the function of reading display data,
The functionality of the active display can be further enhanced.

Next, an embodiment of the present invention will be explained in detail.

FIG. 1 shows the structure of an active matrix display according to the present invention.

103 is a liquid crystal display section, inside of which 1 cell is 1
It consists of a pixel group with a circuit configuration like 04.
A cross-sectional view of the silicon substrate 104 is shown in FIG.

207 is a P ⁻ silicon substrate. 209
A gate oxide film 206 and a polycrystalline silicon gate are formed on the n ⁺ source and drain layers to form transistor 105. 10
The source side of 5 is connected to a data line (112 in FIG. 1) having a composition such as Al or Si. The drain side of 105 is connected to the Al wire 205. 20
5 is partially connected to the polycrystalline silicon layer 203. A field oxide film 208 is interposed between the polycrystalline silicon layer 203 and the silicon substrate to form a capacitor 106. 203
The other end of the Al wire is the aluminum layer 210 near the top
It is connected to the. 210 is a segment electrode for driving liquid crystal. 210 indicates the lighting and non-lighting of the liquid crystal 107 sandwiched between the upper common electrode and the upper common electrode.
controlled by the electric charge stored in the

101 is a driver for driving the column lines (hereinafter referred to as R lines) of the active matrix (generates drive signals R ₁ to _{R o} , turns on any one of H ₁ to _{H o} ,
Decide which R line to select), 102 active matrix row line (hereinafter referred to as G line)
Generate drive signals for drive drivers G ₁ to G _o ,
The transistor in each pixel cell like 105
Control ON/OFF.

Reference numeral 102 in FIG. 1 is a drive circuit for driving the gate G line of the transistor 105 in the 104 pixels, and FIG. 3 shows an example of a dynamic shift register circuit. One cell 301 of the shift register has four transistors 3 as shown in the figure.
03-306 and one bootstrap capacity 30
It is composed of 2. The clock has two phases, φ1 and φ2, and is set to “1” by inputting the start pulse SPA.
The potentials are sequentially transferred in synchronization with the clock.
The outputs G ₁ to G _n of each shift register are outputted to the gate lines, and as a result, each gate line is sequentially selected as shown in FIG.

For example, when displaying television images using this active matrix, the frame frequency is slow at 60 Hz, so normal dynamic operation is difficult, and the gate line has a parasitic capacitance of several tens of pF. In order to completely turn on the transistors inside, it is necessary to apply a voltage greater than the maximum voltage of the data line plus a threshold value that takes into account the backgate effect. For this reason, an input transistor, a far-gate transistor 303, is used for the shift register input, and after storing charge at each point of P ₁ to _{P n} ,
Depending on the bootstrap capacity (e.g. 302),
Write “1” to G ₁ to G _n . Furthermore, in order to guarantee operation at low frequencies, a potential fixing transistor 30 is used.
5 is added and refreshed to the "0" level every half cycle of the clock. The capacitances CG ₁ to CG _n are parasitic capacitances to the G line and ensure dynamic operation.

The above timing relationship is shown in FIG.

FIG. 5 shows a data line side drive circuit 1 according to the present invention.
This is an example of 01. The shift register cell 501 includes a bootstrap capacitor 503 and a reset transistor 506 for selecting a shift register, including transistors 504 and 505 necessary for operation, which will be described later.
It is made up of. First stage shift register
A start pulse SP _B is applied to the cell via the input gate 502. Also, each shift register output R ₁
~R _o is the sample-and-hold transistor H ₁ ~H _o
The data signals are sampled and held by the parasitic capacitances CR ₁ to CR _o on the data lines D' ₁ to D' _o . The data line side drive circuit performs all processing while one G line on the row side is selected, so it is fast, so there is no need to consider leakage current, but it increases due to the high speed. It is necessary to consider reducing power consumption. For this reason, the shift register uses a four-phase clock instead of two. The sample-and-hold transistors H ₁ to _{H o} require fairly high-speed switching, but their gate inputs are applied with an amplitude nearly twice that of the clock signal due to bootstrap operation, as shown in Figure 6. It has the advantage of being able to switch very quickly (see Figure 6).

T ₁ -T _o are analog switches for writing and refreshing the memory.

As shown in FIG. 6, during the write period, φR is always "1", so the charges accumulated in CR ₁ to _{CR o} are transferred to D ₁ through the analog switches T ₁ to _{T o} .
~ _D1 is transferred to the data line and written to the pixel memory.

During read and refresh periods,
When the READ signal becomes "0", the sense amplifiers A ₁ to A _o operate, and the data read from the pixel memory is amplified and output to the data lines D' ₁ to D' _o . Immediately after becomes “1”, φR becomes “1”
Then, the sense-amplified data in the pixel memory is written into the pixel memory, and the data in the pixel memory is refreshed. Data is sampled and held by the capacitors C ₁ to _Co.

FIG. 7 shows an example of a sense amplifier. The input terminal a of the sense amplifier is the transistor 702, 703.
, the drain of 704, and the sources of 705 and 706, the source of 702 is connected to the (+) side power supply potential 701, and the sources of 703 and 704 are grounded. In addition, the transistor 70
The drains of 5 and 706 are connected to the output of an inverter consisting of 702 and 703. The output of the inverter is a 708 depletion type.
Connected to the gate of MOS/FET, 708
The source of is grounded, and the drain is connected to the source of 709 and a MOS transistor resistor 710. The drain of 709 is connected to output input terminal b.

The READ signal is connected to the gates of transistors 704 and 706, as well as to the gates of transistors 705 and 709 via an inverter 707.

Transistors 702 and 703 constitute an inverter, and transistors 705 and 70
5 and 706 are connected in parallel and used as a feedback resistor to the input terminal a, forming a C-MOS amplifier circuit as a whole.

In FIG. 7, transistors 705, 706
Signals with mutually opposite phases are applied from the control input terminals to the gates of , but when the signals are "0", the transistor 704 is turned off,
Transistors 705, 706, and 709 are turned on.

Therefore, if is “0”, a
The data signal from the pixel memory input to 708 is amplified by transistors 702 and 703.
input to the gate. The transistor 708 operates in the saturation region depending on the level of the amplified signal, and the potential of C is the same as that of the MOS transistor resistor 71.
It is determined by the ratio of ON resistance of 0 and 708. As a result, a data signal output having the same phase as that of the input terminal a is obtained at the output terminal b.

is “1”, 705,706,
709 is turned off and the sense amplifier does not operate.

Although the sense amplifier in the example of the present invention is an analog amplifier, it is effective when the data in the pixel memory is an analog signal such as a television image signal. The read signal is converted into a digital signal by, for example, an A/D converter and output to a digital signal control circuit.

The sense amplifier may be of a type that uses the threshold voltage of a MOS/FET used in normal dynamic RAM to amplify the sense amplifier.

As described above, in the active matrix electro-optic display device of the present invention, an electro-optic material is sandwiched between a pair of substrates, a transparent electrode is formed on one of the substrates, and a matrix-like material is formed on the other substrate. Multiple gate lines and multiple data lines arranged,
A switching means and a pixel electrode are formed at the intersection of the gate line and the data line, and a data line driving driver is provided on the outer periphery of the other substrate and electrically connected to the plurality of data lines. In an active matrix electro-optical display device including a gate line driving driver electrically connected to the plurality of gate lines, the pixel is connected between the data line driving driver and the plurality of data lines. means for writing data to the electrodes;
The device includes means for reading out data accumulated in the pixel electrode, and the means for reading out the data accumulated in the pixel electrode includes an amplifying means for amplifying the data accumulated in the pixel electrode, and amplifying means for amplifying the data accumulated in the pixel electrode. The present invention is characterized by comprising means for reading the data amplified by the amplifying means, and means for feeding back the data amplified by the amplifying means to the pixel electrode, so that it has the following remarkable effects.

1 For example, it becomes possible to digitally store television images in memory or perform calculations based on the images.

2. Actual displayed image data can be read out with a simple circuit configuration without using external memory.

3 Active matrix type configuration, i.e. 1 piece 1
Since it has a structure in which data is read through an element that switches each pixel electrode independently and writes data, it is possible to read data reliably without being affected by the state of surrounding pixel electrodes.
Data can be read accurately.

4. Since the capacitance stored in the pixel electrode is read out as is, the data stored in the pixel electrode can be read out without applying an external voltage, resulting in low power consumption.

5. Since the read data is amplified and fed back to the pixel electrode, the information on the pixel electrode is not lost for the necessary period.

[Brief explanation of the drawing]

Fig. 1...A configuration diagram of an active matrix display body according to the present invention, Fig. 2...A sectional view of one pixel in the active matrix, Fig. 3...Gate line side drive circuit, Fig. 4...Gate Main timing chart of the line side drive circuit, Fig. 5...Data line side drive circuit, refresh circuit, sense amplifier circuit, Fig. 6...Main timing chart of the data line side drive circuit, Fig. 7...Sense Amplifier configuration.

Claims (1)

[Claims] 1. An electro-optical material is sandwiched between a pair of substrates, a transparent electrode is formed on one of the substrates, and a plurality of gate lines and a plurality of data lines arranged in a matrix on the other substrate; A switching means and a pixel electrode are formed at the intersection of the gate line and the data line, and a data line driving driver is provided on the outer periphery of the other substrate and electrically connected to the plurality of data lines. In an active matrix electro-optical display device including a gate line driving driver electrically connected to the plurality of gate lines, the pixel is connected between the data line driving driver and the plurality of data lines. comprising means for writing data into the electrodes and means for reading out the data accumulated in the pixel electrodes,
The means for reading out the data accumulated in the pixel electrode includes an amplifying means for amplifying the data accumulated in the pixel electrode, a means for reading out the data amplified by the amplifying means, and a means for reading out the data amplified by the amplifying means. An active matrix electro-optic display device comprising means for feeding back to the pixel electrode.