JPH0471553B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a game counter device for counting scores of games involving court changes such as tennis.

In recent years, sports facilities have become fully equipped in various places.
The number of sports entrances is rapidly increasing. Tennis in particular is loved for its fun and social nature, and it is said that around 10 million people in Japan play tennis. However, when playing a game of tennis, the rules for game counts, court changes, services, etc. are complicated, making it difficult for amateurs to understand and requiring someone with considerable experience to be able to referee. There is a growing demand for tennis counters that can be used by referees. The present invention is intended to meet the above-mentioned needs, and its purpose is to provide a game counter device that allows even an amateur to easily act as an umpire.

The gist of the present invention to achieve the above object is to provide two externally operated counting members, point counters,
In a counter device equipped with an initial signal circuit and a display device that displays a set of information from the point counter and the initial signal circuit of each opponent as a set on the left and right sides of the display screen, the information is divided and displayed on the display device. It is characterized by being equipped with a display exchange circuit for exchanging information of each opponent on the left and right sides according to a court change signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings, taking as an example an electronic watch having a counter function for a tennis game.

First, to briefly describe the rules of the tennis game that is the subject of the present invention, one game is 0 (LOVE), 15
(FIFTEEN), 30 (THIRTY), 40 (FORTY),
Game over (GAME-OVER), if the first to win 4 points is established, and both sides become a pair of 3 points each at 40, 40, it will be a deuse, and one side will win 2 points in a row in the order of advantage and game over. It is established.

The opponents alternate serving and receiving after each game, and change courts after each odd-numbered game. A set is established when one side wins 6 or more games and there is a difference of 2 games. and 1
A match is contested by a predetermined number of sets, such as 1 set, 3 sets, 5 sets, etc.

The above are the basic rules, but in addition to these, a tie-break rule is generally adopted to prevent the establishment of a set from taking too long. This is a system that allows a set to be established in the next game if the match result is 6-6, and the point counting method has been changed from the conventional 15, 30,
40, instead of counting 1 point, 1, 2, 3, etc., the set is established when one of the opponents scores 6 points or more with a 2 point difference over the opponent. be.

Next, the configuration of the present invention will be explained.

FIG. 1 is an external view of an electronic timepiece showing an embodiment of the present invention, 1 is an electronic timepiece, 2 is a digital display device, and this digital display device 2 includes two-digit Japanese segment 3a, 3b, 4a, 4
b, a first display part 3 and a second display part 4 each having serve marks 3c, 4c and each advantage mark 3d, 4d, and a third display part 4 each having two-digit character display segments 5a, 5b, 6a, 6b; A display section 5, a fourth display section 6, a fifth display section 7, a sixth display section 8 each equipped with a two-digit Japanese character segment, a mark display section 9 for identifying display contents, and the first A court mark 10 that divides the display section 3, the second display section 4, the third display section 5, and the fourth display section 6 into a square shape;
Referee marks 11 are provided corresponding to the court marks 10.

Ba, Bb, Bc, and Bd are operation buttons used for time adjustment, etc. in the clock function.

FIG. 2 is an external view showing the display state of the time mode of the electronic watch 1 shown in FIG. The display section 5 shows the seconds, and the fourth display section 6 shows the day of the month.
The fifth display section 7 displays the date, and the sixth display section 8 displays the month information, such as 12:30:50, October 26th MO (Monday).

FIG. 3 is an external view showing the display state of the tennis game mode of the electronic watch 1 shown in FIG. ST
is displayed, and court mark 10 and referee mark 1 are displayed.
1 is displayed to indicate that the tennis game mode is set.

Although details will be described later, in this tennis game mode, the first display section 3 and the second display section 4 display points, and the third display section 5 and fourth display section 6 display the initials of the opponents. The initial display section shown, the fifth display section 7, and the sixth display section 8 serve as game display sections showing the number of wins in the game. The first display section 3, the third display section 5, and the fifth display section 7
form a set to display the score of one opponent, the second display section 4, the fourth display section 6, and the sixth display section 8.
are grouped together to represent the score of the other opponent.

Next, the configuration of the electronic timepiece 1 shown in FIG. 1 will be explained with reference to FIG. 4.

FIG. 4 is a block diagram showing the configuration of the electronic timepiece 1. Reference numeral 20 is a clock circuit, and the circuit configuration includes a stopwatch function device and an alarm function device in addition to a normal time counting function device. 21 is a tennis counter circuit; 22 is a display switching circuit for switching and displaying each information of the clock circuit 20 and the tennis counter circuit 21 on the digital display device 2; 23 is each operation button Ba shown in FIG. Bb,
Each switch A, B, operated by Bc, Bd,
The operation signals of C and D are converted into pulse signals Pa, Pb, Pc, Pd
A waveform shaping circuit 24 converts the switch D into
This is a function selection circuit controlled by the operation signal of the operation button Bd, and has two selection loops A and B and a timer circuit connecting these two selection loops. By a short-time operation, the first loop I which circulates through the time mode terminal TK, stopwatch mode terminal CR, and alarm mode terminal AR is operated, and mode selection signals Sth, Scr, and Sar are output to each of the terminals.

Then, when the button Bd is continuously operated for a certain period of time from the state of the first loop, the timer circuit T is activated and the mode shifts to the second loop pro in which the tennis game mode is selected. In this second loop, the set mode terminal is set by pressing button Bd for a short time.
A mode selection signal Sts, Stg, Stb, Ssm is circulated through TS, game mode terminal TG, tie break mode terminal TB, and set monitor terminal SM.
Output.

Furthermore, the state of the first loop can be returned from the state of the second low pro by continuously operating the button Bd for a certain period of time to operate the timer circuit T.

The transition between loops using the timer circuit T can be performed from any mode in each loop, and when transitioning from the first loop to the second loop, the set mode TS is called, and from the second loop In the case of transition to the first loop, the mode returns to time mode TK.

Next, the configuration of the tennis counter circuit 21 will be explained. Reference numeral 30 denotes an operation button exchange circuit for exchanging the correspondence of operation buttons according to a court change in a tennis game, which will be described later. The pulse signals Pa and Pb supplied to the input terminals I ₁ and I ₂ are exchanged and outputted to the output terminals O ₁ and O ₂ according to the logic state of the switching terminal DC. That is, in this embodiment, when the switching terminal DC is logic "0", the signal of the input terminal I ₁ is outputted to the output terminal O ₁ , and the signal of the input terminal I ₂ is outputted to the output terminal O ₂ , and the switching is performed. When the terminal DC becomes logic "1", the I ₁ signal is exchanged with O ₂ and the I ₂ signal is exchanged with O ₁ and output.

32 and 33 are point counters that count points in a tennis game using a point count signal output from the operation button exchange circuit 30, and in the normal game mode, each time one pulse is input to the input terminal I, 0,15,30,
40, and when the tie-break mode is selected and the mode selection signal Stb is supplied, it counts as 0, 1, 2, 3 every time one pulse is supplied to the input terminal I. Generate output.

34 is a point determination circuit which inputs the output information of the two point counters 32 and 33;
It is operated by the pulse signal Pc supplied to the judgment terminal CE via the AND gate 35, and each point counter 32, 3 is operated according to the programmed judgment condition.
3, it supplies a point write signal and an advantage mark output signal during a point counting operation to be described later, and if the determination result is game over, a reset signal is generated to the Q terminal to reset each point counter 32, 33. By this, the zero point display is restored, and based on the judgment result, the output terminal O ₁ or O ₂ of the winner side of the game is
Outputs a gate count signal to.

Reference numerals 36 and 37 are game counters that count games based on the game count signal output from the point judgment circuit 34, and 38 is a game judgment circuit which inputs the output information of the game counters 36 and 37 and calculates the number of games according to the programmed judgment conditions. therefore works,
It has a function as a change signal generating means for outputting a court change signal Sdc to the switching signal terminal DC every time an odd game ends.

Also, if the judgment result detects the end of the set, Q
A transfer command signal is generated at the terminal, and the count information of each game counter 36, 37 is sent out from the output terminal O, thereby returning each game counter 36, 37 to the zero display state, and further based on the determination result. A set count signal is output to the output terminal _O1 or _O2 of the set winner.

39 and 40 are set counters that count the sets according to each signal output from the game counters 36 and 37 and the game determination circuit 38, and each set counter 39 and 40 counts the number of sets that are transferred from the game counters 36 and 37. score storage unit 39 for storing 5 sets of game count information;
a, 40a, and a set storage section 3 that stores the set count signal output from the game determination circuit 38.
9b and 40b, the score storage section 3
9a and 40a have five memories corresponding to each set from set 1 to set 5, and are sent out from the output terminals O of game counters 36 and 37 in response to a transfer command signal outputted from the Q terminal of the game judgment circuit 38. The set storage sections 39b and 40b sequentially write and store the count information corresponding to sets 1 to 5, and the set storage sections 39b and 40b receive the set count signal output from the output terminal _O1 or _O2 of the game judgment circuit 38. Count and record the number of wins in the set. Furthermore, when the set monitor mode selection signal Ssm is supplied to the M terminal, the set counters 39 and 40 receive the monitor pulse supplied to the D terminal.
Pc sequentially outputs the stored information in each memory of the score storage units 39a and 40a as a display signal.

41 and 42 are monitor circuits that monitor signals from point counters 32 and 33 and game counter 3 according to signals supplied to control terminal C.
signals from 6 and 37 and set counters 39 and 4.
The signal from 0 is selectively output.

43 and 44 are initial set circuits;
The initials of each opponent can be set by the set pulse Pa supplied through the AND gate 45.

47 and 48 are display circuits, which correspond to the monitor circuits 41 and 42 and the initial set circuit 4, respectively.
It inputs the signals from 3 and 44 and generates a display signal.

50 is a display exchange circuit, and the display circuit 4
The display signals supplied to two input terminals I ₁ and I ₂ from 7 and 48 are exchanged and outputted to two output terminals O ₁ and O ₂ according to the logic state of the control terminal DC.

51 is a mark storage circuit, 52 is a serve mark control circuit, and the court mark 10 shown in FIG.
A display signal for displaying the referee mark 11 and serve marks 3c and 4c is supplied to the display switching circuit 22. The display switching circuit 22 includes a clock circuit 20, a display switching circuit 50, a mark storage circuit 51,
The display signal from the serve mark control circuit 52 is selectively displayed on the digital display device 2 according to each mode selection signal Stk to Ssm supplied from the function selection circuit 24 via the OR gates 25 and 26. be.

54 is a set signal selection circuit, which selects a pulse signal.
Controlled by PC, it generates set selection signals E ₁ to Ss and supplies them to initial set circuits 43 and 44 and serve mark control circuit 52.

The tennis counter circuit 21 has a structure in which a point counter 32, a game counter 36, a set counter 39, a monitor circuit 41, an initial set circuit 43, and a display circuit 47 constitute a score counter for one opponent. 33, a game counter 37, a set counter 40, a monitor circuit 42, an initial set circuit 44, and a display circuit 48 constitute a score counter for the other opponent.

Next, the operation of the electronic timepiece having the above configuration will be explained according to each mode.

First, to briefly explain the normal mode including the watch mode, the function selection circuit 24 is in the first loop state, and the mode selection signal Stk and the pulse signal Pd generated by the operation of the button Bd are
The display switching circuit 22 outputs Scr and Ssr cyclically and is controlled by the output signal of the OR gate 25 which inputs these mode selection signals.
selects the information signal from the clock circuit 20, and when the time mode selection signal Stk is output, the time information of the clock circuit 20 is selected by the display switching circuit 22, as shown in FIG. Gotoku No. 1
The minutes are displayed on the display section 3, the hours are displayed on the second display section 4, and the hours are displayed on the third display section 5.
The second is displayed on the fourth display section 6, the day on the fifth display section 7, and the month on the sixth display section 8.

Further, when the stopwatch mode selection signal Scr is output, part of the time information of the clock circuit 20 and the stopwatch information are selected by the display switching circuit 22, and the first display section 3 and the second display section 20 select the stopwatch information. Part 4
The hour and minute time information is displayed on the four display sections, third display section 5 to sixth display section 8, respectively.
Stopwatch information for 1/100 seconds, seconds, minutes, and hours is displayed. Additionally alarm mode selection signal
When Sar is being output, the first display section 3 to 4
The display section 6 displays time information of hours, minutes, seconds, and day of the week in the same way as in the time mode, and the fifth display section 7 and the sixth
The display section 8 is used to display the hour and minute of the alarm set time information.

Next, the operation in the tennis counter function will be explained.

As mentioned above, when the button Bd is continuously operated for a certain period of time in the normal mode, the function selection circuit 24 operates the timer circuit T and shifts to the second loop pro state, and the set mode terminal TS is specified first and the set mode is selected. A selection signal Sts is output. Then, an OR gate 26 receives each mode selection signal Sts to Ssm in the second loop processor of the function selection circuit 24.
While being controlled by the output signal of the tennis counter circuit 21, the display switching circuit 22 is switched to a display signal selection state from the tennis counter circuit 21. That is, as shown in FIG. 3, court marks 10 and referee marks 11 are displayed in response to signals from the mark storage circuit 51, thereby creating a tennis court on the display device 2. Furthermore, the set mode mark ST on the mark display section 9 is displayed according to the designation of the mode selection signal Sts. In this state, the opponent is made to select the court and serve.

As an example, we will explain how to set up two players whose initials are TN and NK, and as a result, NK takes the right to serve, and TN chooses the left court. In FIG. 4, the set signal selection circuit 54 is always in the state of the neutral terminal N, and from this state, each set selection signal of _E1 to Ss is cyclically transmitted by the pulse signal Pc generated in accordance with the operation of the button Bc. This signal sequentially designates the initial set circuits 43 and 44 and the sub mark control circuit 52 to a settable state. The display section designated as the settable state is clearly displayed in the flashing state, and the pulse signal Pa generated by the operation of the button Ba is transmitted via the AND gate 45 opened by the mode selection signal Sts. By supplying it, an arbitrary display state can be set.

In this case, set the initial NK and serve mark on the right court, and set the initial NK and serve mark on the left court.
To set the TN, first, by sending the set signal selection circuit 52 one step by pressing the button Bc, the set selection signal _E1 is output, and the initial set circuit 43 selects the third signal in FIG.
The character display segment 5a of the display section 5 (initial display section on the right court) is selected and enters a flashing state. In this state, the button
When you operate Ba, the alphabets are displayed in order in the character display segment 5a, so when the letter N you want to set is displayed, press the button.
By canceling the operation of Ba and operating the button Bc to advance the set signal selection circuit 54 by one more step, the initial setting to the character display segment 5a is completed, and at the same time, the set signal selection circuit 54 selects the set selection signal _E2. is output and the next character display segment 5b is set to a settable state, so operate button Ba again and press the initial K.
Set.

Thereafter, in the same manner, when the set selection signals E ₃ and E ₄ are selected, the initial TN is set in the character display segments 6a and 6b of the fourth display 6 (initial display section on the left court) in FIG. You can.

Furthermore, when the set selection signal Ss is output by operating the Bc button, the serve mark control circuit 52 is designated, and in this state, by operating the button Ba, serve marks 3c and 4c shown in FIG. 1 are displayed alternately. Therefore, when the serve mark 3c is displayed as shown in Figure 3, press the button Ba.
The series of set operations is completed by canceling the operation and returning the set signal selection circuit 54 to the neutral terminal N by operating the button Bc.

This set state is shown in FIG. 3, and preparations for starting the tennis game are now complete.

Next, the progress of a match using the tennis counter described above will be explained.

First, the umpire goes up to the umpire table with the electronic watch 1 on which the initial and serve position for each court has been set by the setting operation, and checks the actual court position and the court mark 10 and referee mark 11 displayed on the digital display device 2. Align and prepare. In this state, the positions of each opponent on the actual court and the initial and serve positions set on each court on the digital display device 2 should correspond to each other, so after confirming this, declare the start of the match. At the same time, the button Bd is operated once to advance the function selection circuit 24, thereby switching to the tennis game mode. From then on, button Ba corresponding to each court displayed on the digital display device 2 is the count button for the right court, button Bb is the count button for the left court, and button Bb is the count button for the left court.
When it is confirmed that the value of Bc set by the count buttons Ba and Bb is correct, the game progresses by using a write button to write this as official data and counting the points of each opponent. I can do it. In this embodiment, if the opponent on the right court has scored a point but accidentally operates the count button Bb on the left court side, an error will be displayed in the display that was set before operating the write button Bc. After confirming this, by operating the count button Ba on the right court again, you can erase the number on the left court and reset the correct number on the right court.

The details of the tennis game operation will be explained below with reference to FIGS. 4, 5, and 6. When the function selection circuit 24 in FIG. 4 selects the tennis game mode terminal TG, a mode selection signal Stg is output, and a mark GM indicating the tennis game mode is displayed on the mark display section 9 as shown in FIG. . Furthermore, the fourth
In the figure, the mode selection signal Stg is OR gate 31
The operation button exchange circuit 30 is set to the operating state via the AND gate 35 is opened. And as a condition at the start of the game, the operation button exchange circuit 30
Since the control terminal DC is set to logic "D," the A button operation pulse signal Pa input to the input terminal I ₁ is output to the output terminal O ₁ , and the B button operation input to the input terminal I ₂ is output to the output terminal O 1. Output terminal for pulse signal Pb
It is configured to output to O ₂ , and also monitor circuit 4.
1 and 42 select the outputs of the point counters 32 and 33 and the outputs of the game counters 36 and 37 and supply them to display circuits 47 and 48, respectively.Furthermore, the display exchange circuit 50 receives the input terminal _I1 from the display circuit 47.
Outputs the display signal supplied to output terminal O ₁ ,
The display signal supplied from the display circuit 48 to the input terminal _I2 is outputted to the output terminal _O2 . Therefore, as shown in FIG. 5, the first display section 3 displays information on the point counter 32, the second display section 4 displays information on the point counter 33, and the fifth display section 7 displays information on the game counter 36. The information of the game counter 37 is displayed on the display section 8.

When the match starts from the above state and the opponent's TN takes the first point, when the button Bb is operated, the pulse signal Pb is sent to the operation button exchange circuit 30.
The point count signal is supplied from the _O2 terminal to the point counter 33 to enter the number, and 15 is displayed on the second display section 4. After confirming from this display that the entered number is correct, when the write button Bc is operated, the pulse signal Pc passes through the AND gate _B5 and is supplied to the count enable terminal eE of the point determination circuit 34. Then, the point determination circuit 34 receives a pulse signal.
When Pc is supplied to the CE terminal, a point write signal is supplied to the point counters 32 and 33 to write the set value, and at the same time a series of determination operations are performed. For example, the point counter 32 written just now,
If the information in 33 is determined and the game is successful, a game count signal is output to the output terminal of the winning side, and a reset pulse is output from the Q terminal.
The two point counters 32 and 33 are returned to zero display, and the serve mark control circuit 52 is controlled to change the position of the serve mark, thereby preparing for the next game. If the points of both sides become 40 to 40, the signal is deused, and a signal for displaying advantage marks 3d and 4d from the next point is supplied to the point counters 32 and 33.

In addition, Figure 5 shows that TN has 1 point in the first game,
This shows that NK has won 2 points.

Next, to explain the operation of changing the number when counting points in error, for example,
When a number is set in the point counter 32 by operating the Ba button, if the button Bb is operated again without operating the number button Bc, the operation button exchange circuit 30 is
The point count signal from _O2 changes the number by setting the correct number in the point counter 33 and at the same time controlling the enter clear terminal EC of the point counter 32 to clear information set by mistake. I can do it. That is, in this embodiment, since the point count signal from the operation button exchange circuit 30 is supplied complementary to the input terminal I and the enter clear terminal EC of the two point counters 32 and 33, the button Ba By pressing Bb and Bb again, any set number can be changed, and only the number set by the button operation immediately before operating the number button Bc is written to each counter as point information.

Next, the game count and set count operations will be explained. The game count signal output from the point determination circuit 34 is transmitted to each game counter 3.
6 and 37, and the game information counted respectively is always determined by the game determination circuit 38. Then, each time the total number of games becomes an odd number, the logic state of the coat change signal Sdc output to the switching signal terminal DC is inverted, thereby causing the operation button exchange circuit 30 and the display exchange circuit 50.
Switching is performed. Also, when detecting the end of a set, for example, if it is detected that the information on the game counter 36 is 6 games or more and is 2 games more than the information on the other game counter 37, the output terminal of the winning side of the set, that is, the output terminal By outputting a set count signal to _Q1 , writing winning set number information to the set storage section 39b constituting the set counter 39, and further generating a transfer command signal to the Q terminal, each game counter 36, 37 and each set are Controls counters 39 and 40, and controls each game counter 3
The count information of 6 and 37 is transferred to the corresponding set counters 39 and 40, respectively, and written in the corresponding memories of the score storage sections 39a and 40a.
By this transfer operation, the game counters 36, 37
returns to the zero display state and becomes ready for the next set.

FIG. 6 shows a display state in which a court change is performed by the game counting operation.

That is, in FIG. 4, when the opponent NK wins one game first, a reset signal is output from the terminal Q of the point determination circuit 34, so that the point counters 32 and 33 return to the zero display state, and at the same time, the serve mark control circuit 52,
At the same time as switching to the serve mark opponent TN, a game count signal is supplied from the output terminal _Q1 to the game counter 36, and as a result, the content of the game counter 36 becomes 1 and the content of the game counter 37 becomes 0, so the total number of games is When the game determination circuit 38 detects that SDC is 1, that is, an odd number, it inverts the logic of the court change signal Sdc to "1". As a result, the operation button exchange circuit 30 and the display exchange circuit 50
As shown in FIG. 6, the first display section 3 and the second display section 4 display zero, the third display section 5 displays the initial TN, and the fourth display section 6 displays the initial value.
NK, serve mark 3c, and 6th display section 8.
The number of games won by NK first (1) is displayed, a court change is performed, and the operation buttons also correspond to each court: Ba is the TN score button, and Bb is the NK score button.
This is the score button.

Therefore, the umpire moves the opponent to the court position displayed on the display 2, then starts the second game with TN as the server according to the serve mark 3c, and if TN scores, he operates button Ba. The game can be progressed by writing on the first display section 3, and when NK scores a point, writing on the second display section 4 by operating button Bb.

Next, the operation when the set is established will be explained.

Assume that the game count operation has progressed and 10 games have been completed. If the opponent's NK wins 6 games and TN wins 4 games, the content of the game counter 36 in FIG. 4 is 6 and the content of the game counter 37 is 4, so the game judgment circuit 3
8 supplies a set count signal from the output terminal _Q1 to the set counter 39 in accordance with the judgment condition of winning 6 games first based on the difference between 2 games, and stores the set count signal in the set storage section 39.
The number of wins, 1, is written to b, a transfer command signal is output from terminal Q, and the contents of game counters 36 and 37 are transferred to set counters 39 and 40. As a result, 6 and 4 are written in the first set memories of the score storage units 39a and 40a of the set counters 39 and 40, respectively, and the game counter 3
6 and 37 return to zero display, and the series of operations ends.

Next, the operation of establishing a set by tie-break will be explained. The number of game wins between opponents NK and TN is
If the score becomes 6 to 6 with no difference between the two games, the umpire declares a tie-break and operates button Bd once to set the function selection circuit 24 to tie-break mode. As a result, the tie-break mode pin TB receives the tie-break mode signal.
Stb is generated, controls the point counters 32, 33, point judgment circuit 34, and game judgment circuit 38, sets the count output mode of each point counter 32, 33 to 1 point unit of 1, 2, 3..., and points The determination condition of the determination circuit 34 is set to determine whether the game is established when 6 points with a difference of 2 points are obtained first, and the determination condition of the game determination circuit 38 is also set when the game difference between the game counters 36 and 37 reaches 1. It is possible to establish the set by determining that the condition is established and outputting a series of operation signals.

When the set is established by the tie-break, the function selection circuit 24 is switched to the tennis game mode terminal again by operating button Bd three times.
Set to TG and start the next set of games.

As described above, when the scheduled number of sets is completed by operating the count buttons Ba, Bb and the write button Bc as the game progresses, the score storage section 39a of the set counter 39 stores the number of opponents.
The number of winning games for each set of NK is stored, and the number of winning sets is stored in the set storage section 39b.
Furthermore, the score storage section 40 of the set counter 40
The number of winning games and the number of winning sets of the opponent TN are stored in the set storage section 40b and the number of winning games of the opponent TN, respectively, and the match ends.

Next, the set monitor operation for displaying each score stored in the set counters 39 and 40 on the digital display section 2 will be explained.

When the match is over, operate button Bd twice to set the function selection circuit 24 to the monitor terminal.
Set to SM. As a result, the set monitor mode signal Ssm is output, and this signal is sent to the set counter 3.
9 and 40 are set to the monitor call mode, and the monitor circuits 41 and 42 are controlled to switch the display.

FIG. 7 shows an example of the display state in the above-mentioned set monitor mode, and the Japanese characters segments 3a and 4a of the first display section 3 and the second display section 4 respectively display the opponents NK and TN's winning set numbers 3 and 2 are prominently displayed in a flashing display mode, and the currently monitored set number 1 is displayed in Japanese segments 3b and 4b.

Further, the fifth display section 7 and the sixth display section 8 display the number of winning games of NK and TN in the sets numbered in the Japanese characters segments 3b and 4b, respectively. In other words, the display state shown in Figure 7 shows that the outcome in a 5-set match is 3 to 2.
NK won, and the score of the first set was 6 to 4, indicating that NK won.

Furthermore, if you operate button Bc from the above state,
The set counter 39,
The stored information in each of the 40 score storage units 39a and 40a is sequentially called out to the monitor circuits 41 and 42, and as a result, the Japanese character segment 3 of the digital display unit 2
Set numbers 2, 3, 4, and 5 are sequentially called up in the segments 3b and 4b, and the set numbers displayed in the Japanese character segments 3b and 4b are displayed in the fifth display section 7 and the sixth display section 8. The corresponding scores will be displayed in order.

Therefore, the umpire can notify the opponents of the outcome and each score by calling up the set monitor mode immediately after declaring the end of the match.

When the function mode as a tennis game counter is completed by the series of operations described above, it is possible to return to the clock function mode by continuously operating the button Bd as described above.

Furthermore, the configuration of the present invention is not limited to the counting function of the tennis game shown in the embodiment, but is also applicable to table tennis,
It is possible to use all games that involve court changes such as badminton and volleyball, and by changing the court change conditions and game establishment conditions for each game,
It becomes possible to perform the counting function of a plurality of games with one configuration.

As described above, according to the present invention, when counting the score of a game that involves a court change such as tennis or badminton, the display position of the display unit is changed according to the court change of the opponent.
The position of the opponent can always be matched with the position of the count display section, making it possible to easily perform complicated score counting.

Furthermore, as shown in the example, if the function of the counting member is replaced at the same time as the display part, there is no need to worry about operational errors interfering with the progress of the game, and even amateurs like Sunday players can act as referees. Now I can concentrate on the game and enjoy it.

[Brief explanation of the drawing]

FIG. 1 is an external view of an electronic timepiece showing an embodiment of the present invention, and FIGS. 2, 3, 5, 6, and 7 are each display state of the electronic timepiece shown in FIG. 1. FIG. 4 is a block diagram showing the configuration of the electronic timepiece shown in FIG. 1. 1...Electronic clock, 2...Digital display device, 2
0... Clock circuit, 21... Tennis counter circuit.

Claims (1)

[Claims] 1. Two externally operated counting members corresponding to the opponents of the game, a pair of point storage means for inputting the operation signals of each counting member and storing the points of each opponent, and storing the initials of each opponent. In a counter device equipped with a display device that displays information from a pair of initial storage means for each player, a point storage means corresponding to each opponent, and a tennis score storage means as a set on the left and right sides of the display screen, A change signal generation means for generating a signal, and an operation member exchange circuit for exchanging functions of a display exchange circuit and the counting member are provided, and the display exchange circuit and the operation member exchange circuit are controlled by the coat change signal. A game counter device characterized in that the information of each player dividedly displayed on the display device is exchanged left and right, and at the same time, the function of the counting member is exchanged left and right.