JPH047234B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention secures a predetermined winning right by the entry of a pachinko ball into a predetermined winning opening, and when the winning right is secured, the predetermined winning opening is When a pachinko ball flies into a different winning hole, the predetermined winning right is exercised, and when a pachinko ball flies into a winning hole different from the predetermined winning hole without securing the predetermined winning right, the above-mentioned This invention relates to a pachinko machine that exercises a right with a lower probability of winning than a predetermined winning right.

(Prior Art) Some pachinko machines increase the winning probability of a winning device when a pachinko ball flies into a predetermined winning opening.

However, this type of pachinko machine only increases the probability of winning by a predetermined amount each time a pachinko ball enters the winning hole, so players living in today's increasingly complex and sophisticated world find it difficult to get used to pachinko games. As a result, the game became monotonous, and the player's desire to play tended to decline.

(Object of the Invention) The present invention was made in view of the above-mentioned circumstances, and its purpose is to provide a pachinko machine that is rich in game variety and stimulates the player's desire to play.

(Structure of the Invention) In order to achieve such an object, the present invention includes a solenoid that increases the probability of winning a prize, and a first solenoid that is turned on when a pachinko ball enters a winning opening for securing rights. a right securing circuit that sets the winning probability increasing state to a drive preparation state, and the right securing circuit is in an on state and is turned on by a pachinko ball flying into a winning opening used for right line that is different from the winning opening for securing rights. When the solenoid is driven to a first winning probability increasing state, and when the right securing circuit is in the OFF state and a pachinko ball flies into the winning opening used for right-handling and the solenoid is turned on, the solenoid is activated. and a rights exercise circuit that drives the winning probability to enter a second winning probability increasing state with a lower probability than the first winning probability increasing state.

From the above-mentioned configuration, even if a pachinko ball flies into the winning hole used for the right line, it is possible to obtain different winning probability increasing states depending on whether the right is secured, and the player can enjoy a pachinko game with a rich variety of games. In addition to being able to obtain the above-mentioned winning probability state depending on the player's skill, the player becomes motivated to play.

(Example) Hereinafter, an example of the present invention will be described based on the drawings.

1 to 4, 1 is a winning device according to the present invention, and this winning device 1 is composed of a first winning device 2 and a second winning device 3, and the first winning device 2, the second winning device 2, 3 are attached to the game board surface 4 in a vertical relationship.

The first prize winning device 2 is formed of a casing 5 made of plastic, and the upper part thereof is provided with a top prize opening 6 and left and right top shoulder diving prize openings 7, 8, and the lower part thereof is provided with a left and right diving prize opening 9. , 10 are provided. The top prize opening 6, the left and right top shoulder diving prize openings 7, 8
is connected to a normal winning ball detection mechanism (not shown), and when a pachinko ball enters both of the winning holes 6, 7, and 8, the winning ball detection mechanism pays out a predetermined number of winning balls. It's getting old. The left and right diving prize openings 9 and 10 have their discharge ports opening downward, and when a pachinko ball enters the left and right diving prize openings 9 and 10, the pachinko ball is sent to the second winning device 3.
You will be guided towards.

A winning hole 11 is opened in the center of the casing 5 of the first winning device 2, that is, between the top winning hole 6, the left and right top diving winning holes 7, 8, and the left and right diving winning holes 9, 10, Winning hole 1 corresponding to that winning hole 11
A center gate 12 is supported at both ends of one opening edge so as to be openable and closable. This center gate 12
consists of a guide plate portion 12a and side plate portions 12b, 12b. The guide plate part 12a has both lower ends pivoted to the opening edge of the winning opening 11, and the guide plate part 12a
a opens and closes the prize opening 11 using both ends of the lower end of the guide plate portion 12a as fulcrums in the direction in which the upper end approaches and moves away from the game board surface 4. The side plate portions 12b are erected at both ends of the guide plate portion 12a, and due to the weight of the side plate portions 12b, the guide plate portion 12a
is always biased in the open direction. That is, this side plate part 12b has a fan shape, and one end edge thereof is fixed to both ends of the guide plate part 12a, and the other end edge part extends in a direction away from the front surface of the casing 5. Therefore, the guide plate part 12a opens until the other end edge of each side plate part 12b comes into contact with the front surface of the casing 5, and each side plate part 12b
The angle between the other end edge and one end edge is the guide plate part 1.
Determine the opening degree of 2a. And each side plate part 1
The other end edge of 2b is the casing 5.
When it comes into contact with the front of the left and right diving prize openings 9,
10, and each side plate portion 12b at that time
and an upright plate 13 erected on the front of the casing 5,
13 form passages 13a, 13a that increase the probability of pachinko balls entering the left and right diving prize holes 9,10. And this center gate 12 is
As shown in FIG. 3, opening and closing are controlled by a solenoid 15 via a center gate control lever mechanism 14. The prize opening 11 that opens and closes the center gate 12 has a built-in counting switch 16 that counts the number of pachinko balls that have landed.

The second prize winning device 3 is formed of a casing 717 made of plastic, and a saucer 18 is provided on the upper part of the casing 717 to receive the pachinko balls that have entered the left and right prize winning holes 9 and 10. The saucer 18
Wide pachinko ball passage 1 to the front of the casing 17
The pachinko balls received in the tray 18 roll through the pachinko ball passage 19 toward the front of the casing 17.
On the front surface of the casing 17, partitions 20 and 21 are erected below the opening of the pachinko ball passage 19, and the space between the partitions 20 and 21 is a winning opening for securing rights, and this winning opening 22 for securing rights. has a built-in rights securing switch 23. On both sides of the winning opening 22 for securing rights, winning openings 24 and 25 are provided as passageways through which a predetermined number of prize balls are paid out, and on the front surface of the casing 17 above the winning opening 22 for securing rights, An indicator lamp 26 is provided.

On the front side of the casing 17, there are a winning opening 22 for securing rights, and winning openings 27 and 28 on both sides of the winning openings 24 and 25 for securing rights. An exercise switch 29 is provided. 30 and 31 are plaques,
32 is a right exercise indicator lamp.

FIG. 4 shows the control circuit of the solenoid 15, where 33, 34, and 35 are flip-flop circuits;
36 is a clock oscillation circuit, 37 is a 12-bit binary counter circuit, 38, 39, 40 are reset circuits, 41 is a lamp display blinking circuit, 42 is a solenoid drive circuit, 43 is a right securing display lamp drive circuit, 44 is a right exercise display A lamp drive circuit, 45 a 10 count storage circuit, 46 an electronic sound generation circuit, and 47 a sound amplification circuit. Of these, the flip-flop circuit 33 and the flip-flop circuit 34 roughly constitute the right securing circuit, and the flip-flop circuit 35 and the reset circuits 38, 39, 4
0, clock oscillation circuit 36, 12-bit binary counter circuit 37 and solenoid drive circuit 42
roughly constitutes the rights enforcement circuit.

The configuration and function of each of these circuits will be explained below.

The flip-flop circuit 33 has an input terminal C,
power supply potential terminal D, ground terminal S, output terminal Q,
Q and a reset terminal R. The power supply voltage Vcc and the rights securing switch 23 are connected to the input terminal C via a NAND gate 49, and the power supply voltage
Vcc is considered to be on the high potential side. When the rights securing switch 23 is in the open state as shown in FIG.
Output terminal Q outputs L, and when the right securing switch 23 is closed, one clock is input to input terminal C, and H is output to output terminal Q. Output terminals are not used here.

The flip-flop circuit 34 has input terminals D and C.
, a ground terminal S, an output terminal Q, and a reset terminal R. The output from the output terminal Q of the flip-flop circuit 33 is input to the input terminal D, and the input terminal C is connected to the rights exercise switch 29 via an AND circuit 50 and a NAND gate 51. The right exercise switch 29
As shown in the figure, in the open state, the AND circuit 50 outputs L, and when the right exercise switch 29 is closed due to the landing of a pachinko ball, the AND circuit 50 outputs H. The output of this AND circuit 50 is input to the reset terminal R of the flip-flop circuit 33 via the OR circuit 52, and when the AND circuit 50 outputs H, the flip-flop circuit 33 is reset and its output terminal Q is set to the L state. becomes. One clock is input to the input terminal C of the flip-flop circuit 34 when the rights exercise switch 29 is closed, and the output terminal Q of the flip-flop circuit 34 is connected to the input terminal D by this one clock input. L
When is input, it outputs L as it is,
When H is input to the input terminal D, H
Output. The output terminal outputs an output signal opposite to that of the output terminal Q.

The flip-flop circuit 35 includes two NOR circuits 5
The output of the AND circuit 50 is input to one input terminal of the NOR circuit 53, and the output of the NOR circuit 53 is input to one input terminal of the NOR circuit 54. The output is input to the other input terminal of the NOR circuit 53, and the output of an OR circuit 55, which will be described later, is input to the other input terminal of the NOR circuit 54. This flip-flop circuit 53 outputs L when L is input to the NOR circuit 53 and H is input to the NOR circuit 54, and when H is input to the NOR circuit 53 and L is input to the NOR circuit 54. , outputs H and both NOR circuits 53, 5
It has a function of outputting the previous state when L is input to 4.

The 12-bit binary counter circuit 37 has an input terminal C, output terminals _Q1 to _Q12 , and a reset terminal R. Input terminal C is connected to a clock oscillation circuit 36 that generates a clock signal as shown in FIG.
and each of the output terminals Q ₁ to _{Q 12} is configured to generate a rectangular signal as shown in FIG. The output terminal _Q1 has a period twice that of the clock signal, and has the function of outputting when the first clock signal is input. Output terminal Q ₂ is
It has a period four times that of the clock signal, and has a function of outputting when the second clock signal is input. The output terminal _Q3 has a period eight times as long as the period of the clock signal, and has the function of outputting when the fourth clock signal is input. The output terminal _Q4 has a period 16 times the period of the clock signal, and has a function of outputting when the eighth clock signal is input. Output terminal _Q5 has a period 32 times the period of the clock signal, and outputs when the 16th clock signal is input. Output terminal _Q6 has a cycle that is 64 times the cycle of the clock signal, and outputs when the 32nd clock signal is input. Output terminal _Q7 has a cycle that is 128 times the cycle of the clock signal, and outputs when the 64th clock signal is input. Output terminal _Q8 is
The period is 256 times the period of the clock signal, and the 128th
Outputs when the th clock signal is input. Output terminal _Q9 has a period 512 times that of the clock signal, and outputs when the 256th clock signal is input. The output terminal _Q10 has a period 1024 times the period of the clock signal, and outputs when the 512th clock signal is input. Output terminal
_Q11 has a cycle that is 2048 times the cycle of the clock signal, and outputs when the 1024th clock signal is input. The output terminal _Q12 has a period 4096 times the period of the clock signal, and outputs when the 2048th clock signal is input.

The reset circuit 38 consists of an AND circuit 56,
The outputs of the output terminals Q ₄ and Q ₆ of the 12-bit binary counter circuit 37 are input to the AND circuit 56 . The output of this AND circuit 56 is input to an OR circuit 55. In this OR circuit 55,
In addition, the output from the output terminal Q of the flip-flop circuit 34 is input as well as the output from the power supply reset circuit 57, and the output from the OR circuit 55 is input to the output terminal Q of the flip-flop circuit 34. NOR circuit 54 as a component
is being input to another input terminal. Here, the power supply reset circuit 57 is outputting L.

The solenoid drive circuit 42 is an OR circuit 5
8, a resistor 59, a transistor 60, etc., and is connected to the solenoid 15 via each of these components 58, 59, and 60. The output of the flip-flop circuit 35 and the output from the output terminal _Q7 of the 12-bit binary counter circuit 37 are input to the OR circuit 58.

The reset circuit 39 has a NOR circuit 61, an AND circuit 62, and an OR circuit 63. The output of the flip-flop circuit 35 and the output from the output terminal Q of the flip-flop circuit 34 are input to the NOR circuit 61. The AND circuit 62 has
The output of the NOR circuit 61 and the output from the output terminal _Q6 of the 12-bit binary counter circuit 37 are input. The output of the AND circuit 62 and the output of the AND circuit 50 are input to the OR circuit 63, and the output of the OR circuit 63 is input to the reset terminal R of the 12-bit binary counter circuit 37. and the open state of the rights exercise switch 29;
That is, when the AND circuit 50 is outputting L and the NOR circuit 61 is outputting H, the 12-bit binary counter circuit 3
The output signal from output terminal Q ₆ of 7 is AND circuit 6
2. The signal is inputted to the reset terminal R of the 12-bit binary counter circuit 37 via the OR circuit 63, and the reset/release of the 12-bit binary counter circuit 37 is repeated by the output signal. More specifically, when the output signal from the output terminal _Q6 is in the L state, the reset of the 12-bit binary counter circuit 37 is released, and when the output signal becomes the H state (the first H state), the 12-bit binary counter circuit 37 is reset. (at rising edge) The 12-bit binary counter circuit 37 is reset. 12-bit binary counter circuit 37
is reset, its output terminals Q ₁ to Q ₁₂ go low.
As a result, L is output from the OR circuit 63, the reset of the 12-bit binary counter circuit 37 is released, and from the time of release of this reset, the output terminals Q ₁ to 1 of the 12-bit binary counter circuit 37 are newly output. Q ₁₂ starts outputting each rectangular signal.
Therefore, the output terminals Q ₁ to _{Q 12} of this 12-bit binary counter circuit 37 are in the L state.
When the AND circuit 50 is outputting L and the NOR circuit 61 is outputting L, the OR circuit 63 will output L, and the 12-bit binary counter circuit 37 will be reset. In the released state, each of the output terminals Q ₁ to _{Q 12} outputs a rectangular signal shown in FIGS. 5 and 6, respectively. When the right exercise switch 29 is closed, the OR circuit 63 outputs H, and the 12-bit binary counter circuit 37 is reset regardless of the output signal from the AND circuit 62. As a result, the 12-bit binary counter circuit 37 determines the operation start time for starting the first or second winning probability increasing state, that is, the reference time.

The reset circuit 40 includes an AND circuit 64, an inverter element 65, and a NOR gate 66. The outputs of the output terminals Q ₉ and Q ₁₂ of the 12-bit binary counter circuit 37 are input to the AND circuit 64 . The output terminal of the AND circuit 64 is connected to one input terminal of a NOR gate 66 via an inverter element 65, and the other input terminal of the NOR gate 66 is grounded via a capacitor. The ground side of the other input terminal of this NOR gate 66 is in the L state.

The output of the NOR gate 66 is input to an OR circuit 67. The OR circuit 57 also includes an output from the power supply reset circuit 57 and an AND circuit 68 (described later).
This OR circuit 6
The output of the flip-flop circuit 34 is input to the reset terminal of the flip-flop circuit 34. And this OR circuit 6
When a high level is output from the flip-flop circuit 34, the flip-flop circuit 34 is reset, and the output from its output terminal Q becomes L, and the output from its output terminal becomes H.

The lamp display blinking circuit 41 includes an AND circuit 69,
It has 70. The outputs from the output terminals Q ₄ and Q ₅ of the 12-bit binary counter circuit 37 are input to the AND circuit 69 , and the outputs from the output terminal Q 4 of the flip-flop circuit 34 are input to the AND circuit 70 .
Output from and 12-bit binary counter circuit 37
The output from output terminal _Q4 is input.

The rights securing display lamp drive circuit 43 includes an AND circuit 71, a resistor 72, and a transistor 73. The output from the output terminal Q of the flip-flop circuit 33 and the output from the AND circuit 69 are input to the AND circuit 71. 26.

The right exercise indicator lamp drive circuit 44 includes an OR circuit 74, a resistor 75, and a transistor 76. The output from the flip-flop circuit 35 and the output from the AND circuit 70 are input to the OR circuit 74, and the output from the OR circuit 74 is connected to the resistor 75.
and is inputted to the right exercise indicator lamp 32 via the transistor 76.

The 10 count storage circuit 45 has a 4-bit binary counter circuit 77 and an AND circuit 68.
The 4-bit binary counter circuit 77 has a reset terminal R, an input terminal C, a power supply potential terminal CE,
It has output terminals _Q1 to _Q4 . The output from the output terminal of the flip-flop circuit 34 is input to this reset terminal R, and when H is input to this reset terminal R, this 4-bit binary counter circuit 77 is reset and each output terminal Q ₁ to _Q4 are in the L state. The input terminal C of the 4-bit binary counter circuit 77 is connected to the input terminal of a NAND gate 78, and the input terminal of the NAND gate 78 is connected to the count switch 16. This count switch 16 is closed every time a pachinko ball wins.
The clock is converted to a 4-bit binary counter circuit 77.
When the clock is input to the input terminal C of the clock and L is input to the reset terminal R, the output terminal _Q1
~ _Q4 outputs H. That is, at first,
Output terminals Q ₁ to Q ₄ all output L, and when one clock is input, only output terminal Q ₁ outputs H, and when two clocks are input, output terminal Q Only _Q2 outputs H, and when three clocks are input, output terminals _Q1 and _Q2 output H,
When 4 clocks are input, only output terminal Q ₃ outputs H; when 5 clocks are input, output terminals Q ₁ and Q ₃ output H, and 6 clocks output H. When input, output terminals Q ₂ and Q ₃ become H.
When 7 clocks are input, output terminals Q ₁ , Q ₂ , and Q ₃ output H, and when 8 clocks are input, only output terminal Q ₄ outputs H. Then, when 9 clocks are input, the output terminal
Q ₁ and Q ₄ output H, and when 10 clocks are input, output terminals Q ₂ and Q ₄ output H.
The outputs from the output terminals Q ₂ and Q ₄ of the 4-bit binary counter circuit 77 are input to the AND circuit 68, and the output from the AND circuit 68 is input to the OR circuit 67. Therefore, when 10 clocks are input to the input terminal C of the 4-bit binary counter circuit 77, the output terminals Q ₂ and Q ₄ output H, so the AND circuit 68 outputs H, and the OR circuit 67 receives the H output and outputs H, and the reset terminal R of the flip-flop circuit 34 becomes H and is set.

The output of the NOR circuit 61 and the output from the output terminal _Q3 of the 12-bit binary counter circuit 37 are input to the electronic sound generation circuit 46, and the output from the electronic sound generation circuit 46 is input to the audio amplification circuit 47. has been entered. 78 is a speaker.

Next, the effect will be explained separately for each case.

(i) Rights exercise switch 29, rights securing switch 2
3. When all the count switches 16 are open, the output terminal Q of the flip-flop circuit 33 outputs L, and the output terminals Q ₁ to _{Q 4} of the 4-bit binary counter circuit 77 output L.

When the power supply voltage Vcc is turned on, the 12-bit binary counter circuit 37 starts operating in the reset release state, and since the right exercise switch 29 is at H level in the open state, the AND circuit 50
outputs L. On the other hand, since the L output from the output terminal Q of the flip-flop circuit 33 is input to the input terminal D of the flip-flop circuit 34, the output terminal Q of the flip-flop circuit 34 is
outputs L. Output signals (L signal from output terminal Q 6 ) are output from output terminals Q ₄ and _{Q 6 of} the 12-bit binary counter circuit 37 , and both output signals are sent to the flip-flop circuit 35 via an AND circuit 56 and an OR circuit 55 . At this time, the L output from the AND circuit 50 is input to the NOR circuit 53 as a component of the flip-flop circuit 35, and the L output is input to the NOR circuit 54. Since the input signal is L, the flip-flop circuit 35 always outputs L. Noah circuit 6
1 receives the L output from the flip-flop circuit 35 and the L output from the output terminal Q of the flip-flop circuit 34, and therefore the NOR circuit 61 outputs an H signal. The AND circuit 62 has the H output from the NOR circuit 61 and the 12
Output terminal of bit binary counter circuit 37
The AND circuit 62 outputs the same output signal as the output signal from _the output terminal _Q6 . The L output from the AND circuit 50 and the output signal from the AND circuit 62 are input to the OR circuit 63.
3 outputs the same output signal as the output signal from the AND circuit 62, and the output signal is input to the reset terminal R of the 12-bit binary counter circuit 37. Therefore, as a result, the output signal from the output terminal _Q6 of the 12-bit binary counter circuit 37 is input to its reset terminal R, and the 12-bit binary counter circuit 37
is reset in response to the output signal, that is, when the output signal goes to the H state, and is released from reset when the output signal goes to the L state. Therefore, each output terminal of the 12-bit binary counter circuit 37 starts outputting from the beginning every time the reset is released.
Output terminal of 12-bit binary counter circuit 37
_Q7 to _Q12 are in the L state without outputting a rectangular signal.

Therefore, the L output from the output terminal _Q7 of the 12-bit binary counter circuit 37 and the L output from the flip-flop circuit 35 are input to the OR circuit 58, and the OR circuit 58 outputs L. . The solenoid 15 is not driven by the L output from the OR circuit 58, and the center gate is in a closed state.

The flip-flop circuit 3 is included in the AND circuit 71.
Since the L output from the output terminal Q of No. 3 is input, the AND circuit 71 outputs L. With the L output from this AND circuit 71,
The rights securing indicator lamp 26 is off.

The flip-flop circuit 3 is included in the AND circuit 70.
The L output from the output terminal Q of No. 4 is input, and the AND circuit 70 outputs L. The L output from the flip-flop circuit 35 and the L output from the AND circuit 70 are input to the OR circuit 74, and the OR circuit 74 outputs L. The right exercise indicator lamp 32 is turned off by the L output of the OR circuit 74.

(ii) Output terminal Q of flip-flop circuit 33 is L
is being output and the right exercise switch 29 is closed.

When a pachinko ball enters the winning hole 27, the right exercise switch 29 is temporarily closed by the pachinko ball, and accordingly, the AND circuit 50 outputs a signal from L to H.
The H output from the AND circuit 50 is input to the OR circuit 63, and the OR circuit 63 outputs H regardless of the output signal from the AND circuit 62.
Its H output is 12-bit binary counter circuit 3
7, and the 12-bit binary counter circuit 37 is reset. As a result, the reference time (start reference time) for driving the solenoid 15 is determined. That is, when the right exercise switch 29 is closed, the H output from the AND circuit 50 is input to the NOR circuit 53, and at the same time, since the 12-bit binary counter circuit 37 has been reset as described above, the OR The circuit 55 inputs L to the NOR circuit 54. Therefore, the flip-flip circuit 35 outputs an H level, and the OR circuit 58 receives its H output and the L output from the output terminal _Q7 of the 12-bit binary counter circuit 37 in the reset state.
As a result, the OR circuit 58 starts outputting H, and the driving of the solenoid 15 starts.

When the pachinko ball leaves the right exercise switch 29 and the right exercise switch 29 returns to the open state, the AND circuit 50 outputs an L signal from H, and the L output is input to an OR circuit 63. Upon receiving the input, the OR circuit 63 inputs the L output to the reset terminal R of the 12-bit binary counter circuit 37, and releases the reset state of the 12-bit binary counter circuit 37.

When the reset state of the 12-bit binary counter circuit 37 is released, its output terminals Q ₄ and Q ₅
outputs the rectangular signals shown in Figures 5 and 7,
The output is input to an AND circuit 56. In response to this, the AND circuit 56 outputs a rectangular signal shown in FIG. 7, and its output is input to the OR circuit 55. At this time, since all other input signals input to the OR circuit 55 are L, the OR circuit 55 outputs the same rectangular signal as the AND circuit 56, and the output signal is output from the NOR circuit 54.
is input. At this time, the right exercise switch 2
9 returns to the open state, L is input to the NOR circuit 53. Therefore, the flip-flop circuit 35 receives only L for 0.5 seconds after starting to receive the rectangular signal from the OR circuit 55.
5 outputs the previous state, ie, H, during that time. During this period, the output signal from the output terminal _Q7 of the 12-bit binary counter circuit 37 is still low.
Therefore, the OR circuit 58 outputs H
continues to be output, and the solenoid 15 continues to be driven.

At this time, the H output from the flip-flop circuit 35 is also input to the NOR circuit 61. NOR circuit 61 receives the H output and the L output from output terminal Q of flip-flop circuit 34 and outputs L, and the L output is input to AND circuit 62. The AND circuit 62 outputs L and inputs the L output to the OR circuit 63, and the OR circuit 63 outputs 12
The L output is input to the reset terminal R of the bit binary counter circuit 37. Therefore, while the flip-flop circuit 35 is outputting H,
The reset of the 12-bit binary counter circuit 37 has been released.

When 0.5 seconds have passed since the right exercise switch 29 changed from the closed state to the open state, that is,
When 0.5 seconds have elapsed since the rectangular signal from the OR circuit 55 was input to the NOR circuit 54, the rectangular signal inputs an H state to the NOR circuit 54, and since L is input to the NOR circuit 53, the flip-flop circuit 35 outputs L. Therefore,
While L is input to the NOR circuit 53, the flip-flop circuit 35 continues to output L even if the output signal from the OR circuit 55 input to the NOR circuit 54 changes. The L output from the flip-flop circuit 35 is input to a NOR circuit 61, and the NOR circuit 61 outputs an H level. Therefore, the AND circuit 62 receives its H output and the rectangular signal from the output terminal _Q6 of the 12-bit binary counter circuit 37, and as described in (i) above, the 12-bit binary counter circuit 37, the reset/reset release is repeated according to the output signal from the output terminal _Q6 , and the 12
Output terminal of bit binary counter circuit 37
Q ₇ to Q ₁₂ are in the L state. Therefore, the L output from the flip-flop circuit 35 and the L output from the output terminal _Q7 of the 12-bit binary counter circuit 37 are input to the OR circuit 58, and the OR circuit 58 outputs L. This L output causes the solenoid 15 to stop driving and the center gate 12 to be in the closed state. That is, solenoid 1
5 is driven once for 0.5 seconds as shown in FIG. 7, the center gate 12 is opened and closed once, and the second winning probability increasing state is exercised.

Since the output terminal Q of the flip-flop circuit 33 continues to output L to the AND circuit 71, the AND circuit 71 outputs L, and the right reservation indicator lamp 26 is turned off.

The L output from the output terminal Q of the flip-flop circuit 34 is input to the AND circuit 70 , and the AND circuit 70 outputs L, and the L output is input to the OR circuit 74 . Further, since the output signal from the flip-flop circuit 35 is input to the OR circuit 74, the OR circuit 74
outputs the same signal as the output signal from the flip-flop circuit 35, and the right exercise lamp indicator lamp 32 lights up when the output signal is in the H state, and goes out when the output signal is in the L state. That is, the right exercise indicator lamp 32 is
Together with the solenoid 15, it lights up while the solenoid 15 is being driven.

(iii) When the output terminals Q ₁ to _{Q 4} of the 4-bit binary counter circuit 77 are in the L state, and the rights securing switch 23 is first closed, and then the rights exercise switch 29 is closed.

When a pachinko ball enters the left and right diving prize openings 9 and 10, the pachinko ball is dropped into the tray 18 of the second prize winning device 3, and from the tray 18 is passed through the pachinko ball path 19 to the second prize winning device 3. You will be guided forward. When the pachinko ball falls from the opening of the pachinko ball passage 19 into the winning holes 24 and 25, a predetermined number of prize balls are paid out and fall into the winning hole 22 for securing rights as usual. When the vehicle enters the vehicle, the rights securing switch 23 is closed.

When the rights securing switch 23 is closed, one clock is input to the input terminal C of the flip-flop circuit 33, and its output terminal Q outputs an H level. The H output is inputted to the AND circuit 71 and also inputted to the input terminal D of the flip-flop circuit 34 and stored in the flip-flop circuit 34. Rectangular signals from the output terminals Q ₄ and Q ₅ of the 12-bit binary counter circuit 37 are input to the AND circuit 69 .
receives both rectangular signals, outputs an output signal, and inputs the output signal to the AND circuit 71. Therefore, the AND circuit 71 outputs the same output signal as the AND circuit 69 to the right securing display lamp 26.
The rights reservation indicator lamp 2 will be output.
6 repeats blinking. This right securing indicator lamp 2
6 blinks, the player knows that the preparation state for the first winning probability increasing state, that is, the right to the first winning probability increasing state has been secured.

The OR circuit 74 includes a flip-flop circuit 3
Since the L output from 5 and the L output from the AND circuit 70 are still being input, the right exercise indicator lamp 32 is off.

Subsequently, as shown in (ii) above, when a pachinko ball flies into the winning hole 27 for the right line, the right exercise switch 29 is temporarily closed, and one clock is input to the input terminal C of the flip-flop circuit 34. As a result, its output terminal Q outputs the H state stored in the flip-flop circuit 34. Therefore, the NOR circuit 61 outputs L, the AND circuit 62 outputs L, and the OR circuit 6
L is input to 3. On the other hand, when the right exercise switch 29 is closed, the AND circuit 50 outputs an H signal from L, and the H output is input to an OR circuit 63. As a result, the OR circuit 63 outputs H, the 12-bit binary counter circuit 37 is reset, and the reference time for driving the solenoid 15 is determined.

When the pachinko ball leaves the right exercise switch 29 and the right exercise switch 29 returns to the open state, the AND circuit 50 outputs an L signal from H, and the L output is input to an OR circuit 63.
The OR circuit 63 outputs L based on the L output from the AND circuit 62 and this L output, and the reset of the 12-bit binary counter circuit 37 continues to be released.

With the release of the reset of the 12-bit binary counter circuit ₃₇ , the _fifth
The rectangular signals shown in FIGS. and 6 are output, and the output terminals Q ₄ and Q ₆ input the output signals to the OR circuit 55 via the AND circuit 56. However, the H output from the output terminal Q of the flip-flop circuit 34 is input to this OR circuit.
The OR circuit 55 outputs H, and this H output is input to the NOR circuit 54. At this time, since the right exercise switch 29 has returned from the closed state to the open state, the AND circuit 50 is inputting L to the NOR circuit 53, and therefore the flip-flop circuit 3
5 outputs L, and inputs the L output to OR circuit 58. A rectangular signal from the output terminal _Q7 of the 12-bit binary counter circuit is input to the OR circuit 58, and the OR circuit 58 outputs the rectangular signal shown in FIG. For this reason, the solenoid
The center gate 12 is driven at 0.8 second intervals and repeatedly opens and closes.

On the other hand, rectangular signals from the output terminals Q ₉ and Q ₁₂ of the 12-bit binary counter circuit 37 are input to the AND circuit 64, and the AND circuit 64 outputs the rectangular signal shown in FIG. This output signal is input to a NOR gate 66 via an inverter element 65, and the NOR gate 66 outputs an inverted rectangular signal of the AND circuit 64, and the output signal from the NOR gate 66 is input to an OR circuit 67. At this time, the power supply reset circuit 57 and the AND circuit 68
This L output is output from the OR circuit 6.
7 is entered. Therefore, the OR circuit 67 outputs the signal shown in FIG. 8, and when that signal first outputs H, H is input to the reset terminal R of the flip-flop circuit 34, and the flip-flop circuit 34 is reset. As a result of the reset, the output from the output terminal Q changes from H to L. The OR circuit 55 inputs the L output, outputs L, and inputs the L output to the NOR circuit 54. However, since L is input to the NOR circuit 53, the flip-flop circuit 35 returns to the previous state. , that is, it outputs L, and this L output and the output terminal Q of the flip-flop circuit 34
The L output from the NOR circuit 61 is input to the NOR circuit 61, and the NOR circuit 61 outputs an H signal. Therefore, the AND circuit 62 receives its H output and the rectangular signal from the output terminal _{Q6 of the 12-bit binary counter circuit 37, and as described in (i) and (ii) above, the AND circuit 62 receives the H output and the rectangular signal from the output terminal Q6} of the 12-bit binary counter circuit 37. The counter circuit 37 has the output terminal Q ₆
Reset and reset release are repeated according to the output signal from the 12-bit binary counter circuit 37, and the output terminals Q ₇ to Q ₁₂ of the 12-bit binary counter circuit 37 are in the L state. Therefore, after 28.8 seconds have elapsed since the reset of the 12-bit binary counter circuit 37 is released, the OR circuit 58 receives the L output from the flip-flop circuit 35 and the 12
Output terminal Q ₇ of bit binary counter circuit 37
The OR circuit 58 outputs L. This L output causes the solenoid 15 to stop driving and the center gate 12 to be in the closed state. That is, as shown in FIG. 8, the solenoid 15 is driven 18 times at 0.8 second intervals, the center gate 12 is opened and closed 18 times, and the first winning probability increasing state is exercised.

While the solenoid 15 is being driven at 0.8 second intervals, the H output from the output terminal Q of the flip-flop circuit 34 and the rectangular signal from the output terminal _Q4 of the 12-bit binary counter circuit 37 are input to the AND circuit 70. The AND circuit 70 outputs the same output signal as the rectangular signal from the output terminal _Q4 . The output signal and the L output from the flip-flop circuit 33 are input to the OR circuit 74.
The right exercise indicator lamp 32 flashes according to the H or L state of the output signal.

While the center gate 12 is repeatedly opened and closed by the drive of the solenoid 15, when 10 pachinko balls fly into the winning slot 11 one after another, the count switch 16 is closed for each pachinko ball and one clock is divided into 4 bits. In order to output to the input terminal C of the binary counter circuit 77, the output terminals Q ₂ and Q ₄ of the 4-bit binary counter circuit 77 output H, and both H outputs are input to the AND circuit 68. The AND circuit 68 therefore outputs H, and the H output is input to the OR circuit 67, which outputs H and flips the flip-flop circuit 3.
The flip-flop circuit 34 is reset by inputting H to the reset terminal R of the flip-flop circuit 4. Therefore, similarly to the above, the NOR circuit 61 outputs H, and the AND circuit 62 receives the H output and the output signal from the output terminal _Q6 of the 12-bit binary counter circuit 37, The bit binary counter circuit 37 is repeatedly reset and reset in response to the output signal from the output terminal _Q6 . Therefore, the output terminals Q ₇ to _{Q 12} of the 12-bit binary counter circuit 37 are in the L state, and L is output from the OR circuit 58, so that the solenoid 15 is driven even if the solenoid 15 has not completed the 18th driving operation. stops.

When the right exercise switch 29 is closed, the AND circuit 50 outputs H as described above, but the H output is input to the reset terminal R of the flip-flop circuit 33 via the OR circuit 52, and the output is input to the reset terminal R of the flip-flop circuit 33. will be reset. Therefore, its output terminal Q outputs a signal from H to L, and the L output is inputted to the input terminal D of the flip-flop circuit 34.
cancels the storage of the H output from the output terminal Q of the flip-flop circuit 33. As a result, L is inputted to the AND circuit 71 from the output terminal Q of the flip-flop circuit 33, and the right reservation indicator lamp 26 is turned off.

Even if L is input to the input terminal D of the flip-flop circuit 34 as described above, the right exercise switch 29
is closed, the AND circuit 50 outputs H, and H is input to the flip-flop circuit input terminal C. If the count winning switch 16 is not closed for 28.8 seconds (0.8 seconds x 18 times) or 10 times, Since H is not input to the reset terminal R of the flip-flop circuit 34, no reset occurs. This flip-flop circuit 34 is reset and the output terminal Q
becomes L, and L is input to the AND circuit 70. L is input to the AND circuit 70. When L is input to the AND circuit 70, the AND circuit outputs L, and the L output and the L output from the flip-flop circuit 35 are input to the OR circuit 74. Therefore, the OR circuit 74 outputs L, and the right exercise indicator lamp 32 stops blinking and goes out.

(Effects of the Invention) As described above, the present invention can provide a pachinko machine that is rich in game variety and stimulates the player's desire to play.

[Brief explanation of drawings]

FIG. 1 is a front view showing a pachinko machine according to the present invention, FIG. 2 is a schematic view of the front main part of the pachinko machine according to the present invention, viewed from an oblique side, and FIG. 3 is a front view showing a pachinko machine according to the present invention. A perspective view showing the connection relationship between a center gate and a solenoid used in a pachinko machine, No. 4
5 is a control circuit diagram used in the present invention, FIGS. 5 and 6 are signal waveform diagrams of a clock signal output from a 12-bit binary counter circuit, and FIG.
The figure shows a series of signal waveforms when the solenoid performs the second winning probability increasing state, and FIG. 8 shows a series of signal waveforms when the solenoid performs the first winning probability increasing state. 15... Solenoid, 22... Prize opening for securing rights,
27...Right row use prize opening, 33...Flip-flop circuit, 34...Flip-flop circuit, 35...Flip-flop circuit, 36...Clock oscillation circuit,
37...12-bit binary counter circuit, 38...Reset circuit, 39...Reset circuit, 40...Reset circuit, 42...Solenoid drive circuit.

Claims (1)

[Claims] 1. A solenoid that increases the probability of winning a prize, and a right securing that is turned on when a pachinko ball enters the winning opening for securing the right and sets the solenoid to a first winning probability increasing state and drive preparation state. circuit, and when the right securing circuit is in an ON state and a pachinko ball flies into a winning opening for right-handling use that is different from the winning opening for securing rights and is turned on, the solenoid is set in a first winning probability increasing state. When the right securing circuit is in the OFF state and a pachinko ball flies into the right row use winning opening and is turned on, the solenoid is activated so that the winning probability is lower than in the first winning probability increasing state. A pachinko machine characterized by comprising: a rights exercise circuit that drives the probability to be in a second winning probability increasing state.