JPH0472382B2 - - Google Patents

Description

[Detailed description of the invention]

[Summary] The present invention is a method for manufacturing a semiconductor device, in which a shot gate electrode of silicide containing tungsten is formed on a compound semiconductor, and impurity ions are implanted using the gate electrode as a mask to form a source region and a drain region. The implanted impurities are activated by high-temperature heat treatment, and electrodes are formed on the source and drain regions. By taking the peak values required for the source and drain regions at a predetermined depth from the surface, semiconductor devices such as shot-gate field effect transistors using compound semiconductors can be manufactured in a self-aligned manner. Moreover, a sufficient breakdown voltage can be obtained between the shot gate electrode and the source and drain regions without any special processing. [Industrial Field of Application] The present invention is directed to a shotgun using a compound semiconductor.
The present invention relates to a method suitable for manufacturing semiconductor devices such as gate field effect transistors. [Prior Art] Conventionally, for example, gate electrodes of GaAs shot gate field effect transistors have been made of aluminum (Al), gold (Au), titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta).
Metals such as are used. [Problems to be solved by the invention] However, heat treatment at about 600 degrees Celsius deteriorates the electrical characteristics of the gate electrode, such as barrier height, n value (1.04), and reverse breakdown voltage. , it becomes impossible to operate as a transistor. Therefore, in recent years, a device using TiW as a gate electrode has been announced as an attempt to eliminate the drawbacks of the conventional device. However, this too cannot withstand heat treatment at, for example, 850 [°C], and the barrier is lost and it becomes unstable. Moreover, if normal manufacturing processes are used, the resistivity may increase due to corrosion during the process, or
It may be lost. The present invention seeks to provide a method for manufacturing a semiconductor device having a shot gate electrode that can withstand heat treatment at temperatures of 850[° C.] or higher. Incidentally, here, "shot contact" refers to the case where the electrode metal directly contacts the semiconductor substrate to generate diode characteristics, or the case where the electrode metal directly contacts the semiconductor substrate and further forms an alloy between the semiconductor substrate and generates diode characteristics. In addition, the term also includes those in which an electrode metal is disposed through a natural oxide film on the surface of a semiconductor substrate, and diode characteristics occur due to tunneling in the natural oxide film. [Means for Solving the Problems] In the method for manufacturing a semiconductor device according to the present invention, (1) an active layer of one conductivity type (for example, n-type layer 3) is formed on the surface of a compound semiconductor (for example, substrate 1); Next, a step of forming a shot gate electrode (for example, shot gate electrode 4) made of silicide containing tungsten on the active layer; and then, using the shot gate electrode as a mask, impurities (for example, A step of ion-implanting Si, etc.) to form a source region (e.g., n ⁺ type region 6) and a drain region (e.g., n ⁺ type region 7) on both sides of the shot gate electrode; High-temperature heat treatment for activation (e.g. heat treatment at approximately 800 [℃])
and then forming electrodes (for example, electrodes 8 and 9) in contact with the source and drain regions, and the ion implantation for forming the source and drain regions is carried out on the surface. The impurity concentration is higher than that of the active layer and low enough not to cause a short circuit with the shot gate electrode, and peaks at a predetermined depth from the surface. or (2) a step of forming an active layer of one conductivity type on the surface of the compound semiconductor, and then forming a shot layer made of silicide containing tungsten on the active layer.
a step of forming a gate electrode, then a step of ion-implanting an impurity using the shot gate electrode as a mask to form a source region and a drain region on both sides of the shot gate electrode; a step of performing high-temperature heat treatment for activation, and then etching the surfaces of the source and drain regions so that they are lower than the interface between the shot gate electrode and the compound semiconductor (step, for example, see FIG. 6). and then forming electrodes in contact with the source and drain regions, and the ion implantation for forming the source and drain regions is performed so that the impurity concentration at the surface is higher than that of the active layer. It is characterized by being high and low enough not to cause a short circuit with the shot gate electrode, and reaching a peak at a predetermined depth from the surface. [Function] By adopting the above structure, the relative positional relationship between the shot gate electrode and the source region and the drain region can be determined in a self-aligned manner, and the shot barrier remains good even when high-temperature heat treatment is performed. In addition, it is possible to maintain a sufficient breakdown voltage between the shot gate electrode and the source region and the drain region without creating a special structure or performing special processing. be. [Embodiment] Figures 1 to 6 are cut-away side views of essential parts of a semiconductor device at key points in the process for explaining an embodiment of the present invention, and the following description will be made with reference to these figures. do. See Figure 1 (1) A silicon dioxide film 2 with a thickness of, for example, 6000 [Å] is formed on a GaAs semi-insulating substrate 1 doped with chromium (Cr), and this is patterned using a normal technique to form a window 2a. do. (2) By applying ion implantation technology, the acceleration energy is 175 [KeV] and the dose is 2.6×10 ¹²
Silicon (Si) is implanted as [cm ^-2 ]. See Figure 2 (3) After removing the silicon dioxide film 2, a new thickness of, for example, 1000 [Å] is added to prevent out-diffusion.
After forming a silicon dioxide film of about 100 mL, heat treatment is performed at a temperature of 850 Å for a time of 15 minutes, for example, to obtain an n-type layer 3 as shown in the figure. Note that the silicon dioxide film formed to prevent outward diffusion is removed after the heat treatment is completed. See Figure 3 (4) An alloy of TiWSi, for example, an alloy consisting of Ti _0.3 W _0.7 Si _0.2 , is deposited by sputtering to a thickness of 6000 mm, for example.
An alloy film of [Å] is formed, and this is mixed with CF ₄ +O ₂ (5
The shot gate electrode 4 is formed by patterning using a dry etching technique using an etchant consisting of [%]. See FIG. 4 (5) A silicon dioxide film 5 is formed and patterned to form a window 5a to expose a part of the surface of the n-type layer 3. (6) By applying ion implantation technology, the acceleration energy is 175 [KeV] and the dose is 1.7×10 ¹³
Si is implanted as [cm ^-2 ]. See Figure 5 (7) After removing the silicon dioxide film 5, a new silicon dioxide film with a thickness of, for example, 1000 [Å] is formed, and the temperature is set to, for example, 800 [°C] for 15 hours.
After heat treatment for about [minutes], it becomes as shown in the figure.
n ⁺ type region (source region and drain region) 6,
form 7. Note that the second silicon dioxide film formed is for the purpose of preventing outward diffusion, and is therefore removed after the heat treatment is completed. The impurity concentration of the n ⁺ type regions 6 and 7 thus formed is 1×10 ¹⁸ [cm ^-3 ] at the peak portion, and that of the n-type layer 3 is also 1×10 ¹⁷ [cm −3 ] at the peak portion. ^-3 ]. Refer to FIG. 6 (8) If necessary, the exposed GaAs partial surface, especially the surface of the n ⁺ type regions 6 and 7, is etched by about 100 Å. In this case, KOH+H ₂ O ₂ may be used as the etching solution. (9) Complete the process by forming electrodes 8 and 9 on n ⁺ type regions 6 and 7 by applying ordinary techniques.
As the electrode material in this case, AuGe/Au type may be used. Specific main data regarding the semiconductor device thus obtained are as follows. Gate length: 1.4 [μm] Gate width: 200 [μm] Source-drain distance: 6 [μm] Mutual conductance g _n : 23 [m] Source-gate capacitance C _gs : 0.21 [pF] Cut-off frequency _T : 12.3"GHz" Regarding the short gate n value: 1.18 Barrier height: 0.78 Breakdown voltage: 10 [V] By the way, in the present invention, the n ⁺ type regions 6 and 7 are formed by a self-alignment method using the gate electrode 4 as a mask. There are concerns about short circuits occurring between them, but this is not a problem at all. That is, as described above, the n ⁺ type region 6,
7, the impurity concentration distribution there becomes the 7th
As seen in the figure, it becomes a Gaussian distribution, with a peak generated at a depth of, for example, 0.12 [μm],
So if 1×10 ¹⁸ [cm ^-3 ], then 1× on the surface
Since it is about 10 ¹⁷ [cm ^-3 ], it is possible to ensure a breakdown voltage of 5 [V] or more. Further, as shown in step (8), if etching is performed to a depth of, for example, about 100 [Å], the breakdown voltage depending on the impurity concentration distribution can be further improved without substantially impairing it. In order to maintain the reverse breakdown voltage at the shot gate electrode, the following measures can be considered. That is, (1) the dose of n ⁺ type regions 6 and 7 is reduced. (2) After forming the n ⁺ type regions 6 and 7, the shot gate electrode 4 is etched to be thin. (3) Insulate the short gate electrode 4. (4) Etch the surfaces of n ⁺ type regions 6 and 7. (5) Before forming the n ⁺ type regions 6 and 7, the shot gate electrode 4 serving as a mask is processed into an umbrella shape, or an umbrella-shaped mask is provided separately before ion implantation. . (6) The project range is deepened by increasing the energy of ion implantation (as in the above embodiment). In the present invention, the above-mentioned means (6) is basically adopted, but other means may be used in combination as necessary. For example, the data regarding the shot reverse breakdown voltage for the GaAsn ⁺ type region is as follows.

[Table] By the way, in the present invention, the position of the shot gate electrode can be determined by self-alignment, that is, the shot gate electrode can be formed, then ion implantation can be performed, and its activation heat treatment can be performed. This is largely due to the use of high melting point metal silicide, especially tungsten-containing silicide, as the electrode material.
Comparing data with TiWSi and TiWSi is shown below.

〔Effect of the invention〕

As can be seen from the above explanation, in the present invention,
By using a silicide containing tungsten among refractory metal silicides as the shot gate electrode, the relative positional relationship between the shot gate electrode and the source and drain regions can be determined in a self-aligned manner. ,Also,
Even if high-temperature heat treatment is performed, the shot barrier is maintained in good condition, and the shot gate electrode and the source and drain regions can be connected to each other without creating a special structure or performing special processing. It is possible to obtain a sufficient withstand pressure between .

[Brief explanation of drawings]

1 to 6 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIG. 7 is a diagram for explaining impurity concentration distribution. ing. In the figure, 1 is a substrate, 3 is an n-type layer, 4 is a shot gate electrode, 6 and 7 are n ⁺ type regions, 8,
9 each indicates an electrode.

Claims (1)

[Claims] 1. A step of forming an active layer of one conductivity type on the surface of a compound semiconductor; Next, a step of forming a shot gate electrode made of silicide containing tungsten on the active layer; a step of ion-implanting impurities using the shot gate electrode as a mask to form a source region and a drain region on both sides of the shot gate electrode; a step of performing high temperature heat treatment to activate the implanted impurities; , forming an electrode in contact with the source region and the drain region, and the ion implantation for forming the source region and the drain region is performed so that the impurity concentration at the surface is higher than that of the active layer. 1. A method of manufacturing a semiconductor device, characterized in that the short-circuiting is performed at a level low enough not to cause a short circuit with the gate electrode, and at the same time reaching a peak at a predetermined depth from the surface. 2. Forming an active layer of one conductivity type on the surface of the compound semiconductor; Next, forming a shot gate electrode made of silicide containing tungsten on the active layer; Next, masking the shot gate electrode. a step of ion-implanting impurities to form a source region and a drain region on both sides of the shot gate electrode; a step of performing high-temperature heat treatment to activate the implanted impurities; etching the surface of the region to be lower than the interface between the shot gate electrode and the compound semiconductor; and then forming an electrode in contact with the source region and the drain region. The ion implantation for forming the drain region is performed so that the impurity concentration at the surface is higher than that of the active layer, low enough not to cause a short circuit with the short gate electrode, and at a predetermined depth from the surface. A method for manufacturing a semiconductor device, characterized in that the manufacturing method is performed so that the peak occurs at .