JPH0473322B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to transistor RF amplifiers, and more particularly to packaging high power RF amplifiers that utilize a push-pull (also known as balanced or dual) configuration. be.

Transistor dice, ie, transistor devices having multiple transistor cells formed on a chip, are often employed in the design of radio frequency amplifiers. Those dice are
It is used together with other components to form the entire RF amplifier. This amplifier includes an input impedance matching circuit and an output impedance matching circuit to match the input impedance and output impedance to the respective internal impedances of the connected signal source and load. Large power (10~200
To construct an amplifier (Watt's stand), the conventional method was to connect many transistor cells in parallel. This approach increases the amplifier's power, but lowers its input and output impedances, creating RF losses and reducing the amplifier's bandwidth.

Improvements to conventional parallel combination amplifiers have been granted a U.S. patent.
Issue 4107728 and the magazine "Microwave"
Max's article "Balanced Transistors: A New Option for RF Design" published in June 1977.
For RF Design). In the disclosed design, a pair of transistor chips having an equal number of cells are connected in series for RF operation. This series connection increases the input impedance and output impedance of the transistors by four times the impedance when they are connected in parallel. External circuitry is utilized to drive the two dice in a push-pull mode of operation. The high input and output impedances make it very easy to match the transistor to the signal source and load.

The overall physical configuration of a conventional push-pull configuration is shown in FIG. Device 10 includes a pair of multi-cell transistor dice 12, 14 arranged such that all the transistor cells lie along a single line perpendicular to the symmetry axis of the device. Dice 1
2,14 are placed on the collector metallization pads 18,20. The pads are placed on a ceramic ( _BeO ) carrier 22. The device includes a ground metallization region 24 and a pair of MOS input capacitors 26 disposed above the ground metallization region.
including. Connecting wires 28 connect the base, emitter, and collector of the die to various points. A shunt inductor 30 is provided to counteract the effects of the output capacitance of this device. Typically, this shunt inductor is a metallized strip connected between the collector pads of the two dies.

Parasitic inductance exists in the wires and metallization areas. As this inductance increases, the loss inside the device increases and the bandwidth of the device becomes narrower. Therefore, it is desirable to minimize the inductance associated with the wires and metallization areas of the device. It is an object of the invention to reduce the inductance associated with these elements.

For optimal operation, all cells within each cell must operate identically. That is, the current flowing through each cell should be the same. This will minimize the temperature difference between the cells and ensure that the power is shared evenly. However, in the configuration shown in FIG. 1, the current paths between cells connected in series (via the emitter ground (or base-ground) wire 28 and the ground metallization region) are not equal. Another object of the invention is to obtain a transistor configuration that equalizes the currents flowing through the transistor cells.

These and other objects are achieved by providing a push-pull transistor device configured such that the individual cells of each die are equidistant from an axis of symmetry of the push-pull transistor device. This configuration provides a constant electrical length between the two dice, which allows current to flow from the base (or emitter) of one die to the base (or emitter) of the other die with the lowest impedance. Since the electrical length is constant, the power is shared equally between each cell, and 2
The inductance between the two dice becomes smaller.
The lower inductance reduces series feedback and increases stability due to lower losses within the device. This configuration makes it easy to shorten the length of the shunt inductor between the collectors. This is useful for microwave applications and high power transistors with large output capacitances that require small value shunt inductors. This configuration also allows multiple identical shunt inductors to be used to further equalize power sharing between cells.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

Referring first to FIGS. 2 and 3, the push-pull transistor of the present invention utilizes a ceramic (typically B _e O) carrier 40 and an alumina substrate 54 on top. The carrier 40 includes base (for grounded emitter configurations) or emitter (for grounded base configurations) input metallization areas 42, 44, ground metallization areas 46, 48, and collector or output metallization areas 50, 52. include. The collector metallization region includes collector pads 50a, 52a. A pair of collector metallization-to-collector metallization shunt inductors 53 connect collector pads 50a, 52a.

The alumina substrate 54 has a pair of elongated holes 54a, 5
Contains 4b. A common ground metallization area 56 is connected to the substrate 5.
Cover most of the top surface of 4. This metallized region extends at the edge of the substrate 54. These edge metallization areas 56a, 56b connect the metallization areas 56 to the carrier 4.
0 metallized areas 46, 48. A pair of input metallization regions 58, 60 are connected to the substrate 40.
and includes edge metallized areas 58a, 60a. These edge metallization areas 58a, 60a are connected to the input metallization areas 58, 60 to the metallization areas 42, 44 of the carrier 40.
contact.

FIG. 4 shows an assembled transistor device of the present invention. The alumina substrate 54 has holes 54a, 54
is mounted on the ceramic carrier 40 such that the collector pads 50a, 52a are located above the collector pads 50a, 52a. A pair of transistor dice 62,6
4 are fixed to collector pads 50a and 52a, respectively. Each transistor die is comprised of a plurality of transistor cells, and the body of the die constitutes a common collector for all transistor cells. Although each die is shown in FIG. 4 as having four transistor cells, any number of cells may be used.

A pair of MOS capacitors 66, 6 are installed near the holes 54a, 54b on the top surface of the alumina substrate 54.
8 is provided. A plurality of wires 70a, 70b connect the emitters of the transistor cells to the ground metallization in the strip between the holes and to the terminals of the appropriate capacitors 66, 68, respectively. Similarly,
Wires 72a, 72b connect the bases of the transistor cells to the other terminals of appropriate capacitors 66, 68 and input metallization regions 58, 60, respectively. One of the terminals of capacitors 66, 68 is connected to ground metallization. An input lead 74, a collector lead 76, and a ground lead 78 are attached to corresponding metallized areas on carrier 40.

By connecting the emitter of the transistor cell to ground metallization region 56, the illustrated transistor device provides grounded emitter operation. Base grounding is accomplished by changing the wire connection to the base of the transistor cell to a connection to a ground metallization region.

Figure 5 shows the transistor shown in Figure 4.
This is the equivalent circuit of the package. Transmission line 50,5
2, 58, 60 and inductors 53, 56, 70,
72 corresponds to the similarly numbered wires and/or metallization areas of the device shown in FIG. The equivalent circuit for the device shown in Figure 1 is the same as the circuit shown in Figure 5, except that the additional parasitic inductance 79 is created by the wire required to connect the collector pad to the output terminal. What they are forced to do is different. The present invention eliminates the need for those wires (or any type of bridge connection) by using a separate carrier 40 and substrate 54.

The advantages when the structure shown in FIG. 4 is used over the conventional structure become clear by comparing the corresponding values of the various parasitic inductances of both structures. The inductance created by the wires 70a connecting the emitter of each cell to the ground metallization is, due to the length of those wires,
The conventional structure shown in the figure is relatively large. In the structure shown in FIG. 4, the wire 70a is short because the alumina substrate 54 can be provided close to the die. A single level structure such as that shown in FIG. 1 requires a relatively large amount of space between the collector pad 18 and the ground metallization region 24. In contrast, in the present invention, because of the location of the ground metallization on a separate alumina substrate, the wires connecting the cell to the ground metallization can be significantly shorter.

Ground metallization area 56 in the structure shown in FIG.
The inductance of a is constant for each cell,
Relatively small (due to short paths). In traditional structures, their inductance is relatively large;
It is not constant for each cell. That is, the electrical path through the ground metallization between the dies is different from cell to cell. In the structure shown in Figure 4, the electrical length between the two dies is very constant, so that the current flows from the emitter of one die to the emitter of the other die (or from base to base in a common base structure). can flow with the lowest impedance. If the electrical length between the two dice is constant, the power will be shared equally between each cell.
The relatively small inductance between the two dice increases the stability of the device and reduces RF losses.

The conventional structure shown in FIG. 1 uses only one shunt inductor, the shortest length of which is approximately equal to the length of the die. Several shunt inductors can be used with the present invention and can be made very short if necessary. Using multiple shunt inductors allows for equal electrical paths between the cells and equal power sharing between the cells. When a short shunt inductor is required, such as in the microwave field or when a small shunt inductor value is required, such as in a high power transistor with a large output capacitance, the method shown in Figure 6 is used. Structures similar to those shown can be used. In this construction, four very short metallization strips 80 are used in place of the two relatively long shunt inductors 53 shown in FIG. The inductors 80 provide each transistor cell with a small and equal value of inductance. Also, open stubs 42a and 44 for performing input matching and output matching for the microwave transistor.
The input metallization and collector metallization can be modified to include a, 50b, and 52b.

FIG. 7 shows another embodiment of the invention in which the alumina substrate is provided with an opening 90 and the emitters (or bases) of the dice are connected together by wires 92. In this embodiment, the center of the wire constitutes a virtual ground and makes no actual connection to the ground metallization area. wire 92
is supported by a glass rod 94. Further input matching and output matching can be achieved by MOS capacitors 96 and 98.

In summary, the arrangement of the invention provides a transistor device with low values of parasitic inductance due to the wires and metallization regions. This small value of parasitic inductance increases device stability, increases bandwidth, and reduces losses within the package. Furthermore, the symmetry of the package has been improved over conventional structures to improve power sharing between different cells of the die. The RF performance of the transistor is improved because the improved power sharing between the cells reduces the temperature difference between the cells. Several types of collector-collector shunt inductors are available for this package configuration, and unlike conventional structures, the minimum size of the inductor is not constrained by the size of the die. Additionally, the need for wires or bridges between the collector pad and the collector lead, either of which was previously required, is eliminated.

[Brief explanation of the drawing]

Fig. 1 is a plan view showing the structure of a conventional push-pull RF power transistor, Fig. 2 is a top view of a ceramic (B _e O) carrier that forms part of the present invention, and Fig. 3 shows a part of the present invention. A top view of the constituent alumina substrate, FIG. 4 is a top view of one embodiment of the present invention, FIG. 5 is an equivalent circuit diagram of the device shown in FIG. 4, and FIG. 6 is a top view of another embodiment of the present invention. 7 are top views of still another embodiment of the present invention. 40...carrier, 42, 44, 58, 60...
...Input metallization area, 46,48...Ground metallization area, 50,52...Output metallization area, 53,80
... Shunt inductor, 54 ... Substrate, 56
...metalized region, 56a, 56b, 58a, 60
a... Edge metallization region, 62, 64... Transistor die.

Claims (1)

[Scope of Claims] 1. A dielectric member having first and second input leads, first and second output leads, and a ground lead, in which these leads are arranged substantially symmetrically with respect to an axis of symmetry; a plurality of substantially identical transistor cells on a first die, each cell having an input terminal and a ground terminal on a first side of the first die and an opposite side of the first die; has a common output terminal on the second surface, which is the second surface, and this output terminal is connected to the first
a first transistor attached to said first output lead by a conductor of said second die, and a plurality of substantially identical transistor cells on a second die, each cell connected to said first output lead of said second die; It has an input terminal and a ground terminal on the surface thereof, and a common output terminal on the second surface which is the opposite surface of the second die, and this output terminal is connected to the second die.
a second transistor attached to the second output lead by a conductor; a third conductor connecting an input terminal of each cell of the first transistor to the first input lead; a fourth conductor that connects the input terminal of each cell of the transistor to the second input lead; and a fifth conductor that connects the ground terminal of each cell of the first and second transistors to the ground lead. , the cells of the first and second transistors are arranged parallel to and approximately equidistant from the axis of symmetry, and each of the third conductors has approximately the same electrical length. , each of the fourth conductors has substantially the same electrical length, each of the fifth conductors has substantially the same electrical length, and the first and second conductors have substantially the same electrical length. Pushpull RF amplifier featuring: 2. The dielectric portion comprises a carrier and a substrate stacked together, the carrier having the first and second output leads, and the substrate forming the first and second input leads and a ground lead. 2. The push-pull RF amplifier of claim 1, further comprising a metal region for accommodating said first and second transistors and at least one opening for accommodating said first and second transistors. 3. The fifth conductor comprises a conductor extending from a ground terminal of an individual cell to the dielectric portion forming a portion of a ground lead located between the first and second transistors. Push-pull RF according to claim 1, characterized in that
amplifier. 4. The push-pull RF amplifier according to claim 1, wherein the fifth conductor includes a conductor that directly connects the ground terminals of the individual cells of the first and second transistors. 5. A patent characterized in that the fifth conductor includes a conductor that directly connects the individual ground terminals of the first and second transistors without contacting the ground lead on the dielectric part. Claim 4
Push-pull RF amplifier as described in Section 1. 6. The push-pull RF amplifier of claim 1, wherein the first and second output leads are interconnected. 7. Push-pull RF according to claim 1, characterized in that opposing cells of the first and second transistors are coupled to a push-pull.
amplifier. 8. Claim 7, wherein the first and second output leads are interconnected by a plurality of spatially separated conductors connecting the opposing cells. Pushupuru described
RF amplifier.