JPH0473615B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a selective lifetime control technology, and in particular to a high-voltage, high-speed operation device comprising a semiconductor layer in which a region with a short carrier lifetime is selectively provided. The present invention relates to a semiconductor device and a manufacturing method thereof. [Technical Background of the Invention and Problems Therewith] A high voltage diode will be described as an example of a conventional high voltage semiconductor device with reference to FIG. Generally, in high voltage diodes, its PN
One side of the junction is constructed with a very low impurity concentration layer so that it can be easily depleted and also has a large layer thickness. P ⁺ in Figure 5
The N ⁻ layer 2 which is connected to the layer 1 is a region having a low impurity concentration and a large thickness. The N ⁺ layer 3 is a high impurity concentration layer and is provided mainly for taking out the electrode. In devices such as these that require high-speed operation using high-voltage diodes, it is necessary to improve reverse recovery characteristics, and generally, for example, it is necessary to shorten the lifetime of minority carriers (holes) injected into the N ^-layer 2. To do this, heavy metals such as gold and platinum are used as lifetime killers to diffuse them, or neutron beams, gamma rays, electron beams, etc. are irradiated. When the lifetime is shortened by these methods, the carrier lifetime of not just a part of the semiconductor substrate but almost the entire area is shortened. Therefore, the forward voltage drop of the diode V _F (Forward
Voltage Drop) increases significantly as the lifetime becomes shorter. In particular, the reverse withstand voltage value V _R
In a design that attempts to obtain (Reverse Blocking Voltage) of 1000 V or more, it is necessary to make one side of the PN junction, for example, the N ^- layer 2, extremely low concentration and thick, and the tendency for V _F to increase is extremely high. become noticeable. In order to solve this problem, a method has been proposed in which a short lifetime region is formed in a part of the N ^- layer 2 parallel to the main surface. As means for this method, there have been reports on the application of proton implantation technology, for example, but all of these are at the experimental research stage, and there is no good method that can be put to practical use. [Object of the Invention] In order to solve the above-mentioned problems, the object of the present invention is to provide a semiconductor device with a new structure in which a selective region with a short lifetime parallel to the layer plane is formed inside a semiconductor layer, and a method for manufacturing the same. It is. [Summary of the Invention] A semiconductor device of the present invention includes a first semiconductor layer of one conductivity type and a second semiconductor layer of one conductivity type,
a composite semiconductor layer including a junction surface where the plane orientation of the first semiconductor layer plane and the plane orientation of the second semiconductor layer plane are different from each other, and having a region in the vicinity thereof having a carrier lifetime shorter than that of the first and second semiconductor layers; It is characterized by comprising a PN junction formed with a semiconductor layer of an opposite conductivity type provided on at least one main surface of the composite semiconductor layer. Further, the method for manufacturing a semiconductor device of the present invention includes a step of mirror-polishing the main surface of the wafer on which the first and second semiconductor layers of one conductivity type are exposed, and polishing each of the mirror surfaces so that the plane orientations of the crystals are different from each other. A step of forming a composite semiconductor layer in which a bonding region having a carrier lifetime shorter than that of the first and second semiconductor layers is formed in the vicinity of the bonding surface by close bonding, and a step of forming a PN junction. do. The electrical resistance and thermal resistance at the junction surface of the composite semiconductor layer of the present invention are negligibly small. In addition, a silicon defect layer or an amorphous layer having a short carrier lifetime is formed near the bonding surface due to discontinuities in the crystal. An effective method is to use wafers in which the first and second semiconductor layers have different plane orientations, or to overlap and bond the wafers so that their orientation flats (chords of crescent-shaped notches in the wafers) do not coincide with each other. This is preferable because crystal disorder can be obtained. Furthermore, the region where the carrier lifetime is short is limited to the vicinity of the bonding surface, and in regions more than a few μm away from this region, the carrier lifetime does not decrease and the lifetime of the silicon wafer substrate before bonding is maintained. . In this way, in a composite semiconductor layer in which regions with short carrier lifetimes are selectively provided, excess accumulated minority carriers disappear quickly, and the reverse recovery characteristics can be improved while maintaining other characteristics of the semiconductor device. . [Embodiments of the Invention] A high-voltage, high-speed rectifier diode will be described below as a first embodiment of the present invention. Figure 1 is a cross-sectional view of this diode, where 11a is of one conductivity type (N ^-
11b is a first semiconductor layer of one conductivity type (N ^-
type). 11c is the first of two
and a region (hereinafter referred to as a short lifetime region for convenience) in which the carrier lifetime is shorter than that of the first and second semiconductor layers, which is formed in the vicinity of the bonding surface of the second semiconductor layers 11a and 11b. The composite semiconductor layer 11 includes a first semiconductor layer 11a, a short lifetime region 11c, and a second semiconductor layer 11b. 1
3 is a high concentration layer (N ⁺ layer) of one conductivity type and is a contact layer with an electrode (cathode K). 12 is a semiconductor layer of the opposite conductivity type P and forms a PN junction 19 with the composite semiconductor layer 11 . In this embodiment, in order to achieve a high breakdown voltage, the first and second ^{semiconductor} layers 11a are
and 11b have low impurity concentration and high resistance (20 to 60Ω
cm) and its thickness is also thick. In addition, in order to improve the reverse recovery characteristics of this PN junction diode, it is necessary to create a short lifetime region near the PN junction.
1c, and therefore the thickness of the first semiconductor layer 11a is designed to be as thin as possible compared to the thickness of the second semiconductor layer 11b. Next, among the steps of the method for manufacturing a semiconductor device of the present invention, the silicon wafer bonding technique will be explained first. This technology is a technology that integrates two silicon wafers and makes the interfacial resistance formed between both silicon substrates negligibly small. The actual method is to mirror-polish the surfaces of two silicon wafers to be joined in advance to a surface roughness of 500 Å or less.
If necessary, depending on the surface condition of the silicon wafer, a pretreatment step using H ₂ O ₂ +H ₂ SO ₄ →HF → dilute HF is performed successively. This degreases the surface of the silicon wafer and removes the adhered stain film. Next, the mirror surface of the silicon wafer is washed with clean water for several minutes, and dehydration treatment such as spinner treatment is performed at room temperature. In this treatment step, excess water is removed while leaving the water that is assumed to have been adsorbed on the mirror surface of the silicon wafer, and most of this adsorbed water evaporates.
Avoid heating and drying above 100℃. The silicon wafers that have undergone these treatments are placed in, for example, a clean atmosphere of class 1 or lower, and bonded in close contact with each other with substantially no foreign matter interposed between the mirror surfaces. Note that the bonding strength can be increased by heat-treating the silicon wafers bonded in this way at 200° C. or higher, preferably 1000° C. to 1200° C. A silicon bonding interface formed by this method does not form an electrical or thermal conduction barrier and has strong physical adhesion strength, resulting in a composite substrate that can be handled as if it were a single silicon single crystal. Next, a manufacturing method for forming the high-voltage high-speed rectifier diode shown in FIG. 1 will be described. A silicon wafer 14 on which a first semiconductor layer of one conductivity type (N ^- type) is exposed and a silicon wafer 15 on which a second semiconductor layer of the same conductivity type (N ^- type) is exposed are prepared, and the silicon wafer bonding technique described above is used. The mirror surface of the first semiconductor layer and the mirror surface of the second semiconductor layer are closely bonded to form a second semiconductor layer.
A composite semiconductor substrate shown in Figure a is obtained. At this time, a short lifetime region 11c is formed in the vicinity including the joint surface. Next, ^a high concentration of
A P ⁺ type impurity is diffused to form a PN junction 19 .
Next, N ⁺ type impurities are diffused into the N ^- type wafer 15,
A P ⁺ −N ⁻ −N ⁺ rectifier diode shown in FIG. 1 is formed. In another manufacturing method, a layer containing N ^- type impurities is formed on a P ⁺ type wafer by vapor phase epitaxy, and an ^{N -} type wafer is bonded using the method described above. On the exposed surface of the wafer,
A P ⁺ −N ⁻ −N ⁺ rectifier diode can also be formed by diffusing a higher concentration of N ⁺ type impurities. In this case, it is possible to control the thickness of the layer containing the N ^- type impurity to be grown in a vapor phase to several μm, thereby making it possible to form the short lifetime region 11c extremely close to the PN junction 19. . In this manufacturing method, even if the two wafers to be bonded have the same plane orientation and their crystal axes are aligned, crystallinity is disturbed in the vicinity of the bonding surface, resulting in the formation of a short lifetime region. However, for example, if the surface orientation of two wafers to be bonded is (100)
It is more effective to shift the crystal axes by combining and (111) or (100) and (911), or by gluing two wafers so that their orientation flats do not match. A short lifetime region can be formed. Next, the conductivity modulation type MOS FET of the second embodiment
I will explain about it. FIG. 3 is a cross-sectional view of this device, in which a PN junction is formed following the drain region of a so-called VDMOS structure. 21a
21b is an N ^- type first semiconductor layer, 21b is an N ^- type second semiconductor layer, and 21c is a short lifetime region in the vicinity including the junction surface. This maintains the carrier lifetime of the wafer substrate. The composite semiconductor layer 21 is the drain region of the VDMOS FET and the PN
It also serves as the cathode region of the diode having the junction 29. The portion of the P body 23 exposed on the substrate surface faces the semiconductor polycrystalline film 27 with the gate insulating film 28 interposed therebetween, forming a channel. 24 is N sauce,
25 and 26 are a source electrode and a gate electrode. 22 is a P ⁺ layer which is connected to the N-type first semiconductor layer 21a and PN
A bond 29 is formed. A rectifier diode similar to that shown in FIG. 1 is formed by the anode region 22 and the composite semiconductor layer 21 which also serves as a cathode region. One embodiment of the method for manufacturing this N-channel conductivity modulation type MOS FET is as follows. On P ⁺ type substrate (P ⁺
a substrate on which an N ^- type high resistance region (first semiconductor layer 21a) of about 20 to 60 Ωcm is grown in vapor phase on layer 22);
It is bonded to another N ^- type high resistance substrate (second semiconductor layer 21b) using the silicon wafer bonding technique described above to form a short lifetime region 21c. Thereafter, by a known method, P type impurities and N ⁺ type impurities are double diffused from the exposed surface of the N ^- type high resistance substrate using the semiconductor polycrystalline film 27 and the gate insulating film 28 as masks to form the P body 23 and the N + type impurity, respectively. N sauce 2
4 is formed, and further a gate electrode 26 and a source electrode 25 are formed. Similarly, the present invention can be applied to thyristors and the like. As a third embodiment, FIG. 4 shows a sectional view of a reverse blocking three-terminal thyristor. 31a is the first N ^- type
The semiconductor layer 31b is an N ^- type second semiconductor layer 31
c is a short lifetime region formed in the vicinity of the wafer bonding surface, and the composite semiconductor layer 31 consisting of these becomes the N ^- base layer of this thyristor.
32 is P ⁺ emitter layer, 33 is P ^- base layer, 34
is an N ⁺ emitter layer. Short lifetime layer 31
c improves the turn-off characteristics of this thyristor. [Effects of the Invention] Since the PN junction diode according to the present invention has a short lifetime region with a thickness of 1 μm or less selectively provided on the low concentration layer side, the forward electrical resistance of the low concentration layer is maintained. , the rate of disappearance of accumulated excess minority carriers at the time of polarity reversal can be increased. Therefore, it is possible to improve the reverse recovery characteristics or turn-off characteristics of semiconductor devices such as rectifier diodes, transistors, or thyristors that include this PN junction diode as a component without increasing the forward voltage drop, resulting in high withstand voltage and high speed performance. A working semiconductor device is obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a high voltage rectifier diode according to the first embodiment of the present invention, FIGS. 2 a and b are sectional views showing the manufacturing process of the high voltage rectifier diode of FIG. 1, and FIG. Example of conductivity modulated MOS FET
FIG. 4 is a cross-sectional view of a reverse blocking three-terminal thyristor of the third embodiment, and FIG. 5 is a cross-sectional view of a conventional high voltage rectifier diode. 11 , 21 , 31 ...composite semiconductor layer, 11a,
21a, 31a...first semiconductor layer of one conductivity type (N ^- type first semiconductor layer), 11b, 21b, 31b
... Second semiconductor layer of one conductivity type (N ^- type second semiconductor layer), 11c, 21c, 31c ... Short carrier lifetime region (short lifetime region) in the vicinity including the junction surface, 12, 22 , 32...Semiconductor layer of opposite conductivity type (P ⁺ layer), 14...Wafer in which the first semiconductor layer of one conductivity type is exposed, 15...Wafer in which the second semiconductor layer of one conductivity type is exposed, 19,
29...PN junction.

Claims (1)

[Claims] 1. A first semiconductor layer of one conductivity type and a second semiconductor layer of one conductivity type are bonded to each other, and the plane orientation of the first semiconductor layer plane and the plane orientation of the second semiconductor layer plane are different from each other. a composite semiconductor layer having a region in its vicinity including mutually different bonding surfaces and having a carrier lifetime shorter than that of the first and second semiconductor layers; and a composite semiconductor layer of opposite conductivity type provided on at least one main surface of the composite semiconductor layer. 1. A semiconductor device comprising a PN junction comprising a semiconductor layer. 2 (a) mirror polishing the main surface of the wafer where the first semiconductor layer of one conductivity type is exposed; (b) mirror polishing the main surface of the wafer where the second semiconductor layer of one conductivity type is exposed; c) The mirror surface of the first semiconductor layer and the mirror surface of the second semiconductor layer are closely bonded so that the plane orientations of the crystals of both mirror surfaces are different from each other, and the carrier lifetime is (d) forming a PN junction; and (d) forming a PN junction. 3. Claim 2, in which the orientation flat of the wafer on which the first semiconductor layer is exposed and the orientation flat of the wafer on which the second semiconductor layer is exposed are overlapped and closely bonded so that they do not coincide with each other. A method for manufacturing a semiconductor device.