JPH0550867B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention improves the breakdown voltage characteristics of a semiconductor device formed into a composite semiconductor substrate obtained by integrating a plurality of semiconductor substrates using a bonding technique.

[Technical Background of the Invention] The collector junction of diodes, bipolar transistors, etc. and the drain junction of double-diffused MOSFETs are used with the PN junction in a reverse bias state, but in order to reduce the series resistance that occurs at this time, it is necessary to As shown in Figure 5, an N ⁺ type semiconductor substrate 1 is used as a base.
It utilizes a stacked structure with an N ^- type semiconductor substrate 2.
It is common to form a semiconductor device by introducing impurities of opposite conductivity type into this N ^- type semiconductor substrate. By keeping a sufficient distance (t) between the bottom of the PN junction obtained by introducing this impurity and the N ⁺ type semiconductor substrate,
It is normal to prevent the breakdown phenomenon due to so-called "Reach Through" caused by the depletion layer that occurs during the PN junction operation. In addition, as structures in which the depletion layer extends in the direction along the surface of the semiconductor substrate, the field limiting type shown in FIG.
Place this on the insulator covering the PN junction end shown in the figure.
A field plate type is known in which the PN junction electrode is extended to share the voltage with this insulator.

On the other hand, the abalasynthic breakdown voltage of a PN junction is said to be smaller at the curved part than at the flat part.
Therefore, in planar semiconductor devices, consideration has been given to increasing the curvature of this curved portion, but it is difficult to extend the curvature to infinity or eliminate this curved portion.

[Problems with background technology]

Incidentally, in recent years, the breakdown voltage characteristics required of semiconductor devices have tended to increase, and this trend has been particularly noticeable recently.

In some planar semiconductor devices, an N ^- type semiconductor layer is deposited on an N + type semiconductor substrate by an epitaxial method, and a PN layer with exposed edges is deposited on the surface of the N ^- type semiconductor layer by an epitaxial method.
form a junction. Naturally, this N ⁺ semiconductor substrate is
The resistance is lower than that of the deposited low concentration semiconductor layer, and
Since the entire N ⁺ semiconductor substrate can be considered as an electrode, this
The electric field from the N ⁺ semiconductor substrate to the curved part continuous to the PN junction end is larger than the electric field to the flat part continuous to the curved part, which prevents high breakdown voltage as a semiconductor element. This state is shown in FIG. 8, where the flat portion is labeled A and the curved portion is labeled B.
As shown in the example in which the N ^- type semiconductor layer is deposited by the epitaxial method, the epitaxial method is preferred when stacking semiconductor layers with different concentrations regardless of whether the conductivity types are the same or different. Therefore, if it is necessary to avoid the above-mentioned "Reach Through", the thickness of the deposited layer is increased.

In order to reduce crystal defects in the layer deposited by this epitaxial method and improve the characteristics of the functional element formed here, the underlying semiconductor substrate is subjected to intrinsic gettering.
Gettering) is often applied. However, when the thickness of this deposited layer is increased, more heat load is applied to the underlying semiconductor substrate, which increases the frequency at which crystal defects occur due to the movement of oxygen contained in the deposited layer to the interface of the deposited layer. do.

[Purpose of the invention]

The present invention provides a novel semiconductor device that eliminates the above-mentioned drawbacks, and is particularly applicable to devices with a planar structure such as diodes, bipolar transistors, and double-diffused MOSFETs that use one side of a semiconductor substrate as an electrode. The purpose is to increase the withstand voltage of

[Summary of the invention]

As a method to achieve the above objective, a new composite semiconductor substrate is formed by closely bonding mirror surfaces formed on the surfaces of semiconductor substrates that exhibit the same conductivity type and have a difference in concentration, and a semiconductor device is formed here. . Regarding this bonding technology, there is a fact that the slightly damp mirror surfaces formed on the surface of a semiconductor substrate are integrated through a bonding layer that is obtained by closely adhering them, and that this bonding layer provides the bonding strength necessary for a semiconductor substrate. The applicant has confirmed the fact that a PN junction provided in a composite semiconductor has properties worthy of practical use. The present invention was completed based on this fact.

By the way, in the present invention, a PN junction is formed by introducing an impurity of an opposite conductivity type into the interior from the surface of the composite semiconductor substrate, and at this time, the end portion of the PN junction is exposed to the surface of the composite semiconductor substrate. This PN junction is formed in a dish shape as in the conventional case, and therefore has a flat part substantially parallel to the bonding layer of the composite semiconductor substrate, an exposed end of the PN junction, and a flat part located between this end and the flat part. It has a continuous curved part. An insulating layer is formed adjacent to the junction portion, which occupies a position facing the curved portion, to prevent an increase in the electric field at the curved portion, thereby achieving a high withstand voltage of the planar semiconductor device.
It is assumed that there is a structure different from the bulk structure at the interface of the semiconductor substrates that are brought into close contact with each other by applying the bonding technique, and that a grain boundary in metallography is formed.
This is referred to as a bonding layer in the present invention.

On the other hand, in a stacked structure of semiconductor substrates that exhibit the same conductivity type but have different concentrations, the boundary between the layers may vary depending on the thermal load applied thereto.
Therefore, the bonding layers of the present invention exhibit the same conductivity type,
Moreover, it does not only mean clearly dividing the boundaries between adjacent semiconductor substrates having a concentration difference, but also includes the above-mentioned fluctuation state.

[Embodiments of the invention]

The present invention will be explained in detail with reference to FIGS. 1 to 5.

First, the formation of the composite semiconductor substrate and the embedding of the insulating layer will be explained.

An oxide film 12 of 0.1 μm is provided on the surface of an N ⁺ type low-resistance silicon substrate 10 by a known thermal oxidation method, and serves as a buffer oxide for a silicon nitride layer to be described later. Next, the well-known chemical vapor phase growth method was used to obtain 0.1μ
After depositing silicon nitride 13 of m thickness, patterning is performed by a known photolithography method as shown in FIG. 1A in order to use this as a mask for selective oxidation. The position to install this mask varies depending on the type of semiconductor device to be formed, but it can be used for bipolar transistors, vertical double diffusion MOSFETs (hereinafter abbreviated as VDMOSFETs).
In the case of a model in which a plurality of PN junctions function as if they were a single unit, such as the above, the composite semiconductor substrate is formed except for the outer peripheral portion thereof. Subsequently, the oxide film 12 exposed by the photolithography process is removed once.
After etching the silicon substrate 10, it is again grown to a desired thickness by high temperature thermal oxidation treatment. This state is shown in FIG. 1a. This thickness adjustment is performed depending on the degree of etching of the silicon substrate 10 by the photolithography process and the high temperature thermal oxidation conditions. Further, the silicon nitride layer 13 is removed to obtain the cross-sectional structure shown in FIG. 1B in which the thick oxide film 12 is exposed. On the other hand, an N ^- type high resistance silicon substrate 14 is prepared, and a bonding process is performed together with the N ⁺ type low resistance silicon substrate 10 in which the thin oxide film 12 is embedded.

The surfaces of both silicon substrates 10 and 14 to be bonded are mirror polished to a surface roughness of 500° or less. At this time, depending on the surface condition of this silicon substrate, H ₂ O ₂ +
A pretreatment step using H ₂ SO ₄ →HF→dilute HF is subsequently performed to degrease and remove the stain film adhering to the silicon substrate surface. Next, this mirror surface of the silicon substrate is washed with clean water for several minutes, and dehydration treatment such as spinner treatment is performed at room temperature. In this treatment process, the moisture that is assumed to have been adsorbed on the mirror surface of the silicon substrate is left as is, and excess moisture is removed.Heat drying above 100°C, where most of this adsorbed moisture evaporates, is avoided. .

The silicon substrate mirror surface that has undergone these treatments is placed in, for example, a class 1 or higher clean atmosphere (not limited to the atmosphere, but may also be an H ₂ or oxidizing atmosphere),
These mirror surfaces are brought into close contact with each other in a state where no foreign matter is practically present between them to form the bonding layer and are integrated.
Note that this composite semiconductor substrate can be heat-treated at 200° C. or higher, preferably 1000° C. to 1200° C., to increase the bonding strength.

As a result, the cross-sectional structure shown in FIG. 1c was obtained,
The oxide film 12 has a shape adjacent to a bonding layer formed on the composite semiconductor substrate.

In this example, a selective oxidation method was adopted as a means for forming the oxide film, but as shown in FIG. An oxide film 16 is coated by a method, and a polycrystalline silicon layer 17 is further deposited. After mirror polishing this surface according to the bonding process, it is bonded to another silicon semiconductor substrate having a mirror surface and having a different concentration, to obtain a composite semiconductor substrate. SIPOS (Semi insulating Poly
Various insulating films such as crystalline silicon) and CVD films can be applied.

In the above composite semiconductor substrate, an example was shown in which N ⁺ type and N ^- type semiconductor substrates are integrated using the above bonding technology, but a P type semiconductor substrate is prepared, and a material selected from P, As, or Sb is prepared. There is no problem in applying the above bonding technique after forming an N ⁺ layer by introducing one type of N + layer. The composite semiconductor substrate obtained in this way
We will explain an example of forming a conductivity modulated MOSFET using VDMOSFET and VDMOSFET.
The cross-sectional structure of MOSFET 31 is shown.

In this MOSFET 31 , the thickness of the N ^- type drain region is set in advance to obtain the desired source-drain breakdown voltage, but in an element with a breakdown voltage of 500V, the specific resistance of the drain region is set to 20Ω・cm to 30Ω・cm with a thickness of 50 μm. ~
60μm, and for an element with a withstand voltage of 1000V, the specific resistance is
Set to 50Ω・cm～60Ω・cm thickness about 80～150μm,
P is usually used as the impurity contained. An N-type silicon substrate 20 with these considerations in place is prepared, and a P ⁺ -type semiconductor substrate 19 containing 10 ¹⁹ to 10 ²¹ atoms/cc of B is further prepared, and P ₉ is added to one surface of the substrate by ion implantation or the like. After introducing one type selected from As or Sb, heat treatment is performed to form the N ⁺ type region 21. This N ⁺ type region surface and N ^- type drain region 20
A composite semiconductor substrate is obtained by forming a mirror surface on the surface and integrating it in the bonding step, but the bonding layer 23 formed here does not act as an electrical or thermal conduction barrier, and does not provide a physical barrier. The bonding strength is sufficient and it can be handled as a single single crystal. This composite semiconductor substrate has a P ⁺ -N ⁺ -N ^- structure, and the surface of this N ^- silicon semiconductor substrate 20 is polished to adjust the thickness to a value required for a drain region. It goes without saying that the steps shown in FIGS. 1a to 1c are performed prior to this joining step.

Next, this polished surface is cleaned in a surface treatment process and coated with a silicon dioxide layer 24 of about 1000 Å, which is then coated with a silicon dioxide layer 24 of about 2000 Å to 3000 Å, which will become the gate layer 25 described later.
Selectively form polycrystalline silicon of .ANG. Using this polycrystalline silicon layer as a mask, an N-type impurity B is introduced into the N ^- type silicon semiconductor substrate by passing through the relatively thin silicon dioxide 24 by an ion implantation method.
P body regions 26 are formed by an annealing process.

Although not shown, a portion of the exposed silicon dioxide layer on which the polycrystalline silicon layer is not laminated is removed by a photolithography process, and As or P is applied to the N ^- type silicon semiconductor substrate 2 through this opening. The source region 27 is introduced into the P body region 26.
…form within. Furthermore, a CVD coating is deposited on the selectively formed polycrystalline silicon to form a buried structure. The source region 27... and the P body region 2
6 are exposed on the surface of the N-type silicon semiconductor substrate 20, so that they are protected by the silicon dioxide layer 24 as a result.

The silicon dioxide 24 deposited opposite the gate layer 25...that is, the polycrystalline silicon layer is removed, and then a conductive material such as Al or Al alloy is deposited to form the gate electrode 28...and the P body region 26. …
A conductive material such as Al or Al alloy is also deposited on the exposed surfaces of the source regions 27 to form the source electrodes 29.
..., and furthermore, the P ⁺ type silicon semiconductor substrate 19
The anode electrode 30 is formed by depositing Au etc. on the exposed surface of the anode electrode 30.
A conductivity modulation type semiconductor device 31 was completed.

Figure 3 shows the cross-sectional structure of VDMOSFET.
The conductivity modulated semiconductor device 31 shown in FIG.
Since the substrates are the same except for the P ⁺ type semiconductor substrate, the explanation will be omitted.

VDMOSFET and conductivity modulation MOSFET
By introducing impurities into the interior from the surface part, PN
Although multiple junctions are formed, a method is adopted in which each PN junction functions as a single element. However, when each PN junction is used as a single functional element, it is necessary to It is also possible to form an insulating layer for each of the curved portions that constitute one part. FIG. 4 shows a cross-sectional structure of this type of semiconductor device before completion. In this example, semiconductor substrates of the same conductivity type with different impurity concentrations are integrated through the bonding process to form a composite semiconductor substrate, and then necessary parts are formed to complete a semiconductor device. However, before performing the bonding process, as shown in FIGS. 1a to 1d, an insulating layer 12 is formed on the semiconductor substrate having a high concentration and facing the curved portion B existing in each of the PN junctions. .

〔Effect of the invention〕

In a stacked structure of semiconductor substrates that exhibit the same conductivity type but differ in concentration, a semiconductor substrate containing a high concentration of impurities exhibits low resistance due to the presence of other impurities, and can be regarded as an electrode. However, in the present invention, since an insulating layer is installed adjacent to the bonding layer facing the curved part of the PN junction where the electric field is most concentrated, the potential difference from this electrode to the curved part of the PN junction is reduced by this insulation layer. The voltage is shared by the material layers.

As a result, high voltage is not generated near the curved portion, so that the high durability required for a semiconductor device can be achieved.

In the above embodiments, a diode VDMOSFET and a conductivity modulation type MOSFET are illustrated, but it can be used as a collector junction, a drain junction, and the junction termination of a power semiconductor device such as a bipolar transistor known as a vertical element.

[Brief explanation of the drawing]

FIGS. 1a to 1e are cross-sectional views showing the manufacturing process of the present invention. FIGS. 2 to 4 are cross-sectional views of conductivity modulated MOSFETs according to the present invention, and FIGS. 5 to 8 are cross-sectional views showing the conventional structure. FIG. 21: first semiconductor substrate, 23: bonding layer, 19:
Second semiconductor substrate, B: curved portion, 12: insulator layer,
A: Flat area.

Claims (1)

[Claims] 1. A semiconductor substrate having a certain impurity concentration, a PN junction formed inward from the surface of this semiconductor substrate, a PN junction end exposed on the surface of this semiconductor substrate, and a connection to this PN junction end. What is claimed is: 1. A power semiconductor device comprising: a PN junction curved portion formed as a PN junction; and an insulator layer formed inside the semiconductor substrate facing the curved portion. 2. A step of embedding an insulating layer in one or both of a first semiconductor substrate having a certain impurity concentration and a second semiconductor substrate having an impurity concentration lower than the impurity concentration, and the surface of the first semiconductor substrate in which the insulating layer is embedded. and a step of forming a first mirror surface and a second mirror surface on the surface of a second semiconductor substrate, a step of bonding between the first mirror surface and the second mirror surface in which the insulating layer is partially embedded, and A power semiconductor, comprising a step of introducing impurities from one surface toward the inside to form a PN junction in which a curved portion is provided at a position facing a partially buried insulating layer. Method of manufacturing the device.