JPH0473913B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal processing device for a charge coupled device.

(Prior Art) Charge-coupled devices (hereinafter abbreviated as CCD) are generally used as image sensors, and compared to conventional image pickup tubes, they have the features of being smaller, lighter, lower power consumption, and more reliable. Furthermore, it has advantages in terms of characteristics such as no graphic distortion or burn-in. For this reason, in recent years,
In fields such as industrial cameras and home-use VTR-integrated cameras, image pickup tubes are being replaced, and advances in semiconductor manufacturing technology have resulted in the development of higher-resolution, higher-sensitivity CCDs. They are also beginning to be used in fields that require high-quality images, such as broadcast cameras.

However, the CCD image sensor having the above-mentioned features also has several drawbacks, one of the major ones being the problem of pixel defects. In other words, in image sensors that form individual pixels, such as CCD image sensors, if there is a defect in a pixel, even one pixel out of hundreds of thousands of pixels, it will be clearly visible as a scratch in the image. This is a major hindrance to achieving high image quality. For this reason, defect compensation has conventionally been performed by replacing the signal of a defective pixel with the signal of an adjacent pixel using a sample and hold circuit or the like.

FIG. 8 shows an example of a conventional pixel defect compensation circuit using the correlated double sampling method.

In FIG. 8, the CCD 81 is connected to a drive circuit 86.
Driven by. The signal A output from the CCD 81 is clamped by a clamp circuit 82 during the feed-through period, and the signal voltage of the output signal B is sampled and held by a sample hold circuit 83. This sampling method is called the correlated double sampling method (abbreviated as CDS method). Note that D and E indicate a clamp pulse and a sample hold pulse, respectively, which are generated by the sample pulse generator 87 and are controlled by the sample pulse control circuit 85 and the drive circuit 8.
It is applied in synchronization with the drive pulse No. 6. The memory 84 also stores position information of defective pixels.

Next, the operation of this pixel defect compensation circuit will be explained using the time chart of FIG. One cycle of the output signal A of the CCD 81 includes a reset period 31 in which the reset switch transistor is turned on by a reset pulse, a feed-through period 32 in which the floating diffusion layer is kept at a constant potential, and then,
It consists of a signal period 33 during which signal charges are sent from the CCD 81 to the charge detection section. The signal voltage V is detected as the difference V _P1 to V _P4 between the potential during the feed-through period 32 and the potential during the signal period 33 in the charge detection section. A clamp pulse D is applied to the clamp circuit 82 during the feed-through period 32 every cycle, and the feed-through level is clamped to a constant potential _VCP . Then, in the signal period 33, the sample and hold pulse E is applied to the sample and hold circuit 83.
In addition, the signal voltages V _P1 to V _P4 are sampled and held. For example, if the voltage of V _P3 is the voltage of a defective pixel, V _{P3 is} The voltage of V _P2 is held as it is without applying the sample hold pulse that samples it. Then, a sample and hold pulse is applied to the next normal pixel. The above operation makes it possible to replace the signal of the defective pixel with the signal of the pixel one cycle before.

(Problems to be Solved by the Invention) In the conventional pixel defect compensation circuit described above, in order to replace the image information of the defective pixel with the image information of the pixel one cycle before, the signal voltage is sampled during sampling. Must hold. Therefore, if the signal contains a high-frequency noise component, by holding the signal voltage, this high-frequency noise component is folded back as a low-frequency noise component, as will be explained in detail next. This causes the image quality to deteriorate.

FIG. 10 shows the sample and hold operation in the conventional CDS method. Clamp circuit 8 in Figure 8
2, the output signal B of the CCD 81 has its feedthrough level clamped to a certain potential _VCP .
is sampled and held by the sample and hold pulse E, but the output signal fluctuates like C until it is held. In other words, time t _a
When sample and hold starts, the potential of the hold capacitor gradually approaches input signal B, and becomes the same as input signal B at time _tb .
((t _b −t _a ) is called the acquisition time) The potential of the hold capacitor at time t _c when the sample pulse turns off is held until the next sample pulse turns on. Therefore, the held voltage is determined by the signal voltage at the time t _c when the sample pulse turns off, so if fluctuations due to high-frequency noise components are superimposed on the signal voltage, the high-frequency fluctuations will be compared to the low-frequency fluctuations. It will be replaced as a change. To explain with reference to the frequency characteristic diagram of FIG. 11, as shown in the figure, high-frequency noise components are folded back into low-frequency noise components. Therefore, even if you limit the band with a low-pass filter (LPF), this noise component cannot be removed.

The present invention has solved this problem, and its purpose is to provide a noise suppression and pixel defect compensation circuit that eliminates aliasing noise components and can compensate for pixel defects. It is in.

(Means for Solving the Problems) According to the present invention, a group of photoelectric conversion elements formed on a semiconductor substrate, a charge transfer shift register that transfers signal charges photoelectrically converted by the group of photoelectric conversion elements,
A floating diffusion type charge detection section that detects the transferred signal charge, an output amplifier that outputs a potential change of the charge detection section, a reset section that resets the potential of the charge detection section to a constant potential, and a detected signal charge. a charge-coupled device having a reset drain portion for sweeping out the charge-coupled device;
The output signal is divided into a period of time, a second period in which the signal charge of the charge detection section is swept out to the reset drain section, and a third period in which the potential of the charge detection section is reset to a constant potential. a drive circuit that receives the output signal and a signal obtained by delaying the output signal by a delay line for a predetermined period; a differential amplifier that outputs a signal that is divided and appears as a first signal voltage that is a negative voltage and a second signal voltage that is a negative voltage; and the first and second signal voltages are alternately switched to two outputs. A first switch circuit to take out the sample, a sample hold circuit and a gate circuit placed in parallel to each output of the switch circuit, and an inverter that makes the outputs of the sample hold circuit and the gate circuit have the same polarity. a second circuit for selecting and extracting the output signals of the sample and hold circuit and the gate circuit;
A charge-coupled device signal processing device is obtained, characterized in that it is equipped with a switch circuit.

(Operation) FIG. 6 shows the sampling operation in this embodiment. In this embodiment, a gate circuit is used for sampling except for image information of a defective pixel to be replaced. Therefore, as shown in the figure, the gate circuit is conductive only while the gate pulse is on, and an output signal that follows the input signal is obtained. Therefore, high frequency noise components are not folded back into the low frequency range. Therefore, by band-limiting with a low-pass filter as shown in the frequency characteristics of FIG. 7, high-frequency noise components can be completely removed.

As described above, with the defective pixel compensation circuit according to the present invention, defective pixel compensation can be performed without high-frequency noise components being folded back into the low-frequency range.

(Example) Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of a CCD signal processing circuit according to the present invention. In the same figure, CCD
11 is driven by a drive circuit 22. The output signal of the CCD 11 is connected to a differential amplifier 13 along with an output signal delayed by a certain period of time through a delay line 12 so that the difference between the potential in the feed-through period and the potential in the signal period can be amplified. In the output signal of the differential amplifier 13, voltages representing the signal voltage appear at two positions, positive and negative, within one cycle period. Therefore, the positive and negative signals appearing within one cycle are each output from the sample pulse control circuit 1.
An analog switch 14 controlled by an analog switch 9 controls switching so that one side is sampled by the gate circuit 17 and the other side is sampled by the sample-and-hold circuit 15. Further, the analog switch 18 controls the output signal of the gate circuit 17 for normal pixels, and the output signal of the sample and hold circuit 15 (more precisely, the inverter 16) for defective pixels.
output signal). Note that the inverter 16 is for matching the polarity of the signal, and the memory 20 stores position information of the defective pixel. Further, the pulse generator 21 is a pulse generator that is a source of all sample pulses.

FIG. 2 shows the configuration of a CCD image sensor and a differential amplifier circuit in an embodiment applied to an interline CCD image sensor. In the same figure, the signal charges photoelectrically exchanged by photodiodes P1 to P5 are
The data is read out to the vertical shift register 23 and transferred to the horizontal shift register 24. Next, the signal charge transferred to the horizontal shift register 24 is
Each line is output from the output amplifier 25. In addition,
The diagonal line on photodiode P3 indicates that P3 is a defective pixel. A differential amplifier 13 is connected next to the output amplifier 25. The output signal of the output amplifier 25 is directly input to the positive input of the differential amplifier 13, and the output signal delayed for a certain period is input to the negative input via the delay line 12. Next, the operation of this differential amplifier section will be explained using the time chart shown in FIG. One pixel period of the output signal of the output amplifier 25 includes a reset period 31 and a feedthrough period 3.
2. The signal period 33 is divided into signal periods 33, and the output signal voltage of one pixel is expressed as the difference between the potential in the feed-through period 32 and the potential in the signal period 33. In other words, in this figure, the output signal voltages of pixels P1 to P4 are respectively
V _P1 to V _P4 . The signal is a signal obtained by delaying the CCD output signal by the delay line 12 by a feed-through period.

The signal is the output signal of the differential amplifier 13. As shown in the figure, in the output signal of the differential amplifier 13, the output signal voltages V _P1 to V P4 of the pixels P1 to _P4 are as follows:
Positive and negative voltage V _P1 (+) ~ V _P4 (+), V _P1 (-) ~ V _P4
(-) appears in two places each.

FIG. 4 shows the circuit configuration of the sampling section.
The output of the differential amplifier 13 is sent to the analog switch 14.
It is connected to a sample hold circuit 15 and a gate circuit 17 via.

The output of each sampling circuit is connected to the next signal processing circuit via an analog switch 18.

In the same figure, , , and indicate pulses for controlling the analog switches 14 and 18, respectively, sample and hold pulses, and gate pulses.

Further, the inverter 16 is connected to the sampling circuit 1
This is to make the polarities of 5 and 16 the same.
The operation of the above signal processing circuit will be explained using the time chart shown in FIG. First, the differential amplifier 13
The signal voltage of pixel P1 is a negative voltage in the output signal of
At time _t1 , which appears as V _P1 (-), the control pulse of the analog switch 14 is Low (hereinafter L
), and the switch 14 is
It is electrically connected to the gate circuit 17.

At that time, the gate pulse becomes High (hereinafter abbreviated as H), the gate circuit 17 is in the ON state while the gate pulse is High, and the negative signal voltage V _P1 (-) is sampled. Then, the control pulse goes into the H state, and the switch 14 is switched to the sample and hold circuit 15 side. Then, at time _t2 when the signal voltage of pixel P1 appears as a positive voltage V _P1 (+), the pulse becomes H, the signal voltage V _P1 (+) begins to be sampled, and after the pulse becomes L, is held until the signal voltage V _P1 becomes H next. By repeating the above operations,
Signal voltages V _P (+) and V _P (-) that appear positive and negative are sampled.

Next, the output signal of the gate circuit 17 is inverted by the inverter 16 so as to have the same polarity as the output signal of the sample and hold circuit 15.

The operation of the analog switch 18 connected to the output circuit will be described. In a normal pixel, the control pulse of the analog switch 18 becomes L, and the output signal from the gate circuit 17 side is output. Then, the output signal V _P3 of the defective pixel P3 is output to the gate circuit 1.
At time _t3 output from 7, the control pulse of the analog switch 18 becomes H, and the switch 18
is switched to the sample-and-hold circuit 15 side, and the signal voltage V _P 2 of one pixel before is outputted this time. In other words, by operating the switch 18 based on the position information of the defective pixel in the memory 20, the signal voltage of the defective pixel can be replaced with the signal voltage of the previous pixel.

By repeating the above operations, pixel defects can be compensated for while sampling the signal voltage with the gate circuit.

(Effects of the Invention) As described above, with the signal processing circuit according to the present invention, it is possible to sample the signal voltage of a normal pixel using a gate circuit without folding the high-frequency noise component back into the low-frequency range. The signal voltage of a defective pixel can be replaced with the signal voltage of an adjacent pixel by a switch operation using a signal from a sample and hold circuit. As a result, it is possible to obtain a high-quality image with low noise and less deterioration in image quality due to scratches.

Note that in this example, the signal voltage of the defective pixel is
Although it is replaced with the signal voltage of one pixel before, it can be replaced with the signal voltage of any pixel by controlling the sample and hold pulse based on the position information of the flaw in the memory. Therefore, even if there are consecutive defective pixels, defect compensation is possible.

[Brief explanation of drawings]

FIG. 1 is an overall circuit configuration diagram of an embodiment according to the present invention, FIG. 2 is a circuit diagram of the CCD image sensor and differential amplification section of this embodiment, and FIG. 3 is an operation of the differential amplification section. The time chart, Figure 4, shows
FIG. 5 is a time chart showing the operation of sampling and pixel defect compensation; FIG. 6 is a diagram showing the operation of the gate circuit; and FIG. 7 is a diagram showing the operation of the gate circuit. Figure 8 is a diagram showing the high-frequency noise suppression effect, Figure 8 is an overall circuit configuration diagram in the conventional example, Figure 9 is a diagram showing the operation of sampling and pixel defect compensation in the conventional example, and Figure 10 is the sample and hold circuit. A diagram showing the operation of, FIG. 11, is as follows.
FIG. 3 is a diagram showing a aliasing phenomenon of high-frequency noise components in a conventional example. 11, 81... Charge coupled device, 12... Delay line, 13... Differential amplifier, 14, 18...
Analog switch, 15, 83... Sample hold circuit, 16... Inverter, 17... Gate circuit, 19, 85... Sample pulse control circuit,
20,84...Memory, 21,87, Sample pulse generator, 22,86...Drive circuit, 23...
Vertical shift register, 24...Horizontal shift register, 25...Output amplifier.

Claims (1)

[Claims] 1. A group of photoelectric conversion elements formed on a semiconductor substrate,
A charge transfer shift register that transfers signal charges photoelectrically converted by the photoelectric conversion element group, a floating diffusion type charge detection section that detects the transferred signal charges, an output amplifier that outputs a potential change of the charge detection section; A charge-coupled device has a reset section that resets the potential of the charge detection section to a constant potential, and a reset drain section that sweeps out the detected signal charge, and the charge-coupled device is driven to remove the signal charge within one pixel period. A first period in which the signal charge is injected into the charge detection section, a second period in which the signal charge of the charge detection section is swept out to the reset drain section, and a third period in which the potential of the charge detection section is reset to a constant potential. a drive circuit that divides the output signal into periods and obtains an output signal; and inputs the output signal and a signal obtained by delaying the output signal by a delay line for a predetermined period; a differential amplifier that outputs a signal that appears after being divided into a first signal voltage having a positive voltage and a second signal voltage having a negative voltage; A first switch circuit that alternately switches the signal voltage to two outputs and takes out the signal voltage, a sample-hold circuit and a gate circuit that are placed in parallel to each output of the switch circuit, and the outputs of the sample-hold circuit and the gate circuit have the same polarity. 1. A signal processing device for a charge-coupled device, comprising: an inverter that outputs signals of the same polarity, and a second switch circuit that selects and extracts output signals of the sample-and-hold circuit and the gate circuit that have the same polarity. 2. The sampling pulse that controls the first and second switch circuits, the sample pulse that controls the sample hold circuit and the gate circuit are generated by combining pulses generated by a pulse generator, and are synchronized with the drive circuit by a sample pulse control circuit. A charge-coupled device signal processing device according to claim 1. 3. The sample pulse that controls the sample hold circuit and the extraction pulse that controls the second switch circuit are controlled by a sample pulse control circuit based on data in a memory that stores position information of the defective pixel. 2. The signal processing device for a charge-coupled device according to claim 1, wherein the signal of is replaced by the signal of an adjacent peripheral pixel.