JP2563785B2 - Solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device including a signal output processing circuit of a solid-state image pickup device having a three-channel output for performing correlated double sampling.

[Prior Art] FIG. 1 is a diagram of a correlated double sampling circuit (CDS circuit) provided at the final stage of each horizontal shift register of the solid-state imaging device of the prior art and the present invention, and FIG. 2 is the output and drive of FIG. It is a timing chart showing a pulse.

1 and 2, φ _RS is a reset pulse, φ _CL is a clamp pulse, φ _SH is a sample hold pulse,
These three pulses φ _RS , φ _CL , and φ _SH also serve as drive pulses for the horizontal shift register, which will be described later.
The signal component is output.

In FIG. 1, 1 is a floating diode and 2
Turn on the MOSFET and set the potential at point A to a constant reset potential.
Hold at V _R and then turn off this MOSFET2. The signal charge is sent to the potential well created by the junction capacitance of the floating diode 1 at point A. The resulting potential change at point A is amplified through the source follower of MOSFET3. At the output at the point B, reset noise caused by switching of the resetting MOSFET 2 and 1 / f noise generated by the amplifying MOSFET 3 are included. The CDS circuit removes this noise. First, the high frequency component is cut by LPF4, and the potential (feedthrough level) of the signal AC-coupled by capacitor 5 is turned on by turning on MOSFET 6 for clamping. Clamp to the electric potential V _clamp . Further, after turning off the clamp MOSFET 6, the sample hold MOSFET 8 is turned on, the output signal potential of the charge coupled device (CCD), which is a solid-state image pickup device described later, is accumulated in the sample hold capacitor 9, and the sample hold is performed. The output signal potential is held even after the power MOSFET 8 is turned off. The held potential is amplified by the amplifier 10 and output.

Fig. 3 shows 3-channel output. Vertical CCDs A, B, C to horizontal CCDs a, b of CCDs that drive the three-phases by shifting the phases of the transfer pulses of the first, second, and third channels by 120 °. FIG. 4 is a diagram showing an example of a portion for transferring charges to c and c, and FIG. 4 is a CC of FIG.
In the figure showing the drive pulse of D, φ _P is a vertical CCD, transfer pulse of A, B, C, φ _T is a signal taken in the vertical CCD from a light receiving pixel (not shown), CCD and A are 1 bit at a time. Transfer pulses for sending out, φ _S1 , φ _S2 , and φ _S3 are transfer pulses for transferring respective signals in the horizontal CCDs, a, b, and c.

The CCD shown in FIG. 3 is a virtual phase CCD (for details, see
11) (shown in No. 55-11394) is Virtual Phase
And the 12 shaded areas have the polysilicon electrodes
Clocked Phase.

FIG. 5 is a diagram showing potential profiles of Virtual Phase 14 and Clocked Phase 15. The solid line shows the movement of charges when the transfer pulse φ is low (L), and the broken line shows the movement of charges when the transfer pulse φ is high (H). As is apparent from FIG. 5, charges can be transferred by driving φ in a single phase. Therefore, charges can be transferred from the vertical CCD to the horizontal CCD by the pulse in the horizontal blanking period 13 in FIG.

In the case of attaching the CDS circuit to a CCD having such three-channel output and driving pulses of three phases, conventionally, the CDS circuit is driven by using the transfer pulses φ _S1 , φ _S2 , φ _S3 of FIG. It was

12 to 14 are timing charts showing timings of transfer pulses for driving the conventional CDS circuit. First
In FIG. 12, V _out 1 is the output of the first channel. Reset at transfer pulse φ _S3 time t ₁ , transfer pulse φ _S1 time t ₂
Therefore, unnecessary noise does not occur because the sample is held at the time t ₃ of the clamp and transfer pulse φ _S2 . In Figure 13, V _out 2
Is the output of the second channel. Transfer pulse φ _S1 time
Reset at t ₄ and clamp at transfer pulse φ _S2 time t ₅ ,
Since the sample is held at the time t ₆ of the transfer pulse φ _S3 , no noise is generated as in the case of the first channel. Shown in Figure 14
V _out 3 is the output of the third channel, and the transfer pulse φ _S2
Reset at time t _7, clamped at time t ₈ the transfer pulse phi _S3, samples and holds at time t ₉ the transfer pulse phi _S1. In the third channel, for a time t ₈ of time t ₇ and the clamp pulse phi _S3 of the reset pulse phi _S2 are simultaneous, unnecessary high output at the beginning of 1 horizontal period occurs. In order to remove this noise, the fall time t ₁₂ of the last pulse of the horizontal blanking period of the pulse φ _S3 may be delayed a little as shown in FIG. Reset time t ₁₀ and clamp time t ₁₁ at the end of the horizontal blanking period of the channel
Are generated simultaneously, which causes noise.

[Problems to be Solved by the Invention] As described above, in the conventional solid-state imaging device, the reset pulse and the clamp pulse are generated at the beginning of the horizontal period and the end of the horizontal blanking period of one of the channels. There is a fear that it will occur at the same time, so that the signal component is formed in a form in which the clamp potential and the reset potential are superimposed is the reference,
As a result, there is a problem that the level of the signal component becomes very large and a large output is generated.

The present invention has been made in order to solve such a conventional problem, and provides a solid-state imaging device including a driving unit that shifts the timings of reset and clamp pulses to eliminate the occurrence of noise during clamping. Is.

[Means for Solving the Problems] In order to achieve the above-mentioned object, a solid-state imaging device according to the present invention includes a charge-coupled device having first, second, and third parallel channel outputs; The phases of the transfer pulses of the first, second, and third channels are shifted by 120 ° outside the horizontal blanking period, and the transfer pulses of the first, second, and third channels are shifted by the first, second, and third channels. The potential levels of the output signals of the three channels are clamped respectively, and then the floating levels of the second, third and first channels are respectively set.
A signal processing circuit of a charge-coupled device, which is used as a pulse for resetting the charges of the diffusions, and further using the signal levels corresponding to the transferred charges of the third, first, and second channels as sample and hold, respectively; The fall order of at least the last pulse of each of the first, second, and third pulse horizontal blanking periods is defined by the horizontal blanking period of the charge transfer pulses of the first, second, and third channels. And a control means for shifting the pulse so that it is in the same order as the fall of the outer pulse.

[Operation] With the above-described configuration, the falling edge of the clamping pulse of each channel is always located in the low (L) period of the reset pulse, so that noise does not occur in the signal component. .

[Embodiment] FIG. 6 is a timing chart showing the timing by the driving method of the solid-state imaging device according to an embodiment of the present invention. As shown in FIG. 6, by slightly shifting the trailing edge of the last pulse of the transfer pulses φ _S1 , φ _S2 , and φ _S3 during the horizontal blanking period, driving is performed so that reset and clamp are not applied simultaneously.

Specific timing charts of the embodiment of the present invention will be described below with reference to FIGS. 7 to 11.

FIG. 7 shows an embodiment in which the transfer pulses φ _S1 , φ _S2 , and φ _S3 are three-phase driven even during the horizontal blanking period in order to obtain the above-mentioned driving timing. As a result, the transfer pulses φ _S1 , φ _S2 , and φ _{S3 in} the last part of the horizontal blanking period are generated with different timings.

8 and 9 show a method in which the trailing edges of the transfer pulses φ _S1 , φ _S2 , and φ _S3 in the horizontal blanking period are slightly shifted. In FIG. 8, the falling timing of each transfer pulse at the end of the horizontal blanking period is shifted by changing the width of each transfer pulse φ _S1 , φ _S2 , φ _S3 .

Further, in FIG. 9, each transfer pulse φ _S1 , φ _S2 , φ _S3 is delayed little by little with respect to the transfer pulse of the previous channel to obtain the falling timing of each transfer pulse.

Figures 10 and 11 show the usage in which the trailing edge of the last pulse in the horizontal blanking period is at least slightly shifted. 10th
In the figure, the timing of the driving means according to the present invention is obtained by delaying the last pulse of φ _S1 , φ _S2 , and φ _S3 of each transfer pulse with respect to the transfer pulse of the previous channel.

Even at the timing of the driving means of the present invention, no problem occurs in the charge transfer of the conversion unit from the vertical CCD to the horizontal CCD.

[Advantages of the Invention] According to the present invention, it is possible to remove noise that has conventionally occurred at the beginning of the horizontal period or at the end of the horizontal blanking period, and it is also possible to drive the CDS circuit by the transfer pulse of the CCD.

[Brief description of drawings]

FIG. 1 is a diagram of a correlated double sampling circuit (CDS circuit) provided at the final stage of each horizontal shift register of the conventional and the solid-state image pickup device of the present invention, and FIG. 2 is a timing showing the output and drive pulse of FIG. The chart in Fig. 3 shows the phase of the transfer pulse of the 1st, 2nd and 3rd channels with 3-channel output.
A diagram showing an example of a portion where charges are transferred from the vertical CCD portions A, B, C of the CCD that is shifted by three degrees and driven in three phases to the horizontal CCD portions a, b, c,
FIG. 4 is a diagram showing the drive pulses of the CCD of FIG. 3, FIG. 5 is a diagram showing the potential profiles of Virtual Phase and Clocked Phase, and FIG. 6 is a diagram showing a solid-state image pickup device according to an embodiment of the present invention. Timing charts showing timings according to the driving method, FIG. 7, FIG. 8, FIG. 9, FIG. 10, and FIG. 11 are concrete timing charts of transfer pulses in the embodiment of the present invention, respectively, and FIG. FIG. 14, FIG. 15 and FIG. 15 are timing charts of transfer pulses for driving a conventional device, respectively. In the figure, 2,6,9: MOSFET 4: LPF, 5, 9: Capacitor 7, 10: Amplifier φ _RS : Reset pulse φ _CL : Clamp pulse φ _SH : Sample hold pulse φ _S1 , φ _S2 , φ _S3 : Transfer pulse

Claims (1)

(57) [Claims] 1. A charge-coupled device having first, second, and third parallel channel outputs, and the phase of each transfer pulse of the first, second, and third channels is 120 outside the horizontal blanking period.゜ shift,
The transfer pulses of the first, second, and third channels clamp the potential levels of the output signals of the first, second, and third channels, respectively, and then the second, third, and first channels, respectively.
A signal processing circuit of a charge-coupled device that resets the charges of the floating diffusions of the channels, and further uses the signal levels corresponding to the transferred charges of the third, first, and second channels as sample and hold pulses, respectively. And the order of the trailing edges of at least the last pulse in the horizontal blanking period of the first, second, and third pulses is the same as that of the charge transfer pulses of the first, second, and third channels. A solid-state image pickup device comprising: a control unit that shifts the pulse so that the pulse falls outside the horizontal blanking period in the same order.