JPH0474797B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a refresh control device, and specifically to a refresh control device that realizes a high-speed image memory device that can correspond to the speed of a video signal.

[Technical background of the invention and its problems]

An image memory device configured with dynamic RAM needs to refresh its contents at regular time intervals. When displaying an image as dot information on a CRT display, reading from the image memory is continued during the display period. For that time, CRT
For example, if the video signal driving the display is an NTSC signal, one line takes about 53 μs (microseconds; an effective screen during one horizontal scanning period), and the image memory is continuously accessed during this period.

Since a dynamic RAM with a capacity of 16k x 1 bit is normally refreshed once every 16 microseconds, it is necessary to refresh three times while displaying one line.

Memory access for display display is
Since the vertical and horizontal distances between each dot are 1:1 on the CRT, the effective screen is 483 dots vertically and 644 dots horizontally, and each dot is printed at a rate of approximately 82 nanoseconds/byte. (NTSC) Conventionally, the memory speed was increased so that memory access and refresh operations during display could be performed in parallel. In other words, in order to achieve this high speed, a method is usually used in which 4 bytes are accessed simultaneously, but in order to achieve a higher speed at which memory refresh can be performed, 5 or more bytes must be accessed simultaneously. Normally, when accessing multiple bytes at the same time, 2 ^N (N=1, 2,
3...) as the number of bytes, 8 or 16
This results in simultaneous byte access. This results in an increase in the number of cables and further increases in mounting, which increases costs and further reduces reliability.

[Purpose of the invention]

The present invention has been made based on the above-mentioned circumstances, and the number of refresh requests is memorized whenever a refresh is executed while the display is being displayed and the effective screen range is being scanned, and the number of refresh requests is stored during the blanking period. It is an object of the present invention to provide a refresh control device capable of obtaining a high-speed image memory device that can cope with the speed of a video signal while executing a predetermined memory refresh by having a configuration in which refresh is performed as many times as the number of times that memory refresh has not been performed. do.

[Summary of the invention]

In the present invention, the refresh control device is configured with the circuit shown below, and the refresh is not executed while the display is being displayed and the effective screen range is being scanned, but the number of refresh requests is memorized, and the number of refresh requests is stored during the blanking period. By performing refresh the number of times that was not executed during the execution, a memory with the minimum necessary speed is constructed.

(1) A request circuit that generates a refresh request at regular time intervals; (2) a counter that counts the number of times a refresh request is not accepted by the memory and returns the count to the original value each time a refresh request is accepted by the memory; (3) ) A gate that outputs a refresh request signal to the memory when the counter is not "0" and the memory is in a state where refresh operation is possible. This eliminates the need for simultaneous 8-byte access as described above, and allows the memory to be accessed in 4-byte simultaneous access mode. Therefore, it is possible to realize a high-speed image memory device that can cope with the speed of video signals by using conventional hardware such as cables.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is an oscillator, which issues a memory refresh request at fixed time intervals. 2 is an AND circuit. The above oscillator 1 is connected to the AND circuit 2.
In addition to the output, a signal is supplied from the memory 7, which will be described later, via the line 9, and the AND gate 2 only receives a refresh request when the memory 7 can accept the refresh request.
It has the ability to pass through. 3 is a counter circuit. The counter circuit 3 counts refresh requests by obtaining an output from the oscillator 1, and returns the count by one each time a refresh operation is performed. The output of this counter 3 is connected to one input terminal of the AND gate 5.

4 is a refresh request generation circuit. The refresh request generation circuit 4 obtains an output from the memory 7 every time memory access becomes possible (READY).
This is the logic for generating the next memory refresh request. This refresh request generation circuit 4
The output is connected to the other input terminal of the AND gate 5. In the AND gate 5, the count of the counter circuit 3 is not "0". That is, when there is a refresh request that cannot be accepted in the memory 7, it has a function of passing the request output from the refresh request generating circuit 4. The output of this AND gate 5 is connected to one input terminal of an OR gate 6. or gate 6
The AND gate 2 output is supplied to the other input terminal of the . OR gate 6 outputs memory 7
This is supplied as a refresh request signal. Reference numeral 7 represents a memory such as an image memory device, which is constituted by a dynamic RAM, and 8 represents a CRT display for displaying data stored in the memory 7.

In the figure, 9 is a signal line through which a READY signal indicating that the memory 7 can be accessed (refreshed) is propagated, and 10 is a signal line through which a message indicating that the memory 7 is currently being refreshed is propagated.
Both 9 and 10 are emitted from the memory 7. or,
Reference numeral 11 denotes a signal line through which a signal indicating that the count by the counter circuit 3 is not "0" is transmitted.

FIGS. 2a and 2b and FIG. 3 are timing charts showing the operation of the embodiment of the present invention. The numbers shown in FIGS. 2a and 2b correspond to each block in FIG. 1 and indicate the respective outputs. The timing chart in Figure 3 shows the scanning line R, refresh request (REF) in order from the top.
REQ) and refresh cycle (REF CYC).

Hereinafter, the operation of the embodiment of the present invention will be explained in Fig. 2 a and b.
A detailed explanation will be given along the timing chart shown in .

Timing chart a explains the timing when a refresh request occurs when the memory 7 is in an operable state. Oscillator 1 output is
When a memory refresh request is made, ie, a request is made to the memory 7 via the OR gate 6, the counter circuit 3 provides an output as shown on line 11. At this time, since the memory is in READY state (point A), refresh is performed.
The counter circuit 3 is decremented by "1" and immediately reset. Also, as shown at point B, when the memory refresh operation is completed, memory 7 becomes READY.
state, and the refresh request generation circuit 4 issues a refresh request. However, since this is a state where there is no output as shown by point C in the figure, the AND gate 5 works and no output appears. Therefore, no output appears from the OR gate 6, and the refresh request does not reach the memory 7.

Next, along timing chart b, the operation when the CRT display device 8 accesses the memory 7 immediately before a refresh request will be explained. As shown at point D in the figure, the CRT display device 8 is accessing the memory 7 and is BUSY.
The output of the oscillator 1 generated in this state is blocked by the AND gate 2 and does not become a refresh request. (Point E) However, this signal acts to count up the counter circuit 3, and the resulting output appears. After the access by the CRT display device 8 is completed, the memory is displayed as shown at point F.
When READY is reached, a refresh request is issued from the refresh request generator 4 as shown at point G, and at this time, the output of the counter circuit 3 (point H) becomes a refresh request through the AND gate 5 and the OR gate 6, and the refresh request is sent to the memory 7. is transmitted to. (Point J) Since the memory is READY at this time, refreshing is performed and the output of the counter circuit 3 is reset as shown at point K. When the refresh is completed, a refresh request is output again as shown at point L, but since the count by the counter circuit 3 is "0" (point M), it is not transmitted to the memory 7 as a refresh request.

As explained above, the request signal output from the oscillator 1 while the memory 7 is BUSY is temporarily stored, and the refresh request generation circuit 4 outputs the refresh request until the number of refresh executions becomes equal to the number of requests, and thereby the dynamic RAM refresh can be executed within a predetermined time. This will be explained below along the timing chart shown in FIG.

That is, if memory refresh is required three times during the display period, that is, if a refresh request is issued three times during the display period, the refresh is executed three times in succession after the blanking period begins. (Refresh 0 to 2) [Effects of the Invention] As explained above, according to the present invention, while the CRT display is being displayed, when the effective screen range is being scanned, the number of refresh requests is stored without executing refresh. A memory with the minimum required speed can be provided by refreshing the memory as many times as it was not performed during the blanking period. As a result, there is no need to simultaneously access 8 bytes of memory as described above, and the initial purpose can be achieved with a conventional memory configuration in which 4 bytes are accessed simultaneously. Therefore, hardware such as cables can be made smaller and reliability is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention, and FIGS. 2a, b, and 3 are timing charts showing the operation of the invention. 1... Oscillator, 3... Counter circuit, 4... Refresh request generation circuit, 2, 5, 6... Gates, 7... Memory, 8... CRT display device.

Claims (1)

[Claims] 1. A refresh request means that issues a refresh request to a memory storing display data at regular time intervals, counts the number of times the memory refresh request is not accepted by the memory, and causes the refresh request signal to be accepted by the memory. and a control means that outputs the refresh request signal to the memory when the count by the counter means is not zero and the memory refresh operation is possible. Refresh control device.