JPH0476639B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a clock that switches and displays information other than time, such as temperature and humidity, on the same display section, and in particular, The present invention relates to information that allows a user to select only necessary information from among a plurality of pieces of information and to switch and display the information in the order desired by the user.

(b) Conventional technology As a conventional clock of this type,
There was one shown in Publication No. 125898.

This timepiece used a ring counter as a display switching circuit that sequentially outputs signals in response to switch operations.

(c) Problems to be solved by the invention The display switching order in the above-mentioned prior art is fixed from the beginning, and users may become dissatisfied with the switching order depending on the usage environment, or create unnecessary display modes. The problem was that even if there was a problem, you had to be patient and use it.

(d) Means for Solving Problems The present invention provides a time display section; a time clock section; a plurality of additional function sections having functions other than time measurement; a first switch; the time clock section; a display selection circuit that selects an output signal from any one of a plurality of additional function units and supplies the time display unit; a digital watch that corresponds to the time measurement unit and the plurality of additional function units; Code signals that can read code signals
a ROM; a first code readout circuit that reads code signals from the code signal ROM in a predetermined order; and a first code reading circuit having a number of storage areas corresponding to the number of the time clock sections and additional function sections; a code signal storage circuit that sequentially stores code signals in the storage area when a predetermined code signal is output from the readout circuit; and a display selection circuit that reads out the stored contents of the code signal storage circuit in a predetermined order. a second code reading circuit for supplying a second code reading circuit; a display switching circuit for displaying the stored content of the code signal storage circuit on a display section instead of the output content of the display selection circuit; and a readout code number detection circuit that compares the readout code number with the readout code number of the second code readout circuit and returns the readout operation of the second code readout circuit to the initial state when they match.

(e) Examples Examples of the present invention will be described below based on the drawings.

First, the operations for changing the display of a digital watch according to an embodiment of the present invention, changing the switching order, and changing the display after the change are shown in FIGS. 2A to D, 3A to G, and 4A to C. I will explain using

Each figure shows a display section 1 and switches α, β, and γ.

The display section 1 includes four display areas 2 to 8 made up of segments arranged in a sun shape, a colon display area 10 made up of dots 10a and 10b that can be turned on and off independently, and a display area 10 that shows the order of display. A display area 12 consisting of sun-shaped segments showing ℃ and %
Display areas 14 and 16 are provided for displaying.

In addition, switch α is a switch for setting the display switching correction state, switch β is a switch for setting the display function during display switching and correction,
The switch γ is a switch for selecting a display function during correction.

The initially set display switching order is
The order is shown in Figures A to D. That is, seriously the second
The time is displayed as shown in Figure A, and when the switch β is operated to change the display, the temperature is then displayed as shown in Figure 2B. Furthermore, when the switch β is operated, the discomfort index is displayed as shown in FIG. 2C, and when the switch is operated next, the humidity is displayed as shown in FIG. 2D.

In this way, according to the initially set order, the display changes cyclically in the order of time - temperature - discomfort index - humidity by operating the switch β.

Next, an explanation will be given of an operation procedure for changing the order and the number of display functions even though the display switching is set in the above order.

When the switch α of the clock is operated in the normal display state as shown in FIG. 3A, the entire display is cleared as shown in FIG. 3B.

Here, when the switch γ is operated once as shown in FIG. 3C, a symbol "a" representing a display function is displayed in the display area 2. The symbol a represents time, b represents temperature, c represents discomfort index, and d represents humidity. Further, "1" is displayed in the display area 12,
This indicates that the first display function in the switching order can be set.

Furthermore, in response to the operation of this switch γ, the display will be a.
-d is cyclically corrected, so a desired display function can be selected by the number of times the switch γ is operated.

Next, when switch β is operated as shown in FIG. The second display function becomes settable.

If the switch γ is operated twice as shown in FIG. 3E, "b" is displayed in the display area 4.
At this time, when switch β is operated as shown in FIG. 3F, display function b is set second in the display order.

As a result, the display order becomes a-b as shown in FIG. 3F, and is set in the order of time and temperature. Therefore, when the switch α is operated to change the display to the normal state as shown in FIG. 3G, the time is first displayed as shown in FIG. 4A, and then the time is displayed as shown in FIG. 4B.
As shown in FIG. 4C, when the switch β is operated once, this display changes to the temperature display, and when the switch β is further operated as shown in FIG. 4C, the display returns to the time display.

In this way, the user can freely modify the display switching order and the number of display functions.

Next, the circuit configuration of the timepiece according to the embodiment will be explained using FIG.

20 is an oscillator that outputs a high frequency signal; 22 is a frequency dividing circuit that divides this high frequency signal as appropriate; 24
is a clock circuit which inputs the output signal of the frequency dividing circuit 22 and measures time. 26 is a temperature detection circuit, 28 is a humidity detection circuit, and 30 is a discomfort index detection circuit that detects a discomfort index from the output signals of the temperature detection circuit 26 and humidity detection circuit 28.

32 is an initial reset circuit which outputs an initial reset signal _F1 when a battery or the like is inserted, and also outputs an initial set signal _F3 for setting the display switching order to a fixed order in the initial state.

34 are operation signals E ₁ , E ₂ ,
It inputs _E3 and outputs signals _E4 , _E5 , _E6 , _E7 , and _E8 .

Reference numeral 36 denotes a selection code ROM that stores alphanumeric codes a to d corresponding to each display function displayed on the display section 1 when modifying and setting the display function.

38 inputs signals F ₃ and E ₈ and selects the code
This is a first code reading circuit that reads the selection code from the ROM 36.

40 is a code storage circuit that sequentially stores the selection codes read by the first code reading circuit 38.

42 is a second code reading circuit that sequentially reads out the stored codes from the code storage circuit 40.

44 stores the number of code signals stored in the code storage circuit 40, and in response to a switch operation, the second code reading circuit 42 reads the code signal from the code storage circuit 40.
This is a read code number detection circuit that compares the number of code signals read from the second code read circuit 42 and resets a counter in the second code read circuit 42 when they match.

46 is a driver control circuit, which inputs the signal _J1 from the second code reading circuit 42 and outputs the control signal.
It outputs L ₁₄ to L ₁₇ , L ₁₀ , L ₁₈ , L ₁₁ , and L ₁₃ .

48 is a multiplexer as a display selection circuit which inputs the signals A, B, C, and D and outputs an input signal of the display function corresponding to the code signal J ₁ ; 50 is the output signal N of this multiplexer 48 and the code storage circuit 40; Input the code signal M from , and input the signal E ₁
The multiplexer serves as a display switching circuit that switches and outputs this input signal according to the state of the display.

A decoder 52 receives the output signal of the multiplexer 50 and converts it into a code signal for display according to the states of the signals J ₂ and J ₃ .

A driver 54 inputs a signal from the decoder 52 and a signal from the driver control circuit 46 to drive the display section 1.

Next, an outline of the operation of the display switching circuit of this embodiment having the above configuration will be explained.

Normally, the switch α is in an off state, so that the multiplexer 50 is in a state to output the signal N, and the driver control circuit 46 is also in a state to output a control signal for normal display.

Therefore, when the switch β is operated to generate a pulse in the signal _E7 , the second code reading circuit 4
2 reads out the code signal in accordance with the switching order stored in the code storage circuit 40 in response.
In this code storage circuit 40, in an initial state, the first code reading circuit 38 reads the selected code ROM ₃ in response to the signal F3 from the initial reset circuit 32.
Codes to be read from 6 are stored in a predetermined order.

The readout code number detection circuit 44 detects whether the code storage circuit 40 is stored in response to the signal _I1 from the code storage circuit 40 when the code storage circuit 40 is set to a predetermined initial state by the signal _F3 . Memorize the number of codes. When the number of codes read by the second code reading circuit 42 matches the stored value, the counter in the second code reading circuit 42 is reset by the signal _K1 to return to the initial state.

In this way, the second code reading circuit 42
The code read out is applied to multiplexer 48 and driver control circuit 46 as signal _J1 . This multiplexer 48 switches and outputs, as a signal N, a signal whose content is responsive to the content of the signal _J1 . Furthermore, while the signal E ₁ is at L level, the multiplexer 50 outputs the signal N from the multiplexer 48 and applies it to the driver 54 via the decoder 52 .

This driver 54 is controlled by a control signal from the driver control circuit 46, and responds to the signal _J1 outputted by the second code reading circuit 42 in response to the operation of the switch β. The display unit 1 is sequentially driven (FIGS. 2A to 2D).

On the other hand, when the switch α is turned on to enter the display change correction state, the signal _E1 becomes H level and the multiplexer 50 and driver control circuit 46 are switched to the display change correction state. This multiplexer 50 becomes in a state of outputting a signal M indicating the stored contents of the code storage circuit 40, and this signal is applied to the driver 54 via the decoder 52. However, since the memory of the code storage circuit 40 is once cleared by the pulse generated in the signal _E5 when the switch α is turned on, nothing is displayed on the display section 1 (FIGS. 3A and 3B).

When switch γ is operated in this state (Fig. 3C), a pulse is generated in the output signal _E8 of the switch circuit 34, and the first code reading circuit 38 receives the signal
Codes are sequentially read from the selection code ROM 36 in response to _E8 . This read code is applied as a signal _H4 to the code storage circuit 40 and is stored as the first code in the switching order.

When the switch β is operated (FIG. 3D), a pulse is generated in the signal E ₆ and is applied to the code storage circuit 40.

As a result, the second switching order becomes modifiable, and at the same time, in response to a pulse generated in the signal _I1 , the readout code number detection circuit 44 counts that the code storage circuit 40 has stored a code. do. Here, the second switching order can be corrected by operating the switch γ again and reading a desired code from the selection code ROM 36 (FIG. 3E).

Further, when the switch β is operated, the third position in the switching order becomes modifiable, and at the same time, the readout code number storage circuit 44 counts that the code storage circuit 40 has stored two codes (FIG. 3F).

During such a switching operation, the stored contents of the code storage circuit 40 are always applied to the driver 54 via the multiplexer 50 and decoder 52, and the driver control circuit 46 is also in the switching order correction state, so the display section 1 stores the stored contents of the code storage circuit 40, that is, the switching order, a, b,
c, d (Figures 2 and 3).

In this embodiment, it is assumed that the first and second switches in the switching order are modified and set, and nothing is set for the third and fourth switches. Even in such a case, the readout code number detection circuit 44 stores the number of codes stored in the code storage circuit 40, so when the switch β is operated in the normal state, the display will change between the set first and second codes. Things will be displayed cyclically (Figure 4).
Details regarding this point will be described later.

Next, the detailed circuit configuration and operation of each circuit shown in FIG. 1 will be explained.

FIG. 5 is a diagram showing the circuit configuration of the initial reset circuit 32 and the switch circuit 34, and FIGS. 6 and 7 are time charts thereof.

The initial reset circuit 32 includes a reset pulse generating circuit 60 consisting of a resistor, a capacitor, and an inverter that outputs a pulse when a battery is inserted, and a flip-flop (hereinafter abbreviated as "FF") that inputs the output signal _F1 to the reset input R. 62, an AND gate 64 which inputs the signal from its output and the clock signal _φ1 , and outputs the signal _F3 , inputs the signal _F1 and the output signal _E4 of the switch circuit 34, and outputs the signal _F7.
an OR gate 68 which outputs the signal _E6 , an FF70 which inputs the signal E6 to the clock input φ and a signal _F7 to the reset input R, and an AND gate which inputs the signal _F5 from its output and the output signal _E6 of the switch circuit 34. A gate 72, a one-shot multivibrator 74 which receives its output signal and generates a pulse in the signal _F6 , and output signals _K3 , _K4 , _K5 of the readout code number detection circuit 44 are inputted, and these signals are input to a predetermined value. The decoder 76 outputs a pulse as the signal _F8 when the state is reached.

As shown in FIG. 6, this initial reset circuit 32 generates a pulse in the output signal _F1 of the reset pulse generating circuit 60 when a battery or the like is inserted.
When a pulse is generated in this signal F ₁ , the FF 62 is reset, and the signal _{E 2} from its output becomes H _level . to occur.

The pulse generated in the signal F ₃ is generated in the output signal I ₁ of the code storage circuit 40, which will be described later, and is applied to the counter in the read code number detection circuit 44. In this embodiment, when the counter in the read code number detection circuit 44 counts the fourth pulse generated in the signal _F3 , the output signal
The decoder 76 in the initial reset circuit 32 which receives K ₃ , K ₄ and K ₅ outputs a pulse on its output signal F ₈ .

The FF 62 is set by the pulse generated in the signal _F8 , and its output becomes L level. Therefore, the AND gate 64 is closed, and the signal F ₃
is held at L level.

Further, the pulse generated in the signal F ₁ is generated in the signal F ₇ via the OR gate 68. This signal F ₇
The pulse generated in the reset input R of FF70
is applied to reset it. For this reason, F.F.
The output signal F ₅ of 70 becomes H level, and the AND gate 72 is kept open.

The switch circuit 34 provides an operation signal for the switch α.
A one-shot multivibrator 78 that outputs a pulse when _E1 becomes H level, an inverter 80 that inverts signal _E1 , and the inverted signal.
A one-shot multivibrator 82 that inputs E ₁ , an AND gate 84 that inputs the operation signal E ₂ of switch β and signal E ₁ , and an AND gate 86 that inputs signal E ₂ as it is and inverted signal E ₁ .
It consists of an AND gate 88 which inputs the operation signal _E3 of the switch γ and the signal _E1 .

As shown in FIG. 7, when the switch α is turned on and the signal _E1 becomes H level, a pulse is generated in the output signal _E5 of the one-shot multivibrator 78, and AND gates 84 and 88 are opened. become.

Therefore, when the switches β and γ are operated, the pulses generated in the operation signals E ₂ and E ₃ are generated in the output signals E ₆ and E ₈ of the AND gates 84 and 88, respectively.

Furthermore, the pulse generated in the signal _E5 is used to reset the shift register in the code storage circuit 40 when the switching order is corrected so that the first change in the switching order can be corrected, and the pulse generated in the signal _E6 is The pulses are for sequentially modifying the display order as described above, and the pulses generated in the signal _E8 are for selectively modifying the display function.

The pulse generated in the signal _E6 is also generated at the output of the AND gate 72 in the initial reset circuit 32, and upon receiving this pulse, the one-shot multivibrator 74 generates a pulse in its output signal _F6 . The pulse generated in this signal F ₆ is
The counter in the read code number detection circuit 44 is reset to the initial state. The pulse generated in signal _E6 is applied to the clock input φ of RR70, and FF7 is applied in synchronization with the falling edge of this pulse.
0 is set, and its output signal _F5 goes to L level, closing the AND gate 72.

On the other hand, when switch α is turned off, the signal
_E1 becomes L level, the output of inverter 80 which inverts this becomes H level, and in response, one shot multivibrator 82 outputs a pulse to its output signal _E4 . This pulse is generated via OR gate 68 in initial reset circuit 32 to signal _F7 and is applied to reset input R of FF 70 to reset it. For this reason, FF7
The output signal F ₅ of 0 becomes H level and opens the AND gate 72 again.

Further, when the signal _E1 becomes L level, the AND gates 84 and 88 are closed, and the AND gate 8
Only 6 is open.

Therefore, only the pulse generated in the operation signal E ₂ of the switch β is the output signal E ₇ of the AND gate 86.
occurs in

The pulse generated in this signal _E7 is for display switching in the normal display state.

FIG. 8 is a diagram showing the circuit configuration of the selection code ROM 36 and first code reading circuit 38 shown in FIG. 1, and FIG. 9 is a time chart thereof.

The selection code ROM 36 consists of ROMs 90 to 96 that store codes corresponding to display functions of time, temperature, discomfort index, and humidity.
6 is a 2-bit signal G ₁ to indicate each function.
Outputting G ₄ .

The first code reading circuit 38 includes an OR gate 98 that inputs the signal _F3 from the initial reset circuit 32 and the signal _E8 from the switch circuit 34, and an OR gate 98 that inputs its output signal _H1 to the clock input φ, and a code storage circuit. Reset signal I ₁₈ from 40 input R
counter 100 and its outputs Q ₀ , Q ₁
The multiplexer 102 inputs the signals H ₂ and H ₃ from the ROM 36 and the signals G ₁ to _{G 4} from the selection code ROM 36 and switches and outputs the signals G ₁ to _{G 4} according to the states of the signals H ₂ and H ₃ . has been done.

As shown in FIG. 9, the signal _I18 includes the output signal of the initial reset circuit 32 and the switch circuit 34.
A pulse is generated when a pulse is generated at F ₁ and F ₅ (that is, when a battery or the like is inserted or when switch α is turned on). Therefore, the first code reading circuit 38
The counter 100 is reset in the initial state, and its output signals H ₂ and H ₃ are both at L level.

In this way, when the signals H ₂ and H ₃ are both at the L level, the multiplexer 102 is in a state where it outputs the code signal G ₁ (00) that matches the states of the signals H ₂ and H ₃ .

Next, the initial reset circuit 32 and the switch circuit 3
When a pulse occurs in the output signals F ₃ and E ₈ of the OR gate 98 (i.e., when automatically setting to a predetermined order after initial reset or when the switch γ is operated during correction), the pulse is generated in the output signal H ₁ of the OR gate 98. A pulse is generated.

The counter 100 sets its output signal _H2 to H level in synchronization with the falling edge of the first pulse generated in _the signal H1.

Therefore, the signals H ₂ and H ₃ become H and L levels, respectively, and the multiplexer 102 to which they are input
becomes a state in which a code signal G ₂ (01) matching the states of signals H ₂ and H ₃ is output.

Also, when a pulse occurs in signal H ₁ next,
The counter 100 advances its count and outputs a signal
Switch H ₂ and H ₃ to L and H levels.

This causes multiplexer 102 to
A state is reached in which a signal G ₂ (10) matching H ₂ and H ₃ is output. Similarly, when a pulse is generated in the signal H ₁ and the output signals H ₂ and H ₃ of the counter 100 become H and L levels, the multiplexer 102 outputs the signal G ₄
(11) will be output.

In this way, by applying the signal F ₃ or E ₈ to the first code reading circuit 38, the selected code is read out.
Code signals G ₁ to _{G 4} are sequentially read out from the ROM 36 and output as signal H ₄ .

FIG. 10 is a diagram showing the circuit configuration of the code storage circuit 40 shown in FIG. 1, and FIG. 11 is a time chart thereof.

The code storage circuit 40 includes an OR gate 104 to which signals F ₁ and E ₅ are input, an OR gate 106 to which signals F ₃ and E ₆ are input, and an output signal of OR gate 104.
Input _I18 to reset input R and OR gate 1
A _shift register 105 inputs the output signal I ₁ of 06 to the clock input φ, and inputs the signal H ₄ from the first code reading circuit 38 and the output signals I ₂ to I ₅ of the shift register 108, respectively. ~ _I5
gate circuits 110 to 116 that are opened and closed by;
AND gate 1 which inputs the output signals I ₂ to I ₅ of the shift register 108 into each one input terminal and inputs the output signal I ₁ of the OR gate 106 into each other input terminal.
18 to 124 and output signals I ₆ to I ₉ of gate circuits 110 to 116, respectively, and gate 1
A presettable counter 126 which inputs output signals _I10 to _I13 of 18 to 124 to each preset input P.
132, and a decoder 134 which receives the output signals _I14 to _I17 and outputs the signal M.

As shown in FIG. 11, when a pulse occurs in the output signal _I18 of the OR gate 104 (when a battery or the like is inserted or switch α is turned on),
Since the shift register 108 is reset, its output signal _I2 is at H level in the initial state. When this signal I ₂ is at H level, the gate circuit 110 to which it is input is in an open state and generates the signal H ₄ as its output signal I ₆ .

This signal H ₄ includes the code signals G ₁ to _{G 4} indicating the display function as described above, and as shown in FIG. I ₆ also code signal
It will include G ₁ .

When the output signal _I6 of the gate circuit 110 includes a code signal, the presettable counter 126 unconditionally outputs the signal _I6 , and otherwise the presettable counter 126 outputs the preset value. It shall be.

When the output signal _I2 of the shift register 108 is at H level, the gate circuit 110 is also in an open state, and when a pulse is generated in the output signal _I1 of the OR gate 106 (after the initial reset, the gate circuit 110 is automatically set in a predetermined order). or when switch β is operated during correction), the output signal of AND gate 118
A pulse also occurs at _I10 .

When the pulse generated on this signal I ₁₀ falls,
The presettable counter 126, which inputs this to the preset input P, is set to the state of the signal _I6 at this time (ie, the code signal _G1 ). As a result,
The output of the presettable counter 126 is in a state where it outputs the code signal _G1 .

Furthermore, when a pulse is generated in the signal _I1 , the output signal I2 of the shift register 108 becomes L level in synchronization with the falling edge of the pulse, and the output signal _I2 changes to the L level instead.
_I3 becomes H level.

When this signal _I3 becomes H level, gate circuit 1
12 and the AND gate 120 are opened, and the signal H ₄ is generated at the output signal I ₇ of the gate circuit 112. When a pulse is generated again in the signal _I1 , this pulse is generated in the output signal _I11 of the AND gate 120, and in synchronization with the fall of this pulse, the presettable counter 128 outputs the current signal _I7 . (code signal G ₂ in this example), and signal I ₁₅ includes code signal G ₂ .

Similarly, each time a further pulse is generated in the signal I ₁ , the shift register 108 successively sets the output signals I ₄ and I ₅ to H level in synchronization with the falling edge of the pulse, thereby causing the gate circuit 114 and the AND gate 122 or gate circuit 116 and AND gate 12
4 becomes open, and then the states of signals I ₈ and I ₉ at this time are set in presettable counters 130 and 132, respectively, by the fall of the pulse generated in signal I ₁ . When the codes indicating the display function are sequentially set in the presettable counters 126 to 132 in this way, the output signals I ₁₄ to I ₁₇ are applied to the second code readout circuit 42 and simultaneously sent through the decoder 134. is converted into a signal E indicating the order of display functions and applied to the multiplexer 50.

In addition, the output signal I ₃ of the shift register 108,
I ₄ and I ₅ are applied to the driver control circuit 46 in order to turn on and off the display areas 4, 6, and 8 during correction according to the operation of the switch β.

FIG. 12 is a diagram showing the circuit configuration of the second code reading circuit 42 and reading code machine detection circuit 44 shown in FIG. 1, and FIGS. 13 and 14 are time charts thereof.

This second code reading circuit 42 includes a counter 136 which inputs the signal E ₇ from the switch circuit 34 to a clock input φ, and its output signals J ₂ , J ₃ , J _{4 .}
The signal from the code storage circuit 40 depending on the state of
The multiplexer 138 switches and outputs _I14 to _I17 .

The read code number detection circuit 44 also includes a counter 140 which inputs the signal I ₁ from the code storage circuit 40 to a clock input φ, and its output signal K ₃ ,
A matching circuit that inputs K ₄ , K ₅ and the output signals J ₂ , J ₃ , J ₄ of the counter 136 in the second code reading circuit 42, compares them, and generates a pulse in the signal K ₆ when they match. 142 and initial reset circuit 3
An OR gate 144 inputs the signal F ₁ and the signal K ₆ from the counter 136 and applies the output signal K ₁ to the reset input R of the counter 136, and the signal from the initial reset circuit.
Input F ₁ and F ₆ and output signal K ₂ to counter 140
and an OR gate 146 which is applied to the reset input R of the circuit.

The counters 136 and 140 are reset in the initial state by a pulse generated in the signal F ₁ as shown in FIG. 13, and the output signals J ₂ and
J ₃ , J ₄ and K ₃ , K ₄ , K ₅ are all at L level.

At this time, the multiplexer 142
A signal _I14 corresponding to the states of _J2 , _J3 , and _J4 is output.
When a pulse is generated in the signal _I1 (a pulse for automatically setting in a predetermined order after the initial reset), the code storage circuit 40 is activated as described above.
The output signals I ₁₄ -I ₁₇ are each latched containing code signals G ₁ -G ₄ in synchronization with the four pulses generated in signal I ₁ . In addition, the counter 140 inputting this signal _I1 to the clock input φ is
When the count advances and the fourth pulse is counted, the output signals K ₃ , K ₄ , and K ₅ become L, respectively.
Set it to L and H levels.

After the display switching order is automatically set in this way, when the switch β is operated to generate a pulse in the signal _E7 , the counter 136 in the second code reading circuit 42 is synchronized with the falling edge of this pulse. to switch the states of the output signals J ₂ , J ₃ , and J ₄ .

The multiplexer 138
signals I ₁₅ , I ₁₆ , I ₁₇ sequentially according to the state of the output signals of
will be output respectively.

Therefore, if the signals I ₁₄ to I ₁₇ include code signals G ₁ to _{G 4} , respectively, as shown in FIG.
The code signals G ₁ to _{G 4} are sequentially generated as the output signal J ₁ of the multiplexer 138 .

At this time, the coincidence circuit 142 controls the counter 13
6,140 output signals J ₂ , J ₃ , J ₄ and K ₃ , K ₄ , K ₅
(in this embodiment, the counter 136 detects that the states _of
), a pulse is generated in the output signal _K6 . This pulse is generated on signal _K1 via OR gate 144 and applied to the reset input R of counter 136 to reset it. Therefore, if the switch β is continued to be operated, the display will change cyclically.

Next, as shown in FIG. 14, in the display change correction state, when the switch γ is operated to select the display function as described above, and the switch β is then turned on, the signal _F6 is turned on. A pulse is generated.
This pulse is passed through the OR gate 146 to the signal K ₂
is generated and applied to the reset input R of the counter 140 to reset it. When this switch β is operated, a pulse is also generated in the signal _I1 , and the counter 140 immediately after being reset counts this in synchronization with the falling edge of this pulse. Thus, when a pulse occurs in signal _I1 , counter 140 counts the number of pulses that occur. Therefore, after the correction is completed, if you operate switch β to generate a pulse on signal _E7 ,
The counter 136 counts this pulse and the count number of the counter 140 (2 in this example)
When there is a match, match circuit 142 generates a pulse on output signal _K6 , which resets counter 136. In this way, the display changes cyclically within the range of the number of display functions (number of counters 140) set at the time of correction.

FIG. 15 shows the driver control circuit 46 shown in FIG.
16 and 17 are time charts showing the circuit configuration.

This driver control circuit 46 inputs the signal J ₁ from the second code reading circuit 42 and outputs signals L ₆ to L that determine whether to turn on or off the display area when displaying the time, temperature, discomfort index, and humidity, respectively. ₉ and its output signals L ₆ to _{L 9}
AND gates 154 to 160 each input into one input terminal and a signal L ₁ obtained by inverting the signal E ₁ by an inverter 152 to each other input terminal to output signals L ₁₀ to L ₁₃ respectively, and a switch. circuit 34
FF16 which inputs the signals E ₅ and E ₄ from the FF to the set input S and reset input R, respectively, and outputs the signal L _2.
2 and an OR gate 164 that inputs signals E ₄ and E ₅ .
and its output signal is input to each reset input R, and a code storage circuit 40 is input to each set input S.
Input signals I ₃ , I ₄ , I ₅ from , and input signals L ₃ , L ₄ , L ₅
FF166, 168, 170 that outputs the signal
OR gate 17 that inputs L ₂ , L ₁₀ , L ₁₁ , and L ₁₂ and outputs signal L ₁₄ for lighting display area 2
2, an OR gate 174 which inputs signals L ₃ , L ₁₀ , L ₁₁ , L ₁₂ and outputs a signal L ₁₅ for lighting the display area 4, and signals L ₄ , L ₁₀ , L ₁₁ , L ₁₃ . An OR gate 176 that outputs a signal L ₁₆ for inputting and illuminating the display area 6, and a signal L 17 for inputting signals L ₅ , L ₁₀ , and L ₁₃ and outputting a signal L ₁₆ for illuminating the display area 8.
and an OR gate 18 which receives signals L ₁₀ and L ₁₁ and outputs a signal L ₁₈ for lighting the point below the colon in the display area 10.
It is composed of 0.

Now, as shown in FIG. 16, when the signal _E1 is at the L level and in the normal display state, the signal _L1 is at the H level, so the AND gates 154-
160 is in an open state. Here, if the signal _J1 applied to the decoder 150 includes the code signal _G1 for displaying the time, the decoder 150 sets the signal _L6 corresponding to the time display to an H level.

This H level signal L ₆ is applied to the AND gate 15
This causes the output signals _L14 to _L17 of the OR gates ₁₇₂ to 180 to all become H.
become the level.

Therefore, the display areas 2, 4, 6, 8, and 10 are all turned on, and the time is displayed as shown in FIG. 2A.

Further, when the signal _J1 changes to the code signal _G2 for displaying the temperature, the decoder 150 sets the signal _L7 corresponding to the temperature display to H level.

As a result, the output signal L ₁₁ of the AND gate 156
becomes H level, or gate 172-176,
180, the signals L ₁₄ to L ₁₆ and L ₁₈ go to H level, and the display areas 2, 4, 6, 10b (lower points),
14 lights up and the temperature is displayed as shown in FIG. 2B. Similarly, when the content of the signal J ₂ is code signals G ₃ and G ₄ indicating the discomfort index or humidity, the output signals L ₈ and L ₉ of the decoder 150 go to H level, respectively, and the AND gates 158 and 160 The output signals L ₁₂ and L ₁₃ are generated.

Therefore, the output signals L ₁₄ and L ₁₅ of the OR gates 172 and 174 go to H level and the display areas 2 and 4 turn on, or the output signals L ₁₆ and L ₁₇ of the OR gates 176 and 178 go to the H level and the display is displayed. Area 6,
8 and 16 are turned on, and the discomfort index and humidity are displayed, respectively, as shown in FIG. 2C or D.

On the other hand, as shown in FIG. 17, when the signal _E1 becomes H level and enters the switching order correction state, the signal
L ₁ becomes L level and gate 154-16
0 is a closed state.

Also, at this time, the pulse generated in the signal _E5 causes the FF162 to be set, and the other FF166 to
170 is reset. Therefore, only the output signal _L14 of the OR gate 172 becomes H level, and the display area 2 is turned on. As described above, the signals I ₃ , I ₄ , and I ₅ each go to H level in response to turning on the switch β during correction. When these signals I ₃ , I ₄ , and I ₅ go to H level, the respective FF
166, 168, 170 are set, which causes the output signals of OR gates 174, 176, 178 to
L ₁₅ , L ₁₆ , and L ₁₇ are sequentially brought to the H level, and display areas 4, 6, and 8 are sequentially turned on.

FIG. 18 is a diagram showing a circuit configuration of the driver 54 shown in FIG. 1.

As shown in the figure, this driver 54 is made up of subdivided drivers 182-198.
The drivers 182 to 188 convert signals from the decoder 52 into control signals from the driver control circuit 46.
When L ₁₄ to _{L 17} are at H level, the voltages are applied to the display areas 2, 4, 6, and 8 of the display unit 1 to light them up.

Further, the drivers 192 to 198 control the colons 10a and 10b of the display area 10 and the display areas 14 _{and 16} when the control signals L ₁₈ , L ₁₀ , L ₁₁ , and L 13 from the driver control circuit 46 are each at H level. It lights up.

Further, the driver 190 receives a signal from the decoder 52 and drives the display area 12.

In this way, this driver 182-188,1
Reference numerals 92 to 198 determine whether or not the drive signal is output or stopped by a control signal from the driver control circuit 46.

Further, the signal from the decoder 52 applied to the drivers 182 to 188 is a coded version of the signal from the multiplexer 50. This multiplexer 50 outputs the signal from the multiplexer 48 which switches and outputs the signals A to D including information on time, temperature, discomfort index, and humidity using the signal J ₁ when the input signal E ₁ is at the L level. E ₁
When is at H level, a signal M indicating the stored contents of the code storage circuit 40 is output.

Therefore, in the normal display state, a signal including information such as time is applied to the drivers 182 to 188 via the multiplexers 48 and 50 and the decoder 52, and in the switching order correction state, the signal is applied to the drivers 182 to 188 via the multiplexer 50 and the decoder 52. A signal containing the memory contents of the code storage circuit 40 is transmitted to the driver 182.
~188.

Further, a signal is applied from the decoder 52 to the driver 190, but this is because a signal indicating the display order is sent from the decoder 52 based on the signals J ₂ , J ₃ , and J ₄ output from the second code reading circuit 42. It is applied.

As described in detail above, in this embodiment, the switching order of display functions such as time, temperature, discomfort index, humidity, etc. and the number of functions can be freely changed.

In this embodiment, temperature and the like are used as information other than time, but other information such as alarm time, timer time, month and day, etc. may also be used.

(f) Effects of the Invention According to the present invention, the user can modify only the necessary modes in the order that is most convenient for the user according to the usage environment, etc., and the operability can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a display switching circuit of a digital watch according to an embodiment of the present invention, FIGS. Figure 5 showing each operation and display of display switching, display switching correction, and display switching after correction.
The figure shows the circuit configuration of the initial reset circuit and switch circuit shown in Fig. 1, and Figs.
FIG. 8 is a diagram showing the circuit configuration of the selection code ROM 36 and the first code reading circuit shown in FIG. 1. FIG. 9 is a time chart of the signals shown in FIG. 8. FIG. 10 is a time chart of the signals shown in FIG. 11 is a diagram showing the circuit configuration of the code storage circuit shown in FIG. 1, FIG. 11 is a time chart of the signals shown in FIG. 10, and FIG.
The figure shows the circuit configuration of the second code reading circuit and read code number detection circuit shown in FIG. 1, FIGS. 13 and 14 are time charts of the signals shown in FIG. 12, and FIG. Figures 16 and 17 show the circuit configuration of the driver control circuit shown in Figures 16 and 17.
The figure is a time chart of the signal shown in Fig. 15.
FIG. 8 is a diagram showing the circuit configuration of the driver shown in FIG. 1. DESCRIPTION OF SYMBOLS 1... Display part, 20... Oscillator, 22... Frequency division circuit, 24... Time measurement circuit, 26... Temperature detection circuit, 28... Humidity detection circuit, 30... Discomfort index detection circuit, 32... Initial stage Reset circuit, 34... Switch circuit, 36... Selection code ROM, 38...
...First code reading circuit, 40...Code storage circuit, 42...Second code reading circuit, 44...
...Read code number detection circuit, 46...Driver control circuit, 48, 50...Multiplexer, 52
...Decoder, 54...Driver.

Claims (1)

[Scope of Claims] 1. A time display section; A time measurement section; A plurality of additional function sections having functions other than time measurement; A first switch; Any one of the time measurement section and the plurality of additional function sections; a display selection circuit that selects one output signal from the above and supplies the time display section; and a code signal from which code signals corresponding to the time measurement section and a plurality of additional function sections can be read.
a ROM; a first code reading circuit that reads code signals from the code signal ROM in a predetermined order; a first code reading circuit having a number of storage areas corresponding to the number of the time clock sections and additional function sections; a code signal storage circuit that sequentially stores code signals in the storage area when a predetermined code signal is output from the readout circuit; and a display selection circuit that reads out the stored contents of the code signal storage circuit in a predetermined order. a second code reading circuit for supplying a second code reading circuit; a display switching circuit for displaying the stored content of the code signal storage circuit on a display section instead of the output content of the display selection circuit; a readout code number detection circuit that stores the number of readout codes and returns the readout operation of the second code readout circuit to the initial state when the number of readout codes matches the number of readout codes of the second code readout circuit; Clock display switching circuit.