JPH0479011B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Functional Embodiment First Embodiment (Fig. 2 to 5) Second embodiment (Fig. 6 to 8) Effects of the invention [Summary of the invention] Two high-speed shift registers are provided for the low-speed FIFO memory, and data is transferred intermittently. While writing high-speed data to one high-speed shift register,
The data of the other high-speed shift register is transferred to the low-speed FIFO.
By alternating input operations to the memory, data can be transferred to the low-speed FIFO memory at a slow and uniform rate, and data can be transferred from the low-speed FIFO memory at a low and uniform rate. By alternately writing data with a value into one high-speed shift register and outputting data from the other high-speed shift register to the outside, data can be transferred to the outside at high speed. do.

The present invention aims to operate as a single FIFO as a whole, and there is no need to externally control the connection relationship between the internal shift register and the low-speed FIFO. That is, it is characterized in that the internal switch is automatically switched based on the valid bit in the shift register. Moreover, the circuit can be realized at extremely low cost.

[Industrial application field]

The present invention relates to a method for configuring a FIFO (First-In First-Out) buffer memory, and particularly relates to a method for configuring a FIFO (First-In First-Out) buffer memory.
By combining a high-speed shift register on the input or output side of the memory, it is possible to convert the data speed in input and output.
This relates to a FIFO memory control device.

In data processing devices and the like, there are cases where it is necessary to transfer data asynchronously between two devices, and FIFO memory is generally used as a data transfer means in such cases.

The FIFO memory control device of the present invention transfers intermittent high-speed data input as low-speed data at a relatively uniform speed by combining a low-speed large-capacity FIFO memory and a high-speed shift register.
Another object of the present invention is to provide a FIFO memory control device that can transfer low-speed data at a relatively uniform rate as intermittent high-speed data.

[Conventional technology]

Traditionally, the method of configuring FIFO memory is as follows:
A method of transferring data by using RAM (Random Access Memory), providing a write pointer and a read pointer, and controlling both pointers independently to perform writing and reading alternately. is used.

[Problem that the invention seeks to solve]

With this type of FIFO memory, if the input and output data rates are different, the RAM can operate at the maximum instantaneous input and output data transfer rate.
is required. However, in general, for RAM, high speed and large capacity are contradictory demands and it is difficult to achieve both. Therefore, when trying to increase the speed and capacity of FIFO memory, it is necessary to There was a problem in that a large amount of RAM had to be used, which inevitably led to a significant increase in both hardware scale and cost.

[Means for solving problems]

FIG. 1 shows the principle configuration for solving such problems, and consists of two high-speed shift registers 10.
1, 102 and low-speed FIFO memory 103, a switch 104 switches between these two high-speed shift registers 101 and 102 and connects them to the low-speed FIFO memory 103, and the two high-speed shift registers 10
In the first invention, high-speed input data from the outside is written to one of the high-speed shift registers via the switch 105, and is written from the other high-speed shift register to the switch 104. The operation of inputting data to the low-speed FIFO memory 103 via the 100-degree shift register is controlled by switching switches 104 and 105 each time data input to the high-speed shift register is completed.
The two high-speed shift registers 101 and 102 are made to perform the shift alternately.

In the second invention, the operation of writing low-speed data output from the low-speed FIFO memory 103 to one high-speed shift register via the switch 104 and outputting data from the other high-speed shift register via the switch 105 is performed by changing the operation of writing the low-speed data output from the low-speed FIFO memory 103 to one high-speed shift register via the switch 105. By switching the switches 104 and 105 each time data output is completed, the two high-speed shift registers 101 and 102 are caused to perform the shift alternately.

The structure and features of the present invention are as follows.

Configuration (1) First and second shift registers that can store input data as a set and a valid bit that indicates the presence of input data; means for writing bits; a first switch for selecting a first or second shift register and connecting the writing means to the selected one of the shift registers; Read the input data and valid bits,
A transfer circuit means for writing read input data into the FIFO, and a second switch for selecting a first or second shift register and connecting the transfer circuit to the other shift register not connected to the first switch.
The switch and the valid bit in the last stage of the first and second shift registers are monitored, and the valid bit indicates the presence of input data from the shift register to which data is being written, and the valid bit is detected when data is read. When a bit indicating no data is detected from the shift register being processed, the first
and switch switching control means for switching the second switch and connecting it to the other shift register to control the first and second shift registers to alternately write and read data. characterized by
FIFO memory controller.

(2) First and second shift registers capable of storing input data and a valid bit indicating the presence of input data as a set, a FIFO, and the first or second shift register.
a writing means for writing input data read from the FIFO and a valid bit; a first switch for selecting a first or second shift register and connecting the writing means to the selected one of the shift registers; Read the input data and valid bits stored in the first or second shift register,
Transfer circuit means for transferring read input data to an external circuit; selecting a first or second shift register; and connecting the transfer circuit to the other shift register not connected to the first switch; Second
The switch and the valid bit in the last stage of the first and second shift registers are monitored, and the valid bit indicating that there is input data from the shift register where data is being written is detected, and when the data is being read. When a bit indicating no data is detected from the shift register being processed, the first
and switch switching control means for switching the second switch and connecting it to the other shift register to control the first and second shift registers to alternately write and read data. characterized by
FIFO memory controller.

Features The present invention aims to operate as a single FIFO as a whole, and there is no need to externally control the internal shift register level or the connection relationship with the low-speed FIFO. That is, it is characterized in that internal switches are automatically switched based on valid bits in the shift register. Moreover, the circuit can be realized at extremely low cost.

[Effect]

In the first invention, the operation of writing intermittently transferred high-speed data into one of the two high-speed shift registers until it is full, and inputting the data from the other high-speed shift register to the low-speed FIFO memory is performed using two high-speed shift registers. By causing the high-speed shift registers to perform data input alternately each time data input to one of them is completed, data can be transferred to the low-speed FIFO memory at a low speed and at a uniform high speed.

In the second invention, the operation is to write data having a low and uniform speed from the low-speed FIFO memory into one of the two high-speed shift registers until it is full, and to output the data in the other high-speed shift register to the outside. By causing the two high-speed shift registers to alternately perform this every time data output from one of them is completed, data transfer to the outside can be performed at high speed.

〔Example〕

[First Embodiment] FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, in which 1 and 2 are high-speed shift registers, 3 is a transfer circuit, 4 is a switch control circuit, and 5 is a low-speed high-speed shift register. of capacity
FIFO memory (hereinafter simply referred to as low-speed FIFO),
SW1 _-1 , SW1 _-2 , SW1 _-3 and SW2 _-1 , SW2 _-2 ,
SW2 _-3 are switches that can be switched alternately in conjunction with each other.

FIG. 3 is a diagram showing the operation of the valid bits in the shift registers 1 and 2, in which a indicates data input, b indicates a full state of data, and e indicates data output.

Further, FIG. 4 is a time chart showing the operation of each part in the configuration of FIG. 2.

The high-speed shift registers 1 and 2 have 8-bit parallel data as data for each stage, and also have a 9th bit called a valid bit. The valid bit becomes '1' when the data in that stage is valid.
It is assumed to be '0' when it is invalid.

In the initial state, shift registers 1 and 2 and low-speed FIFO 5 are empty, and all valid bits of shift registers 1 and 2 are '0'. Therefore, shift register valid signals FG1 and FG2 on the output side of shift registers 1 and 2G are also '0'.

Initially, switches SW1 _-1 , SW1 _-2 , SW1 _-3 point to the shift register 1 side, and switches SW2 -1, SW1 _-3 point to the shift register 1 side.
Assuming that SW2 _-2 and SW2 _-3 point to the shift register 2 side, in this state the data input passes through the switch SW1 -1, and the input clock passes through the switch SW1 _-1 .
Data is written to the shift register 1 by being applied to the shift register 1 through _SW1-2 . At the same time, the valid bit '1' is
It is input to shift register 1 via switches _SW1-3 .

As data is input to the shift register 1, the valid bit '1' shifts towards the output side as shown in FIG. The bit changes as shown in FIG. 3b, and the shift register valid signal FG1 becomes '1'. In Figure 4, A is
The operation of each part in this case is shown.

The switch control circuit 4 inverts each switch when the shift register valid signal FG1 or FG2 becomes '1'. Now that the signal FG1 has become '1', the switches SW1 _-1 , SW1 _-2 , SW1 _{-3 point to the shift register 2, and the switches SW2 -1, SW1 -3} point to the shift register ₂ .
SW2 _-2 and SW2 _-3 now point to shift register 1. Transfer circuit 3 uses shift register enable signal FG1
Or, when FG2 becomes '1', a low speed shift clock is supplied. This shift clock is applied to the shift register 1 via the switch _SW2-2 , which causes the shift register 1 to output data at a constant low speed, and this data is input to the low-speed FIFO ₅ via the switch SW2-1. At this time, the valid bit '0' is input to the shift register 1 via the switches _SW1-3 . As shown in FIG. 3e, the transfer circuit 3 supplies a shift clock to the shift register 1 while the shift register valid signal FG1 is '1', thereby data is transferred from the shift register 1, and the data is Reading continues until it is empty.

At the same time, data is input to shift register 2 via switch SW1 _-1 , and switch SW1 _-2
By providing an input clock via
The data is written and the switch is
Valid bit '1' is input via _SW2-3 .

In this case, from shift register 1 to low speed FIFO 5
The data transfer speed to is selected to be higher than the average speed of data input from the outside to shift register 2, so when shift register 2 is full of data, shift register 1 is already empty. There is. In FIG. 4, B indicates the operation of each part in this case.

As the shift register 2 becomes full, the shift register valid signal FG2 becomes '1'.
The switch control circuit 4 detects this and inverts each switch, and the transfer circuit 3 supplies a shift clock to write data to the shift register 1, and at the same time, from the shift register 2 to the low-speed FIFO 5. data transfer is started. Data writing ends when shift register 1 is full of data, but
At this time, shift register 2 is already empty as described above. In FIG. 4, C indicates the operation of each part in this case.

After that, by repeating this operation alternately, data is written to shift registers 1 and 2, and data is written from shift registers 1 and 2 at low speed.
Data is transferred by alternately reading and reading data from the FIFO 5. In this way,
Data that is input intermittently at high speed can be input to the low-speed FIFO 5 at a low and uniform speed.

The low-speed FIFO5 is a well-known memory composed of RAM.
A FIFO memory that reads input data asynchronously using an externally applied output clock to generate output data. Note that low-speed FIFO
The data transfer rate on the output side of 5 is a slow uniform rate.

FIG. 5 shows a specific configuration example of the transfer circuit 3 in FIG. 2, in which 11 is an OR gate;
12 is a clock source, and 13 is an AND gate.

OR gate 11 is a shift register enable signal
Output when either FG1 or FG2 becomes '1'
1', which causes the clock of the clock source 12 to be output via the AND gate 13. This output becomes the shift clock for each shift register 1, 2 in FIG. 2 and the input clock for the low-speed FIFO 5.

[Second Embodiment] FIG. 6 shows the configuration of another embodiment of the present invention, in which the same parts as in FIG. 2 are designated by the same numbers, and 3A is a transfer circuit. However, compared to the case in Figure 2, high-speed shift registers 1 and 2 and low-speed shift registers
The FIFO 5 is connected in a reverse relationship with respect to input and output, and can convert input data having a relatively uniform speed into intermittent high-speed data and transfer the data. Along with this, the output clock of the transfer circuit 3A is used as the output clock of the low-speed FIFO 5 and the shift clock when writing to the shift registers 1 and 2, and the read clock of the shift registers 1 and 2 is used as the output clock given from the outside. Clocks are beginning to be used. Switch _SW2-4 outputs shift register enable signals FG1 and FG2 to the outside.

Further, FIG. 7 is a time chart showing the operation of each part in the configuration of FIG. 6.

Shift registers 1 and 2 in the embodiment of FIG.
The operation of the valid bits is similar to that shown in FIG.

In the initial state, low-speed FIFO 5 is empty,
All valid bits of shift registers 1 and 2 are '0'
It is. Therefore, the shift register valid signals FG1 and FG2 on the output sides of shift registers 1 and 2 are also '0'.
It is.

Initially, switches SW1 _-1 , SW1 _-2 , and SW1 _-3 point to the shift register 1 side, and switches SW2 _-1 ,
It is assumed that SW2 _-2 , SW2 _-3 and SW2 _-4 point to the shift register 2 side. When the low-speed FIFO 5 is empty, it generates '1' as an EMPTY signal. The transfer circuit 3A transfers the switch from the low-speed FIFO 5 by supplying an output clock when the EMPTY signal is '0' (when the low-speed FIFO 5 is not empty).
Transfer data to shift register 1 via SW1 _-1 . At this time, shift register 1 contains a switch.
Valid bit '1' is input via _SW1-3 .

As data is transferred from the low-speed FIFO 5 to the shift register 1, the valid bits of the shift register 1 shift toward the output as shown in FIG. When it reaches , the valid bit becomes as shown in Figure 3b, and the shift register valid signal FG1 becomes ''.
Becomes 1'. In FIG. 7, A indicates the operation of each part in this case.

The switch control circuit 4 detects that the shift register enable signal FG1 is '1' and the shift register enable signal FG2 is '0', and inverts each switch. This will cause the switch
SW1 _-1 , SW1 _-2 and SW1 _-3 point to shift register 2, and switches SW2 _-1 , SW2 _-2 , SW2 _-3 and SW2 _-4 point to shift register 1. The shift register enable signal FG1 is output to an external circuit (not shown) via switch _SW2-4 , and the external circuit receives the signal FG1.
When is '1', it is determined that there is data, and by inputting the output clock through switch _SW2-2 , data is read from shift register 1 and output data is generated through switch _SW2-1 . .
Reading data from shift register 1 continues until shift register 1 is empty.

Meanwhile, at the same time, data is written to shift register 2 from low-speed FIFO ₅ via switch SW1-1, and a valid bit '1' is input via switch _SW2-3 . This continues until the register valid signal FG2 becomes '1'. When signal FG2 becomes '1', the shift clock from transfer circuit 3 stops,
Data writing to the shift register 2 is stopped.

At this time, the average data transfer rate from shift register 1 to the outside is selected to be lower than the rate of data transfer from low-speed FIFO 5 to shift register 2, so shift register 1 becomes empty and shift register enable signal FG1 is activated. When it becomes '0', the shift register 2 is already full and the shift register valid signal FG2 has become '1'. In FIG. 7, B indicates the operation of each part in this case.

The switch control circuit 4 is a shift register enable signal
Detects that FG1 is '0' ₃ FG2 is '1' and inverts each switch. As a result, data is transferred from the low-speed FIFO 5 to the shift register 1 via the switch _SW1-1 , and at the same time, output data is generated from the shift register 2 to the outside via the switch _SW2-1 . Reading data from shift register 2 continues until shift register 2 is empty. On the other hand, when the shift register 1 becomes full and the shift register valid signal FG1 becomes '1', the shift clock from the transfer circuit 3A is stopped and data writing to the shift register 1 is stopped. In FIG. 7, C indicates the operation of each part in this case.

Thereafter, by repeating such operations, reading data from shift registers 1 and 2 and writing data from low-speed FIFO 5 to shift registers 1 and 2 are performed alternately, and data is transferred. . In this way, the slow FIFO
Data having a slow and uniform speed from 5 can be output intermittently at a high speed.

Note that the data transfer rate on the input side of the low-speed FIFO 5 in this case is a low, uniform rate.

FIG. 8 shows a concrete configuration example of the transfer circuit 3A in FIG. 6, in which the same parts as in FIG. 5 are designated by the same numbers, and 14 is a NAND gate.

The NAND gate 14 generates an output '0' when both shift register valid signals FG1 and FG2 are '1', and '1' otherwise.
When the signals FG1 and FG2 are not both '1' through the gate 13, the clock of the clock source 12 is output. This output is the shift clock for each shift register 1 and 2 in FIG.
This becomes the output clock for FIFO5.

In addition to the above, by combining the methods of the embodiments whose configurations are shown in FIG. 2 and FIG. You can also do it.

The configuration and operation in this case can be easily inferred from the above explanation, and therefore detailed explanation will be omitted.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to configure a FIFO buffer memory with a high instantaneous input speed or instantaneous output speed using a low-speed large-capacity FIFO, and to achieve the same purpose, it is possible to configure a FIFO buffer memory with a high instantaneous input speed or instantaneous output speed. The amount of wear and cost can be reduced.

In the present invention, internal shift registers and low-speed
There is no need to externally instruct the connection relationship with FIFO. That is, it is possible to automatically change the internal switch based on the valid bit in the shift register, and the internal control logic can be realized at low cost.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing a first embodiment of the present invention, and FIG. 3 is a diagram showing the operation of effective bits in a shift register.
4 is a time chart showing the operation of each part in FIG. 2, FIG. 5 is a diagram showing an example of the configuration of the transfer circuit in FIG. 2, FIG. 6 is a diagram showing the second embodiment of the present invention, and FIG. 6 is a time chart showing the operation of each part in FIG. 6, and FIG. 8 is a diagram showing an example of the configuration of the transfer circuit in FIG. 6. 1, 2...Shift register, 3,3A...Transfer circuit, 4...Switch control circuit, 5...Low speed
FIFO, 11...OR gate, 12...clock source, 13...AND gate, 14...NAND gate.

Claims (1)

[Claims] 1. First and second shift registers capable of storing input data and a valid bit indicating the presence of input data as a set; and input data and input data in the first or second shift register. a means for writing a valid bit together with the first or second shift register;
A first switch connects the writing means to the selected one of the shift registers, reads the input data and valid bits stored in the first or second shift register, and stores the read input data in the FIFO. Select the transfer circuit means to be written and the first or second shift register,
A second switch connects the transfer circuit to the other shift register that is not connected to the first switch, and a valid bit in the final stage of the first and second shift registers is monitored, and data writing is performed. The first and second switches are switched when a valid bit indicating input data is present from the shift register being read and a bit indicating no data is detected from the shift register being read. and a switch switching control means connected to the other shift register to control the writing and reading of data in the first and second shift registers alternately. Memory controller. 2. First and second shift registers capable of storing input data and a valid bit indicating the presence of input data as a set; a FIFO; and a FIFO in the first or second shift register.
a writing means for writing input data and valid bits read from the input data, and a first or second shift register;
A first switch connects the writing means to the selected one of the shift registers, reads input data and valid bits stored in the first or second shift register, and transfers the read input data to an external circuit. Selecting the transfer circuit means to transfer data to and the first or second shift register,
A second switch connects the transfer circuit to the other shift register that is not connected to the first switch, and a valid bit in the final stage of the first and second shift registers is monitored, and data writing is performed. The first and second switches are switched when a valid bit indicating input data is present from the shift register being read and a bit indicating no data is detected from the shift register being read. and a switch switching control means connected to the other shift register to control the writing and reading of data in the first and second shift registers alternately. Memory controller.