JP2769418B2 - Buffer and data conversion method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer for controlling data rate conversion of voice data of a personal handy phone (PHP), and more particularly to a buffer capable of reducing circuit cost and a data conversion method thereof.

[0002]

2. Description of the Related Art As a conventional buffer for controlling data rate conversion of audio data of a personal handy phone, there is a buffer as shown in the block diagram of FIG.
Conventional buffers have a data rate of 38, as shown in FIG.
4kbit / sec (hereinafter simply referred to as 384k) or 32k
Input data is input in units of 160-bit data of bit / sec (hereinafter simply referred to as 32k), and an input control unit 2 controls input of the input data, and a buffer unit 3 used to convert the data rate. And an output control unit 5 for controlling output of output data.

The buffer unit 3 is composed of two 160-bit serial registers (registers) 4d and 4e, converts 384k 160-bit input data to 32k, and converts 32k 160-bit input data to 38k.
4k. Input data is input control unit 2
Is transmitted to the register 4d or the register 4e through the interface, and the data is speed-converted and output when the output control unit 3 extracts the data of the register.

Next, a method of converting a data rate in a buffer of a conventional personal handy phone will be described with reference to FIG. FIG. 5 is a timing chart showing a data rate conversion method in the buffer unit 3. In a conventional personal handyphone buffer, input or output of 160-bit data is performed with 5 msec as one frame, as shown in FIG. That is, one register inputs or outputs 160-bit data having a data rate of 384 k or 32 k during one frame (5 msec).

[0005] A conversion operation for converting input data having a data rate of 384 k into output data having a data rate of 32 k will be specifically described with reference to FIG. 5. In the register 4d, 384 kbit / sec in one frame (frame 1)
Is input to the register 4d via the input control unit 2 in a time of 416 μsec. That is, 38
This is input data of 4k (160 bits / 416 μsec). Then, the next one frame (frame 2)
And the 160-bit data accumulated in frame 1 is 5 m
32k (160 bits / 5msec)
) Output data. Thus, register 4d
The data of 160 bits is converted from 384k to 32k by changing the speed of the data input to and the speed of the output data.

On the other hand, in the register 4e, 160-bit data already stored is
32k (160 bits / 5msec)
) Output data. Then, in frame 2, new 160-bit data is input in a time of 416 μsec, and
The input data of 84k (160 bits / 416 μsec) is stored. The 384k data accumulated in frame 2 is output in the next one frame at a time of 5 msec, and is converted into 32k output data.

That is, in the frame 1, the register 4d
Then, the operation of inputting 384k data in the register 4e and outputting 32k data in the register 4e (operation X) is performed. In frame 2, the operation of outputting 32k data in the register 4d and inputting 384k data in the register 4e (operation Y). Is performed.

Then, by repeating the operation X and the operation Y alternately, the entire buffer section 3 has 16 frames per frame.
The data rate of 0-bit data is converted from 384k to 32k and output.

Similarly, two 160-bit serial registers are used to convert 160-bit 32k data to 384k data.
It can also be converted to data. FIG. 6 shows a timing chart in this case. As shown in FIG.
In this case, 160-bit data is input to the register 4d at a time of 5 msec to be 32k input data, and 160-bit data is output from the register 4e at a time of 416 μsec to be 384k data (operation X ').

In the frame 2, the data is output from the register 4d at a time of 416 .mu.sec to be 384k data, and is input to the register 4e at a time of 5 msec to be 32k input data (operation Y '). By repeating the operation X 'and the operation Y' alternately, the data rate of 160-bit data is converted from 32 k to 384 k for each frame (5 msec) in the entire buffer section 3 and output. .

[0011]

However, since the conventional personal handyphone buffer uses two large-capacity registers of 160 bits, there is a problem that the circuit cost increases. .

The present invention has been made in view of the above circumstances, and provides a buffer capable of reducing the register capacity without lowering the data conversion efficiency and reducing the circuit cost, and a data conversion method therefor. The purpose is to:

[0013]

According to a first aspect of the present invention, there is provided a buffer system comprising three 80-bit registers and 160-bit data which are inputted in the first and second half of the buffer. Divided into two 80-bit data and sequentially entered into two of the three registers.
An input control section for inputting the data rate of the force data, the front
The two half-half 80-bit data are ordered from the register
At a data rate different from the data rate of the input data.
Possess an output control section for outputting a bit data, said output
Take out when the control unit is taking out 80-bit data
The input control unit inputs data to a register where no
Data input .

According to a second aspect of the present invention, there is provided a data conversion method for a buffer according to the first aspect, wherein the input control unit converts the input 160-bit data into a first half of 80 bits and a second half of the first half. The first 80 bits and the second 80 bits are input to different registers, and the output control unit converts the 80-bit data stored in the registers at a data rate different from the data rate of the input data from the registers. And the first 80 bits and the second 80 bits of data are
The output is synthesized with 0-bit data and output is controlled.
When your part is taking out the first half and second half of the 80-bit data
A register in which the input control unit has not been taken out.
The input data is input to the data .

According to a third aspect of the present invention, there is provided a buffer data conversion method according to the second aspect, wherein 2.5 msec is defined as one frame and three frames are used in the first frame. The first half of the first 160-bit data is stored in the first register of the 80-bit registers.
0 bits are input at 208 μsec, and the second half 80 bits of the first 160-bit data are stored in the second register by 2 bits.
08 μsec and another 80 bits from the third register in the first frame for 2.5 ms.
ec, output the first 80 bits of the first 160-bit data from the first register in the second frame in 2.5 msec, and output the second 80 bits to the third register in the third frame. The first 80 bits of the 160-bit data are input at 208 μsec, and the second 80 bits of the second 160-bit data are stored in the first register as 2 bits.
08 μsec, and outputs the second half 80 bits of the first 160-bit data from the second register in the third frame in 2.5 msec.
In the third frame, the second 1
The first 80 bits of 60-bit data is 2.5 msec.
And in the fifth frame, the first half 80 bits of the third 160-bit data are stored in the second register at 208 μm.
second, and the third register is stored in the third register.
The latter 80 bits of the 0-bit data are input at 208 μsec, and the latter 80 bits of the second 160-bit data are output from the first register in the fifth frame at 2.5 msec. In the frame, the first 80 bits of the third 160-bit data are output from the second register in 2.5 msec,
The operation of the sixth frame to the sixth frame is repeated, and the input data rate is 384 kbit / sec, and the output data rate is 32 kb.
It is characterized in that it is converted to it / sec.

According to a fourth aspect of the present invention, there is provided a buffer data conversion method according to the second aspect, wherein 2.5 msec is defined as one frame and three frames are used in the first frame. Of the 160-bit data from the first register of the 80-bit register is output in 208 μsec, and the second half of the 160-bit data is output from the second register in the form of 208 μsec.
sec, and the third frame in the first frame.
The first half 80 bits of the first 160-bit data are input to the first register at 2.5 msec, and the second half 80 bits of the first 160-bit data are input to the first register at 2.5 msec in the second frame. In the third frame, the first 80 bits of the first 160-bit data are output from the third register in 208 μsec in the third frame, and the latter 80 bits of the first 160-bit data are output from the first register in the second frame. In the third frame, the first 80 bits of the second 160-bit data are stored in the second register for 2.5 m at a time of 208 μsec.
The second 80 bits of the second 160-bit data are input to the third register in the fourth frame in 2.5 msec, and the second register is input from the second register in the fifth frame in the fifth frame. Output the first half 80 bits of the 160-bit data at 208 μsec, output the second half 80 bits of the second 160-bit data from the third register at 208 μsec, and output the first 80-bit data at the fifth frame. The first 80 bits of the third 160-bit data are input to the register in 2.5 msec,
In the sixth frame, the third register is stored in the second register.
The latter 80 bits of the 60-bit data are 2.5 msec.
And the operations of the first to sixth frames are repeated to convert the input data rate of 32 kbit / sec to the output data rate of 384 kbit / sec.

[0017]

According to the first aspect of the present invention, three 80-bits are provided.
Store each 80-bit data and input
160-bit data input by the control unitEarly and lateTwo
Divided into 80-bit dataOf the three registers
Two registersInput at the data speed of input data in order
However, the output control unit differs from the data speed of the input data.
From register at data rateIn the first half of the second half80 bi
The 80-bit data to 160 bits.
Output dataHowever, the output control unit is 8
Extraction is performed while extracting 0-bit data.
The input controller inputs the input data to a register that is not
UThe input 160-bit data
Data into two 80-bit registers.
Data speed that is different from the data speed at the time of input.
Convert data rate by taking out each in degrees and combine
As a result, if the data is 160 bits, a small capacity of 80 bits
Data rate conversion of 160-bit data
Can doDo not reduce the data conversion efficiency
The capacity of the registerSignificantly reduces circuit cost
can do.

According to the second aspect of the present invention, the input
The first half of the 160-bit data is
And the latter half into 80 bits for different registersinput
80 bits stored in the register in the output control unit.
Data speed different from the data speed of the input data
The first 80 bits and the second 80 bits of data.
Data into 160-bit data and outputTogether with
The force control unit is taking out the first half and second half of the 80-bit data.
When the input control unit is not
Input data to the dataThe buffer according to claim 1,
Data conversionMethodSo a small capacity 80 bit
Data rate conversion of 160-bit data
Can beWithout reducing data conversion efficiency
Reduce the capacity of the register,Significantly reduce circuit cost
Can be

According to the third aspect of the present invention, in each register, 2.5 msec is defined as one frame, and the first frame of the first frame has 384 kbit / sec.
By dividing the 0-bit data into 80-bit data,
, And another 80-bit data is output from the third register at 32 kbit / sec, the first register of the first 160-bit data is output in the second frame, and the third frame is output. Divides the second 160-bit data into 80-bit data, inputs the divided data to the third and first registers, outputs the second register of the first 160-bit data, and outputs the second 160-bit data in the fourth frame. The third register of bit data is output, the third 160-bit data is divided into 80-bit data in the fifth frame and input to the second and third registers, and the first 160-bit data of the second 160-bit data is input. 3. The data conversion method according to claim 2, further comprising: outputting a register of the second register, outputting a second register of the third 160-bit data in the sixth frame, and repeating the first to sixth frames. Therefore, two frames (5 ms
c) The 80-bit data is synthesized every time to obtain 160-bit data from a data rate of 384 kbit / sec to 32.
It can be converted to k bits / sec, and the circuit capacity can be reduced by reducing the register capacity without lowering the data conversion efficiency.

According to the fourth aspect of the present invention, in each register, 2.5-msec is defined as one frame, and 80-bit data is transferred in the first frame at 384 kbit / frame.
Output from the first and second registers in 32 sec.
The first half of the first 16 0 bi Ttodeta input to third register t / sec, 32kbi in the second frame
The second half of the first 16 0 bi Ttodeta input to the first register in t / sec, the first 16 in the third frame
0 to output the third register component and a first register portion of the bi Ttodeta, the first half of the second 16 0 bi Ttodeta second
Input to the register, 0 second 16 in the fourth frame
Enter the second part of the bi Ttodeta in the third register, 5
Th frame and outputs a second register portion of the second 16 0 bi Ttodeta and a third register content, enter the first part of the third 16 0 bi <br/> Ttodeta in the first register, in the sixth frame the second half of the third 16 0 bi Ttodeta input to the second register, since the data conversion method of claim 2, wherein repeating the 1-6-th frame, 2
8 bits of 160-bit data per frame (5 msec)
It is divided into 0-bit data and the data rate is 32k bit /
sec. to 384 kbit / sec, the register capacity can be reduced and the circuit cost can be reduced without lowering the data conversion efficiency.

[0021]

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration block diagram illustrating a configuration of a buffer according to an embodiment of the present invention. Parts having the same configuration as in FIG. 4 will be described using the same reference numerals.

The buffer of this embodiment has a data rate of 384.
Input data is input in units of 160-bit data of kbit / sec or 32 kbit / sec, and an input control unit 2 for performing input control of input data and three 80-bit serial registers (registers) 4a, 4b, and 4c are provided. A buffer unit 3 'for providing data rate conversion;
An output control unit 5 for controlling output of output data.

Then, as shown in FIG.
Are connected to the three registers 4a, 4b, 4c of the buffer unit 3 ', and each register of the buffer unit 3' is connected to the output control unit 5
It is configured to be connected to

Here, each component of the buffer of the present embodiment will be specifically described. The input control unit 2 includes the input unit 1
, And 160 bits of data, and divides the data into the first half 80 bits and the second half 80 bits, and sends them to the register 4 of the buffer unit 3 '. At this time, control is performed so that the first half 80 bits and the second half 80 bits are respectively sent to different registers 4.

The buffer section 3 'is composed of three 80-bit serial registers 4a, 4b and 4c,
The conversion from data to 32k data or the conversion from 32k data to 384k data is performed. The principle of the data rate conversion is to change the data rate by changing the output time for the data input to the buffer.
It can be converted from 4k to 32k or from 32k to 384k.

In particular, in the buffer of the present embodiment, 2.5 m
The input or output of 80-bit data is performed with sec being a frame unit. That is, one register 4 inputs 80-bit data divided into two by the input control unit 2 during one frame (2.5 msec), and outputs the data at a different speed from the input in the subsequent one frame. Data rate from 384k to 32
k or from 32k to 384k.
By combining the input and output of the three 80-bit registers 4a, 4b and 4c, the data rate of the 160-bit data divided into the first half and the second half is converted.

The output control unit 5 stores the data divided into two 80-bit data in registers 4a, 4b, 4c.
At the data rate (32 k or 384 k) to be converted, recombined, and transmitted again in the form of 160-bit data. That is, the output control section 5 outputs 160-bit data whose data rate has been converted.

Next, the data conversion method in the buffer according to the present embodiment will be specifically described with reference to FIG. FIG. 2 is a timing chart for converting 384k data to 32k data. In the data conversion in the buffer of the present embodiment, the 384k 160-bit data is divided into the first half 80 bits and the second half 80 bits by the input control unit 2 and input to the different registers 4 respectively.
The output control unit 5 extracts the first and second half 80 bits at a data rate of 32 k, combines them, and outputs them as 160-bit data.

First, the registers 4a and 4a for converting the data rate of 160-bit 384k data to 32k.
Operations b and 4c will be described. In frame 1, the first half 80 bits (A1) of 160-bit data A divided by the input control unit 2 in the register 4a are 208 .mu.se.
Entered at time c. The data rate at this time is 384
k (80 bits / 208 μsec) (101). When the input of the register 4a is completed, the latter half 8
0 bits (A2) are at a data rate of 384k, ie 2
It is input for a time of 08 μsec (102). Operation (10
In parallel with 1) and (102), the already stored 80-bit data is extracted from the register 4c in 2.5 msec, and is output as 32k (80 bits / 2.5 msec) output data (103).

In the next frame 2, the first 80 bits (A1) of the data A accumulated in the operation (101) are output from the register 4a in 2.5 msec and converted to 32k (104). In frame 2, register 4b
And 4c perform no input / output.

In frame 3, the first 80 bits (B1) of the next 160-bit data B are stored in the register 4c as 38 bits.
It is input at a data rate of 4k, that is, in a time of 208 μsec (105). After the input to the register 4c, the latter 80 bits (B2) of the data B are stored in the register 4a at 208 .mu.se.
It is input at the time of c (106). Operation (105),
In parallel with (106), the operation from the register 4b (10
The latter 80 bits (A2) of the data A stored in 2) are taken out in 2.5 msec, and the data speed is set to 32 k (107).

In the operations (104) and (107), the output control unit 5 extracts 80-bit data A1 from the register 4a and 80-bit data A2 from the register 4b at a data rate of 32 k (80 bits / 5 msec). Then, A1 and A2 are recombined in the output control unit 5 to become 160-bit 32k data, which is output.

In the frame 4, the first 80 bits (B1) of the data B stored in the register 4c are transferred by 2.5 m.
Data is taken out at a time of sec and the data rate is set to 32 k (108). In this frame, the registers 4a and 4b do not perform input / output.

In the next frame 5, the first 80 bits (C1) of the data C are input to the register 4b at a data rate of 384 k, that is, at a time of 208 μsec (10
9). Subsequently, the latter 80 bits (C2) are input to the register 4c in 208 .mu.sec (110). Operation (10
9), the operation (1) from the register 4a in parallel with (110)
06) The latter 80 bits (B2) of the data B input in
At a time of 2.5 msec, and set the data rate to 32
k (111).

In the operations (108) and (111), the output control unit 5 extracts 80-bit data B1 from the register 4c and 80-bit data B2 from the register 4a at a data rate of 32 k (80 bits / 5 msec). Then, B1 and B2 are recombined in the output control unit 5 to become 160-bit 32k data, which is output.

Then, in frame 6, the operation (109)
The first 80 bits (C1) of the data C stored in
The data is extracted at a time of msec, and the data rate is set to 32 k (112). In this frame, the registers 4a and 4c do not perform input / output.

By repeating a series of operations from frame 1 to frame 6, one 160-bit data is converted every two frames (5 msec).
The data divided and converted into the first half and the second half of each 80 bits is converted again by the output control unit 5 after the conversion.
The data is synthesized from 0-bit data and then output from the output unit 6. In this manner, the conversion from 384k data to 32k data is performed.

Next, 32k in the buffer of this embodiment
The conversion method from 384k to 384k will be described with reference to the timing chart of FIG. In frame 1, register 4
The first 80 bits (D1) of 160-bit data D are stored in c.
Is input at a time of 2.5 msec. The data rate at this time is 32 k (80 bits / 2.5 msec) (20
1). In parallel with this, the already stored 80-bit data is extracted from the register 4a in 208 μsec, and becomes 384k data (80 bits / 208 μsec) (202). When the output of the register 4a is completed, the stored 80-bit data is similarly extracted from the register 4b in a time of 208 μsec, and the data speed is reduced to 384 k.
(203).

In frame 2, 32 is stored in register 4a.
The latter 80 bits (D2) of the 160-bit data D of k are inputted in a time of 2.5 msec (204). In this frame 2, the registers 4b and 4c do not perform input / output.

In the frame 3, the first 80 bits (D1) of the data D are extracted from the register 4c at a time of 208 μsec, and output at a data rate of 384 k (2
05). Subsequently, the second half 80 of the data D is obtained from the register 4a.
The bit (D2) is taken out in a time of 208 .mu.sec and 3
It is output at 84k (206). Data converted 80
The bit data is combined in the output control unit 5 and is
It is output as 60-bit data. This means that 160 bits of data D have been converted from 32k to 384k.

In parallel with the operations (205) and (206), the first half 80 bits (E1) of the 160-bit data E having a data rate of 32 k are stored in the register 4b for 2.5 msec.
(207).

Similarly, the latter 80 bits (E2) of the data E are input to the register 4c in 2.5 msec (208), and the first 80 bits (E1) of the data E are output from the register 4b in 208 μsec (209). ), The latter 80 bits (E2) of data E are stored in registers 4c through 20
The data is output in 8 .mu.sec (210), and the first 80 bits (F1) of the data F are stored in the register 4a in parallel with the output of the data E.
Is input in 2.5 msec (211), and then the data F
80 bits (F2) of register 2b are stored in register 4b by 2.5 mse
It is input at c (212), and so on.

Then, by repeating a series of operations (201) to (212), the data rate is converted from 32 k to 384 k for 160 bit data every two frames (5 msec) in the entire buffer section 3. is there.

That is, the data conversion method of this embodiment is as follows.
Assuming that two of the three registers 4a, 4b, and 4c are one set, the 160-bit data is divided into the first half 80 bits and the second half 80 bits.
The data rate is converted by dividing the data into bits and taking out the data at a speed different from that at the time of input, and the first and second half 80 bits are combined and output as 160-bit data.

Here, how to combine the registers will be briefly described.
The first half of the 60-bit data is input to 4b, and the second half is input to 4b. For the next data, the first half is input to 4c, the second half is input to 4a, and for the next data, the first half is input to 4b and the second half is input to 4c. Then, data is input again by combining 4a and 4b. That is, considering only the input,
How to combine registers is (4a, 4b) → (4c,
4a) → (4b, 4c) → (4a, 4b).

At the time of output, first, the first 80 bits of certain data from the register 4a are output at a different speed from the input when the latter 80 bits are input from 4b. Similarly, for the next data, the first half is output from 4c and the second half is output from 4a.
, The first half is output from 4c, and the second half is output as a set of 4a and 4b. That is,
Looking only at the output, (4a, 4b) → (4c, 4a) →
Register combinations are sequentially shifted in the order of (4b, 4c) → (4a, 4b).

The input operation and the output operation are combined to convert the data rate of 160-bit data from 384k to 32k or from 384k to 32k in two frames (5 msec).

According to this embodiment, the input control unit 2 divides the input 160-bit data into the first half 80 bits and the second half 80 bits, sends the divided 80-bit data to the separate register 4, and outputs the divided data. By taking out data at a speed different from that at the time of input to the register 4 by the control unit 5, the data speed is increased from 384 k to 32 k or 32 k.
k to 384k, and the output control unit 5
Since 0 bits and the latter 80 bits are combined and output as 160-bit data, the conversion of 160-bit data can be performed with three 80-bit registers without lowering the conversion efficiency. There is an effect that the circuit cost can be greatly reduced as compared with the conventional circuit using the 160-bit register.

[0049]

According to the first aspect of the present invention, three 8
80-bit data at 0 bit register stores each after the first half 160-bit data input by the input control unit
Divided into two half 80-bit data, 3 registers
Data rate of input data to two registers in order
The output control unit extracts two 80-bit data in the first half and the second half from the register in order at a data rate different from the data rate of the input data.
Output control after combining with 60-bit data
When the part is extracting 80-bit data,
The input control unit inputs the input data to the
The input data is converted to a data buffer by dividing the input 160-bit data into 80-bit data, storing them in two 80-bit registers, and extracting them at a data speed different from the data speed at the time of input. However, if the data is combined into 160-bit data, the data rate conversion of 160-bit data can be performed with a small-capacity 80-bit register, and the data conversion efficiency is reduced.
Therefore, there is an effect that the capacity of the register can be reduced and the circuit cost can be significantly reduced.

According to the second aspect of the present invention, the input
The first half of the 160-bit data is
And the latter half into 80 bits for different registersinput
80 bits stored in the register in the output control unit.
Data speed different from the data speed of the input data
The first 80 bits and the second 80 bits of data.
Data into 160-bit data and outputTogether with
The force control unit is taking out the first half and second half of the 80-bit data.
When the input control unit is not
Input data to the dataThe buffer according to claim 1,
Data conversionMethodSo a small capacity 80 bit
Data rate conversion of 160-bit data
Can beWithout reducing data conversion efficiency
Reduce the capacity of the register,Significantly reduce circuit cost
There is an effect that can be.

According to the third aspect of the present invention, in each register, 2.5 msec is defined as one frame, and the first frame of 384 kbit / sec is used in the first frame.
By dividing the 0-bit data into 80-bit data,
, And another 80-bit data is output from the third register at 32 kbit / sec, the first register of the first 160-bit data is output in the second frame, and the third frame is output. Divides the second 160-bit data into 80-bit data, inputs the divided data to the third and first registers, outputs the second register of the first 160-bit data, and outputs the second 160-bit data in the fourth frame. The third register of bit data is output, the third 160-bit data is divided into 80-bit data in the fifth frame and input to the second and third registers, and the first 160-bit data of the second 160-bit data is input. 3. The data conversion method according to claim 2, further comprising: outputting a register of the second register, outputting a second register of the third 160-bit data in the sixth frame, and repeating the first to sixth frames. Therefore, two frames (5 ms
c) The 80-bit data is synthesized every time to obtain 160-bit data from a data rate of 384 kbit / sec to 32.
The conversion into k bits / sec can be achieved, and there is an effect that the register cost can be reduced and the circuit cost can be reduced without lowering the data conversion efficiency.

[0052] According to the invention of claim 4, wherein, in each register, a 1 frame 2.5 m sec, 384k and 80-bit data in the first frame bit /
Output from the first and second registers in 32 sec.
The first half of the first 16 0 bi Ttodeta input to third register t / sec, 32kbi in the second frame
The second half of the first 16 0 bi Ttodeta input to the first register in t / sec, the first 16 in the third frame
0 to output the third register component and a first register portion of the bi Ttodeta, the first half of the second 16 0 bi Ttodeta second
Input to the register, 0 second 16 in the fourth frame
Enter the second part of the bi Ttodeta in the third register, 5
Th frame and outputs a second register portion of the second 16 0 bi Ttodeta and a third register content, enter the first part of the third 16 0 bi <br/> Ttodeta in the first register, in the sixth frame the second half of the third 16 0 bi Ttodeta input to the second register, since the data conversion method of claim 2, wherein repeating the 1-6-th frame, 2
8 bits of 160-bit data per frame (5 msec)
It is divided into 0-bit data and the data rate is 32k bit /
sec. to 384 kbit / sec, and there is an effect that the register capacity can be reduced and the circuit cost can be reduced without lowering the data conversion efficiency.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a buffer according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a buffer according to an embodiment of the present invention.
FIG. 4 is a timing chart illustrating a method of converting data into k.

FIG. 3 is a diagram illustrating an example of a buffer from 32k to 384 in the present embodiment.
FIG. 4 is a timing chart illustrating a method of converting data into k.

FIG. 4 is a configuration block diagram of a conventional buffer.

FIG. 5 is a timing chart showing a method of converting data from 384k to 32k in a conventional buffer.

FIG. 6 is a timing chart showing a method of converting data from 32k to 384k in a conventional buffer.

[Explanation of symbols]

2 ... input control unit 3 ... buffer unit 4 ... register
5 Output control unit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 13/08

Claims (4)

(57) [Claims] 1. Three 80-bit registers and input 160-bit data are divided into two 80-bit data in the latter half of the first half, and are divided into two of the three registers. an input control section for inputting the data rate of input data sequentially takes out two 80-bit data of the first half the second half at a data rate different from the data rate of the order input data from the register, by combining the 80-bit data fetched the Output control unit that outputs 160-bit data
And the output control unit extracts 80-bit data.
Input registers to registers that have not been
A buffer, wherein the control section inputs input data . 2. A divided into 80-bit first and second halves 80 bits in the input control unit the input 160-bit data, inputs the second half 80 bits and the first half 80 bits in different registers, the register in the output control section The stored 80-bit data is fetched from the register at a data rate different from the data rate of the input data, and the first half 80 bits and the second half 80 bits of data are extracted from the register.
The output is synthesized with 0-bit data and output is controlled.
When your part is taking out the first half and second half of the 80-bit data
A register in which the input control unit has not been taken out.
2. An input data is input to the data input device.
Data conversion method of the buffer described. 3. Assuming that 2.5 msec is one frame.
In the first frame, the first 80 bits of the first 160-bit data are input to the first register out of the three 80-bit registers at 208 μsec, and the second half of the first 160-bit data are input to the second register. 80 bits to 208
μsec and another 80 bits from the third register in the first frame for 2.5 msec.
And outputs the first 80 bits of the first 160-bit data from the first register in the second frame.
5 msec, the first 80 bits of the second 160-bit data are input to the third register in the third frame in 208 μsec, and the second half of the second 160-bit data are input to the first register. Bit 208
μsec, output the second half 80 bits of the first 160-bit data from the second register in the third frame in 2.5 msec, and output from the third register in the fourth frame in the fourth frame. The second 160
The first 80 bits of the bit data are output in 2.5 msec, and the first 80 bits of the third 160-bit data are stored in the second register in the fifth frame for 208 μsec.
c, the latter 80 bits of the third 160-bit data are input to the third register in 208 μsec, and the second 160-bit data of the second 160-bit data is input from the first register in the fifth frame. The latter half 80 bits are output at 2.5 msec, and the first half 80 bits of the third 160-bit data are output from the second register in the sixth frame at 2.5 msec.
The operation of the third frame is repeated and the input data rate 38
Output data speed 32k bit at 4k bit / sec
3. The data conversion method according to claim 2, wherein the data is converted to / sec. 4. Assuming that 2.5 msec is one frame.
In the first frame, of the three 80-bit registers, the first register outputs the first 80 bits of the 160-bit data from the first register in 208 μsec, and the second register outputs the latter 80 bits of the 160-bit data in the 208 μsec.
c, the first 80 bits of the first 160-bit data are input to the third register in the first frame in 2.5 msec, and the first register is input to the first register in the second frame in the second frame. 8 of the latter half of 160-bit data
0 bit is input in 2.5 msec, and in the third frame, the first 80 bits of the first 160-bit data are output from the third register in 208 μsec, and the first register is output from the first register in 208 μsec. While outputting the latter 80 bits of the 160-bit data in 208 μsec,
In the third frame, a second one is stored in the second register.
The first 80 bits of 60-bit data is 2.5 msec.
And in the fourth frame, store the latter 80 bits of the second 160-bit data in the third register by 2.5.
m second, output the first 80 bits of the second 160-bit data from the second register in the fifth frame in 208 μsec, and output the second half of the second 160-bit data from the third register in the fifth frame. 80 bits are output at 208 μsec, the first 80 bits of the third 160-bit data are input to the first register in the fifth frame at 2.5 msec, and the second at the sixth frame. The second half 80 bits of the third 160-bit data are input to the register at 2.5 msec, and the operations of the first to sixth frames are repeated to set the input data rate of 32 kbit / sec to the output data rate of 38.
3. The data conversion method according to claim 2, wherein the data is converted to 4 k bits / sec.