JPH0479485B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a current control circuit composed of a semiconductor circuit. The present invention uses a MOS transistor as a resistor, and uses it as a circuit that controls the current flowing through this MOS transistor to a desired value.

The present invention relates to a circuit that generates a control gate voltage for a MOS transistor in order to control the drain current flowing through the MOS transistor.
The present invention enables accurate control of the current flowing through a MOS transistor.

[Conventional technology]

Conventionally, in semiconductor circuits, one MOS transistor is connected as shown in Figure 2 and used as one resistor, and a signal line S is connected from a potential supply source V _DD to a signal line S.
Techniques are known for controlling the current flowing through the device to a desired value. That is, using a P channel MOS transistor Q _I as the MOS transistor,
This MOS transistor uses a depletion type transistor whose source and gate are connected.
The value of the current flowing through Q _I is determined by this MOS transistor Q _I
It is determined by the channel width W and channel length L and the manufacturing conditions thereof.

[Problem to be solved by the invention]

However, when a depletion type transistor is used in this way, in order to reduce the value of the current to flow, that is, to increase the resistance of the P-channel MOS transistor, a large area is required for this MOS transistor, and the channel width W
It was necessary to increase the ratio W/L of the channel length and the channel length L so that W/L≪1. Furthermore, with this design, due to variations in manufacturing process expansion, this P-channel MOS
Since the characteristics of the transistor change, the current flowing through it is also affected by this, causing the problem that the product is not uniform.

The present invention solves the above-mentioned drawbacks.The present invention has a small footprint as a whole, and even if there are slight variations in the manufacturing process, it is possible to generate a control voltage for a MOS transistor that can control the current flowing through the MOS transistor more accurately and uniformly. The purpose is to provide circuits.

[Means to solve the problem]

In the present invention, the drain and source are connected between the potential supply source V _DD and the signal line S, and the controlled MOS
This circuit supplies a control voltage to the gate of transistor _QI .

That is, in the present invention, the drain and source are connected in parallel between the potential supply source V _DD and the first connection point B, and the gates thereof are all connected to the first connection point B, and the controlled MOS Transistor Q _I
a plurality of n MOS transistors Q ₁ ...Q _o , which are of the same conductivity type and whose ratios of channel width and channel length are set to be approximately equal to each other;
A load transistor Q _L is connected between the connection point B and the second connection point C, and the load transistor Q L is connected between the second connection point C and the ground potential, and its conductivity type is that of the controlled MOS transistor. A cut-off MOS transistor _QC1 is of the opposite conductivity type to _QI , and another MOS transistor QC1 is connected between the potential supply source and the first connection point B and is of the same conductivity type as the controlled MOS transistor _QI . A cut-off MOS transistor Q _C2 is provided, and the potential at the first connection point B is supplied to the gate of the controlled MOS transistor Q _I as the control voltage.

The load transistor Q _L is a depletion type MOS transistor whose gate is connected to the second connection point C, and is preferably a MOS transistor of a conductivity type opposite to that of the controlled MOS transistor Q _I.

[Effect]

The above n MOS transistors are controlled
If the conductivity type is the same as that of the MOS transistor, and the channel width and channel length ratios are set to be approximately equal to each other, each of the plurality of n
The current flowing through the MOS transistor can be made approximately 1/n of the current flowing through the load transistor _QL . By selecting the value of n, it is possible to set the voltage supplied to the gate of the controlled MOS transistor _QI . The current flowing through the control MOS transistor Q _I can be controlled accurately and uniformly.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows its configuration.
n P-channel MOS transistors Q ₁ , Q ₂ ... _Q o connected in parallel between V _DD and connection point B, and with their respective gates all connected to connection point B.
, an n-channel depletion transistor Q _L connected between connection points B and C, and whose gate is connected to connection point C, and between connection point C and ground potential V _SS an n-channel MOS transistor Q _C1 connected to the gate and controlled by the cut-off signal A, and a P-channel MOS transistor Q _C2 connected between the potential supply source V _DD and the connection point B and controlled by the cut-off signal A. including. Due to the voltage at this connection point B, the potential supply source V _DD
A controlled MOS transistor Q _I connected between the signal line and the signal line is controlled. Here, a plurality of n MOS transistors Q ₁ , Q ₂ ...Q _o and the controlled MOS transistor Q _I are of the same type (same dimension and characteristics)
This is a P-channel MOS transistor.

In the above configuration, when the cut-off signal is given an "H" level, the cut-off MOS transistor Q _C1 is turned on, and the cut-off MOS transistor Q _C2 is turned off, so that a circuit current flows. This current is determined by the load transistor Q _L , and due to the circuit configuration, the transistors Q ₁ ,
Q ₂ ...each of Q _o has n of the current flowing through Q _L
1/1 will flow. Furthermore, Q ₁ , Q ₂ …
...Q _o and Q _I are of the same type, and since both gate inputs are B, equal currents should flow.
When applying the "L" level as the cutoff signal, the cutoff MOS transistor Q _C1 is turned off.
Q _C2 turns on and the potential of B becomes V _DD . At this time
Q _I turns off and current no longer flows in any path.

Generally, a MOS transistor occupies the smallest area when dimension W/L (channel width/channel length)≈1. When W/L≒1, the current flowing through a depletion type transistor like Q _I in Figure 1 and Q _I in Figure 2 is several 100 μA.
This is the order. Therefore, if it is desired to flow a smaller current into the signal line S, the channel length L of the conventional transistor _QI shown in FIG. It means increasing the area. On the other hand, in the case of the present invention, since the value of n can be selected, the dimension of Q _I is set as W/L≒1,
It is possible to cause a small current to flow through the transistor Q _I without making L or W extremely large.

As a result, in the circuit of the present invention, the area occupied by this portion can be reduced. moreover
In the case where there are many signal lines S through which currents of MOS transistors flow, in the present invention, only one set is required for the part that creates the potential of B (all transistors other than Q _I ), and only Q _I requires a plurality of wires. The effect is noticeable.

Furthermore, it is hardly affected by variations in circuit configuration or manufacturing, and accurate current control becomes possible.

〔Effect of the invention〕

As explained above, according to the present invention, since the potential of the connection point B can be set by the number n of transistors of the same type, the current flowing through the controlled MOS transistor whose gate is connected to the connection point B can be controlled accurately and Can be controlled down to small values. Further, the area occupied by the transistor can be kept small.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a control voltage generation circuit for a MOS transistor according to an embodiment of the present invention. Figure 2 shows the conventional example.
Connection circuit diagram of MOS transistor. V _DD ... Potential supply source, V _SS ... Ground potential, Q _I ...
...MOS transistor, Q ₁ , Q ₂ ...Q _o ...P channel MOS transistor, Q _L ...N channel depletion type load transistor, Q _C1 ,
Q _C2 ...Cut-off MOS transistor, A...
Cut-off signal, B, C... connection point, S... signal line.

Claims (1)

[Claims] 1. In a control voltage generation circuit whose drain and source are connected between a potential supply source _VDD and a signal line S and which supplies a control voltage to the gate of a controlled MOS transistor _QI , the potential supply source comprises: The drain and source are connected in parallel between V _DD and the first connection point B, and the gates thereof are all connected to the first connection point B, and are of the same conductivity type as the controlled MOS transistor Q _I. can be,
A plurality of n MOS transistors Q ₁ ...Q _o whose ratios of channel width and channel length are set to be approximately equal to each other are connected between the first connection point B and the second connection point C. A load transistor Q _L is connected between the second connection point C and the ground potential, and its conductivity type is that of the controlled MOS transistor.
A cut-off MOS transistor Q _C1 having a conductivity type opposite to Q _I ; and a controlled MOS transistor Q C1 connected between the potential supply source V _DD and the first connection point B _;
and another cut-off MOS transistor _QC2 of the same conductivity type as the control MOS transistor QI, the potential of the first connection point B is supplied as the control voltage to the gate of the controlled MOS transistor _QI , and the load transistor _QL 1. A control voltage generation circuit for a MOS transistor, characterized in that the gate thereof is a depletion type MOS transistor connected to the second connection point _C , and is comprised of a MOS transistor of a conductivity type opposite to that of the controlled MOS transistor QI.