JPH0480544B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a writing and erasing method for a semiconductor nonvolatile memory device (hereinafter referred to as "nonvolatile memory") that can be electrically written and erased. be.

[Prior Art] EEPROM (Electrically Erasable Read
Only Memory).

To facilitate understanding of this invention,
I will give an overview of EEPROM.

Normally, even when a voltage of about 20 to 30 V is applied to a silicon oxide (SiO ₂ ) film, only an extremely small leakage current flows. However _, the SiO ₂ film exhibits such good insulating properties only when the thickness of the SiO ₂ film is approximately 500 Å or more. When a voltage of about 20 V is applied to this SiO ₂ film, an electric field of about 10 ⁷ V/cm or more is generated, and this electric field causes electrons to jump from the negative electrode side to the positive electrode side over the energy barrier of this SiO ₂ film. The current flows through the SiO ₂ film without passing through the forbidden band of the SiO ₂ film. this is,
This is the already well-known Fowler-Nordheim tunneling phenomenon (hereinafter referred to as "tunneling phenomenon"), and this tunneling phenomenon is bidirectional in that electrons can move in either direction according to the direction of the electric field generated in the SiO ₂ film. be. EEPROM is a memory transistor that utilizes this tunneling phenomenon.

An example of an n-channel EEPROM using a floating gate memory cell having a field effect transistor (FET) structure will be described below.

FIG. 1 is a side sectional view showing a memory cell portion of a conventional n-channel type EEPROM.

In the figure, 1 is a p-type silicon (Si) substrate, 2
and 3 are an n-type drain impurity diffusion layer (hereinafter referred to as "drain") and an n-type source impurity diffusion layer (hereinafter referred to as "source") formed at a predetermined distance from each other on one main surface of the p-type Si substrate 1, respectively. ), 4 is a SiO ₂ film formed over each surface of the drain 2, source 3, and p-type Si substrate 1. 5 is a floating gate conductor layer (hereinafter referred to as "floating gate conductor layer") embedded in the SiO ₂ film 4 so as to pass from above the drain 2 to above the p-type Si substrate 1 between the drain 2 and the source 3 and reach above the source 3. 6 is a SiO ₂ film 4 between the end of the floating gate 5 on the drain 2 side and the drain 2. The film thickness is set to about 10 to 300 Å so that the tunneling phenomenon can occur. This is a tunnel SiO ₂ film. The thickness of the SiO ₂ film 4 immediately below the floating gate 5 other than the end on the drain 2 side is set to 500 Å or more to prevent tunneling. 7 is
A control gate conductor layer (hereinafter referred to as "control gate") is buried above the floating gate 5 in the SiO ₂ film 4 at a distance that prevents a tunneling phenomenon from occurring between the floating gate 5 and the floating gate 5. It is.

Next, the operation of this conventional example will be explained.

Here, charging the floating gate 5 with electrons is called writing, and releasing electrons from the floating gate 5 is called erasing.

First, in the case of writing, the drain 2, source 3 and p-type Si substrate 1 are grounded, and the tunnel SiO ₂
When a positive voltage is applied to the control gate 7 with respect to the p-type Si substrate 1 so as to generate an electric field of a magnitude necessary to cause a tunneling phenomenon in the film 6, electrons are
Tunnel SiO ₂ from Si substrate 1 through drain 2
It passes through the membrane 6 by tunneling and is injected into the floating gate 5. The floating gate 5 is charged by the electrons injected into the floating gate 5, and writing is completed. Since the floating gate 5 is surrounded by the SiO ₂ film 4, the electrons that have charged the floating gate 5 are retained in the floating gate 5 even if the positive voltage applied to the control gate 7 is removed. There is.

Next, in the case of erasing, the control gate 7, source 3 and p-type Si substrate 1 are grounded, and the tunnel SiO ₂
When a positive voltage is applied to the drain 2 with respect to the p-type Si substrate 1 so as to generate an electric field of a magnitude necessary to cause a tunnel phenomenon in the film 6, tunneling occurs.
An electric field is generated in the SiO ₂ film 6 in the opposite direction to that in the writing case, and the electrons accumulated in the floating gate 5 pass through the tunnel SiO ₂ film 6 from the floating gate 5 to the p-type via the drain 2. It is released onto the SiO substrate 1, and erasing is completed.

Furthermore, in the case of reading, since the threshold voltage of the control gate 7 changes depending on whether or not electrons are accumulated in the floating gate 5, the drain 2 and source 3
Logic signals of "1" and "0" can be obtained depending on the ON state and OFF state in between.

Generally, tunneling SiO ₂ by tunneling phenomenon
Some of the electrons passing through the film are captured by traps in the tunnel SiO ₂ film and remain in the tunnel SiO ₂ film, and the number of remaining electrons in this tunnel SiO ₂ film is proportional to the number of times the electrons pass through the tunnel SiO ₂ film. and increase.

[Problems to be Solved by the Invention] Incidentally, in the memory cell of this conventional example, since electrons pass through the same tunnel SiO ₂ film 6 during writing and erasing, the tunnel SiO ₂ film 6
The number of electrons remaining in the memory increases in proportion to the number of times writing and erasing are repeated.
Therefore, even if the number of rewrites is small, enough electrons remain in the tunnel SiO ₂ film 6 to change the threshold voltage of the control gate 7, making rewriting impossible, which shortens the lifespan of the memory cell. There were flaws. In addition, since the direction in which electrons move during writing and the direction in which electrons move during erasing are completely opposite, the tunnel SiO ₂ film 6 deteriorates more quickly than when the electrons move in one direction. However, it also had the disadvantage of poor memory cell reliability.

This invention has been made in view of the above-mentioned drawbacks, and includes a semiconductor substrate on which a source diffusion layer and a drain diffusion layer are formed.
A floating gate is formed above these two diffusion layers via a tunnel insulating film in which each part on the drain diffusion layer has the same thickness, and a floating gate is formed above the tunnel insulating film through a second insulating film. By forming a control gate with approximately the same width as , and writing charges into the floating gate from either the source side or the drain side, and reading charges from the other side,
Memory cells that can write and erase charges to the floating gate using different paths, reduce charge retention in the insulating film, have good reliability, have a long life, are easy to erase, and have fast data read speeds. An object of the present invention is to provide a method for writing and erasing a nonvolatile memory.

[Means for Solving the Problems] In order to achieve the above object, the present invention includes a drain impurity diffusion layer and a source impurity diffusion layer formed on the main surface of a semiconductor substrate at a predetermined distance from each other, and the semiconductor substrate and the source impurity diffusion layer. a first insulating film formed over each surface of the drain impurity diffusion layer and the source impurity diffusion layer; a floating gate conductive layer disposed on the first insulating film; and a floating gate conductive layer disposed on the first insulating film. In a method for writing and erasing a nonvolatile memory cell having a control gate conductor layer disposed on a body layer facing each other with a second insulating film interposed therebetween, the floating gate conductor layer is connected to the drain impurity diffusion layer. from above, passing above the semiconductor substrate between the drain impurity diffusion layer and the source impurity diffusion layer, reaching above the source impurity diffusion layer, and directly below the floating gate conductor layer in the first insulating film. The thickness is the same within the range of 10 to 300 Å, and a positive potential is applied to the control gate conductor layer, and the control gate conductor layer is applied to one of the drain impurity diffusion layer and the source impurity diffusion layer. Applying a potential lower than the positive potential applied to the body layer to cause electrons to pass through the first insulating film located on the one impurity diffusion layer side and accumulate in the floating gate conductor layer, and perform the control described above. A ground potential is applied to the gate conductor layer, and a positive potential is applied to the other impurity diffusion layer of the drain impurity diffusion layer and the source impurity diffusion layer to separate the other impurity diffusion layer and the floating gate conductor. A semiconductor nonvolatile memory device characterized in that electrons accumulated in the floating gate conductor layer are extracted to the other impurity diffusion layer by a tunneling phenomenon of the first insulating film interposed between the floating gate conductor layer and the floating gate conductor layer. The present invention aims to provide a writing and erasing method.

[Embodiment of the Invention] Figure 2 shows an n-channel type embodiment of the invention.
FIG. 3 is a side sectional view showing a memory cell portion of an EEPROM.

In the figure, the same reference numerals as those of the conventional example shown in FIG. 1 indicate equivalent parts, and the explanation thereof will be omitted.

6c is a SiO ₂ film formed directly under the floating gate 5, and has the same film thickness on the drain 2, the source 3, and the semiconductor substrate between them, and the film thickness is set so that a tunneling phenomenon can occur. 10~300
This is a tunnel SiO ₂ film with a thickness of approximately 1.5 Å.

Next, the operation of this embodiment will be explained.

First, for writing, source 3 and p-type
The Si substrate 1 is grounded, and a positive voltage is applied to the p-type Si substrate 1 so as to generate an electric field of a magnitude necessary to cause a tunnel phenomenon in the drain-side tunnel SiO ₂ film and _the source-side tunnel SiO 2 film. is applied to the control gate 7, and a positive voltage of the same order of magnitude is also applied to the drain 2. In this state, since the control gate 7 and the drain 2 _{are at almost the same potential and there is no potential difference, almost no electric field is generated in the drain side tunnel SiO 2 film} .
without tunnel injection of electrons into
Electrons pass from the p-type Si substrate 1, through the source 3, through the source-side tunnel SiO ₂ film by a tunneling phenomenon, and are injected into the floating gate 5. The floating gate 5 is charged by the electrons injected into the floating gate 5,
Writing ends.

Next, in the case of erasing, the control gate 7, the source 3
Then, the p-type Si substrate 1 is grounded, and a positive voltage is applied to the drain ₂ with respect to the p-type Si substrate 1 so that an electric field of a magnitude necessary to cause a tunnel phenomenon in the drain-side tunnel SiO 2 film is generated. When the voltage is applied, the electrons accumulated in the floating gate 5 pass through the tunnel SiO ₂ film from the floating gate 5 by a tunneling phenomenon and are emitted to the p-type Si substrate 1 via the drain 2, thereby completing erasing.

Furthermore, since the readout is similar to the readout in the conventional example shown in FIG. 1, the explanation thereof will be omitted.

In the memory cell of this example, electrons are made to pass through the source-side tunnel SiO ₂ film and the drain-side tunnel SiO ₂ film by tunneling during writing and erasing, respectively.
The rate at which the number of electrons remaining in each SiO ₂ film increases in proportion to the number of rewrites is 1/2 compared to the rate at which the number of remaining electrons increases in the conventional memory cell shown in Figure 1. The number of times of rewriting until the memory cell becomes unrewritable is twice the number of times that it can be rewritten in the case of the conventional memory cell, and the life of the memory cell can be extended. Furthermore, the direction of movement of electrons in both tunnel SiO ₂ films due to the tunneling phenomenon is unidirectional, which suppresses deterioration of the both tunnel SiO ₂ films, compared to both directions in the case of the conventional memory cell described above. Because you can
The reliability of memory cells can be improved.

In addition, in this embodiment, the thickness of the first insulating film 4c formed on the semiconductor substrate 1 on which the source 3 and drain 2 are formed, over the two diffusion layers 2, 3 and the surface of the semiconductor substrate 1 between them is as follows: The thickness of the first insulating film is set to 10 to 300 Å, which can cause a tunnel phenomenon, and the thickness is made the same on the source 3, the drain 2, and the semiconductor substrate 1, so that the thickness of the first insulating film in the portion that contacts the substrate is It is the same and thinner than the part that contacts the source and drain, so the capacitance between the substrate and the floating gate is large, and when _Vcc is raised, the potential difference (electric field) between the floating gate and the source (drain) increases. This makes erasing easier, and because the distance between the floating gate and the substrate is narrow and the electric field generated in the channel is large, a large amount of channel current can flow between the source and drain, making readout faster. can be done.

Although the present invention has been described using an n-channel type EEPROM memory cell as an example, the present invention is not limited thereto, and can also be applied to a p-channel type EEPROM memory cell.

[Effects of the Invention] As explained above, the method for writing and erasing a semiconductor non-volatile memory device of the present invention is to write and erase a semiconductor non-volatile memory device by using a first insulating film on a semiconductor substrate on which a source diffusion layer and a drain diffusion layer are formed. A floating gate is formed above the two diffusion layers, and a control gate with approximately the same width as the floating gate is formed above the floating gate via a second insulating film, and charges are not written to the floating gate. Since it is done from either the source side or the drain side, and the charge is read from the other side,
The rate at which the number of carriers remaining in the drain-side tunnel insulating film and the source-side tunnel insulating film increases in proportion to the number of rewrites is 1/1/2 compared to the rate of increase in the number of residual carriers in the conventional example. 2, the number of rewrites can be doubled compared to the conventional example, and the life of the memory cell can be extended. Furthermore, since the direction of carrier movement in both tunnel insulating films due to the tunneling phenomenon is unidirectional, deterioration of both tunnel insulating films can be suppressed compared to the bidirectional movement in the conventional example. This makes it possible to improve the reliability of memory cells.

[Brief explanation of the drawing]

FIG. 1 is a side cross-sectional view showing a memory cell portion of a conventional n-channel type EEPROM, and FIG. 2 is a side cross-sectional view showing a memory cell portion of an n-channel type EEPROM according to an embodiment of the present invention. In the figure, 1 is a p-type Si substrate (first conduction type semiconductor substrate), 2 is an n-type drain impurity diffusion layer (second conduction type drain impurity diffusion layer), and 3 is an n-type source impurity diffusion layer (second conduction type). 4 is a SiO ₂ film (insulating film), 5 is a floating gate conductor layer, 6c is a tunnel SiO ₂ film (first insulating film), and 7 is a control gate conductor layer. .
Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A drain impurity diffusion layer and a source impurity diffusion layer formed at a predetermined distance from each other on the main surface of a semiconductor substrate, and formed over each surface of the semiconductor substrate, the drain impurity diffusion layer, and the source impurity diffusion layer. a first insulating film, a floating gate conductor layer disposed on the first insulating film, and a second insulating film disposed on the floating gate conductor layer.
In a method for writing and erasing a nonvolatile memory cell having a control gate conductor layer facing each other with an insulating film interposed therebetween, the floating gate conductor layer diffuses the drain impurity from above the drain impurity diffusion layer. The first insulating film has a thickness of 10 to 300 Å directly under the floating gate conductor layer. A positive potential is applied to the control gate conductor layer, and a positive potential is applied to the control gate conductor layer to one of the drain impurity diffusion layer and the source impurity diffusion layer. Applying a potential lower than the potential of , electrons are accumulated in the floating gate conductor layer by passing through the first insulating film located on the one impurity diffusion layer side, and are grounded to the control gate conductor layer. Applying a potential and applying a positive potential to the other impurity diffusion layer of the drain impurity diffusion layer and the source impurity diffusion layer to interpose between the other impurity diffusion layer and the floating gate conductor layer. A method for writing and erasing a semiconductor nonvolatile memory device, characterized in that electrons accumulated in the floating gate conductor layer are extracted to the other impurity diffusion layer by a tunneling phenomenon of the first insulating film.