JPH0481838B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a signal input section of a word line or bit line selection gate circuit thereof.

[Conventional technology]

Some word line selection gate circuits for bipolar static RAM have the configuration shown in FIG. The MCA is a memory cell array, which is not shown, but is made up of pairs of word lines and bit lines extending vertically and horizontally, and flip-flop type memory cells arranged at each intersection of these word lines and bit lines. G1, G2, ... are word lines (the same applies to bit lines, but we will focus on word lines here)
Gate circuit for selection, decoder line DL
It receives an input signal and generates a word line selection output (sets the word line to H level). This decoder line DL is divided into two groups, group A and group B, and each group has multiple wires, of which only one is at L (low) level and the rest are at H (high) level. be made into

The gate circuits G1, G2, ... are two-input NOR gates, one input is connected to group A, the other input is connected to group B, and both inputs are at L level.The gate circuit outputs H level word line selection output. arise. In this example, there are two wires each in groups A and B, and if they are numbered 1, 2, 3, and 4 as shown in the figure, the gate circuit G1 will be the same as when 2 and 4 are L. Gate circuits G2, G3, and G4 generate H level outputs that select the word line when 1 and 4, 2 and 3, and 1 and 3 are L.

In this method, one wiring in the group is L, and when both inputs are L, a word line selection output is generated, so
If the number of wires in a group is m, one of m×m word lines can be selected, and the number of decoder lines is m
+m lines, so the larger m is, the greater the saving effect on decoder lines becomes.(If the decoder lines are not grouped and the gate circuits G1, G2,... m×m
Book).

The circuit that receives the address signal and drives the decoder line DL has a configuration as shown in FIG. This circuit has four wires for driving group A, and the address signal used for this is two bits A1 and A2. Q1 to Q6 are transistors, R1 and R2 are transistors, CS is a constant current source, and such a circuit is provided for each bit of the address signal. Q7,
Q8 is the output transistor of the circuit for bit A2 and corresponds to its Q5 and Q6 for A1. In this circuit, when A1 is H with respect to the reference voltage V _R , transistor Q1 is turned on and Q2 is turned off, transistor Q5 receives an H level input, and Q6 receives an L level input. H
Set level 3 and 4 to L level. When address signal bit A2 is also set to H, Q7 similarly receives an H input and Q8 receives an L input, and the A group decoder lines 1 and 3 are set to the H level and 2 and 4 are set to the L level. These have a wired-or configuration, so 1 to 3 are H,
4 becomes L, and only one wiring in the group becomes L. A1
=L, A2=H then 2, A1=H, A2=L then 3, and A1=A2=L then 1 becomes L. The same applies to the B group drive circuit.

The NOR gates G1, G2, . . . consist of transistors Q11 to Q13, a resistor R, and a constant current source CS, as shown in FIG.
The base of No. 2 is connected to one of the wires of Group A and Group B shown in Figure b, and receives signals V _A and V _B. Reference voltage V _R
On the other hand, if V _A and V _B are L, Q11 and Q12 are turned off, Q13 is turned on, and the output Vo becomes H.
This is one word line of the memory cell array MCA.
drive one.

[Problem that the invention seeks to solve]

Decoder line DL and gate circuits G1, G2,
The two input terminals of ... are connected by wiring l ₁₁ , l ₁₂ , l ₂₁ , l ₂₂ , ... as shown in Fig. 3, but
The wiring has a distributed capacitance C, which creates resistance and time constant of the wiring, which hinders high-speed operation. In order to reduce this wiring parasitic capacitance, one input terminal of each adjacent gate is short-circuited to each other as shown in Fig. 4, and a common wiring l ₁₃
Therefore, a method has been considered in which the decoder line DL is connected to the corresponding wiring. Since this wiring _l13 corresponds to the wirings _l12 and _l22 in FIG. 3, if one line is used in common, the parasitic capacitance can be halved. Furthermore, gate G
Since the distance between gates G1 and G2 is minute, the gates G1 and G2
The parasitic capacitance of the wiring ₁₄ for shorting the input terminals of 2 can be ignored.

The wiring parasitic capacitance can be reduced by the method shown in Fig. 4, but since the wiring l ₁₁ , l ₂₁ , . remains unchanged, and measures to reduce parasitic capacitance are insufficient. The present invention aims to improve these points, further reduce the wiring capacitance, and contribute to high-speed memory operation.

[Means for solving problems]

The present invention is divided into two groups, and the wiring in each group is one
In a semiconductor memory device comprising a plurality of gate circuits that receive an input signal from one wire of each group of decoder lines and generate a word line or bit line selection output, only one of which is set to a different level from the others, the gate circuit and the decoder line The connection is made by short-circuiting the signal input terminals of adjacent gate circuits to each other and connecting them to one wiring of each group of the decoder lines through a common wiring.

Referring to FIG. 1, the same parts in this figure as in FIGS. 3 and 4 are given the same reference numerals. As is clear from comparing these figures, in the present invention, adjacent gate circuits G1 and G2, G2 and G3, G3 and G
4. Wire each one of the input ends of l ₁₄ , l ₂₄ ,...
and connect these to the corresponding wiring of the decoder line DL through common wiring l ₁₃ , l ₂₃ , . . .
If you do this, the wiring l ₁₁ , l ₂₁ , . . . in Fig. 3 will be connected.
It is also possible to reduce the parasitic capacitance by half, and a large parasitic capacitance reduction effect can be obtained as a whole.

Of course, even if you connect the gate circuit as shown in Figure 1,
There is no problem with word line selection. That is, as is clear from the figure, G1 is 2 and 4, G2 is 2 and 3, and G3 is 1.
and 3, G4 produce an H level output when 1 and 4 are L, which is the same as in FIGS. 3 and 4. However, due to the condition that the input terminals of adjacent gate circuits are short-circuited and connected to the decoder line by a common wiring, the order of the word lines selected as the address signal bits A1, A2, etc. change is as shown in Figure 1. 3 and 4 are different. For example, in Fig. 3, if address signal bits A1 and B1 are 00 and G1 produces a selection output, then at 10 G2 produces a selection output, at 01 G3 produces a selection output, and at 11 G4 produces a selection output, and this point is the same in Fig. 4. but,
In FIG. 1, G1 produces a selection output at 00, G2 at 01, G3 at 11, and G4 at 10. However, in a memory, there is generally only a one-to-one correspondence between the address signal bit group and the selected word line.
Which word line is actually selected is left to the mask pattern designer, and the address 00
...00, 00...01, 00...10, 00...11,..., the word line is selected in the order of 1st, 2nd, 3rd, 4th, etc. from the end, without fail. It's not that it's happening that way. Therefore, changing the selection order is not a particular problem.

Short-circuit the input ends of adjacent gate circuits and connect the common wiring to the corresponding wiring of the decoder line.
This is possible even if the number of gate circuits increases. FIG. 2 shows the connection state of gate circuits G1, G2, . . . in a circuit in which groups A and B each consist of four wires, and therefore 4×4=16 word lines can be selected. Each gate circuit receives one input from Group A and Group B, and adjacent input terminals are short-circuited and connected to the corresponding wiring of the decoder line through a common wiring. As is clear from the drawing, each Noah gate G1, G2,
... produces an H level output in the following cases.

G1: 1 and 8 are L G9: 3 and 8 are L G2: 1 and 7 are L G10: 3 and 7 are L G3: 2 and 7 are L G11: 4 and 7 are L G4: 2 and 6 are L G12 :4 and 6 are L G5:1 and 6 are L G13:3 and 6 are L G6:1 and 5 are L G14:3 and 5 are L G7:2 and 5 are L G15:4 and 5 are L G8: 2 and 8 are L G16: 4 and 8 are L G16: Only the outer input terminals of the gates G1 and G16 at both ends have no partner to be shorted, and are wired independently. It can be expanded in the same way even if the number of gate circuits is 32, 64, etc. In addition, the gate circuit is high with L level input.
A level selection output is generated, but this may be such that an H level input generates an H level selection output.
In this case, naturally, the gate circuits G1, G2, . . . become AND gates, and only one decoder line in the group becomes H, and the rest become L.

〔Effect of the invention〕

As described above, according to the present invention, the parasitic capacitance of the wiring connecting the gate circuit and the decoder line can be further reduced, contributing to higher speed memory operation.

[Brief explanation of the drawing]

1 and 2 are explanatory diagrams of the present invention, and FIGS. 3 to 6 are explanatory diagrams of conventional circuits. In the drawing, DL is the decoder line, G1, G2,...
... is a gate circuit, MCA is a memory cell array,
l ₁₄ , l ₂₄ , . . . are short-circuit wirings, and l ₁₃ , l ₂₃ , . . . are common wirings.

Claims (1)

[Claims] 1. The decoder lines are divided into two groups, and only one line in each group has a different level from the others.The decoder line receives an input signal from one line in each group, and selects a word line or bit line. In a semiconductor memory device including a plurality of gate circuits that generate outputs, the gate circuits and decoder lines are connected by shorting the signal input terminals of adjacent gate circuits to each other and connecting them to one wiring of each group of decoder lines through a common wiring. 1. A semiconductor memory device characterized by performing the following steps.