JPH048966B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable delay circuit, and more particularly to a variable delay circuit whose delay time changes in response to a control signal indicating the delay time.

In encoding devices used in pulse code modulation (PCM) communication systems, when a similar pattern appears repeatedly in the modulated signal, the modulated signal is extracted and encoded by extracting only the changes in the repeated pattern. redundancy can be removed and highly efficient encoding can be performed. For example, when the modulated signal is a television signal, the image frame is divided into a plurality of blocks in advance, and a motion detection circuit is installed to detect the motion of the block with the highest degree of correlation between frames. A method has been proposed that performs high-efficiency encoding in response to the detection result of a motion detection circuit. The motion detection circuit calculates the degree of correlation between a predetermined block in a frame and the predetermined block and its surrounding blocks in the next frame by calculating the sum of differences between the television signals of two blocks that correspond between frames. Calculate by At this time, the corresponding 2
A variable delay circuit is required to align the timing of the two blocks of television signals.

FIG. 1 is a block diagram for explaining a conventional variable delay circuit. Variable delay circuit 1 shown in the same figure
includes a plurality of delay devices 11-1 to 11-n (where n is a predetermined positive integer) and a selector 20. The input signal is a signal obtained by sampling a television signal using a clock signal having a predetermined period and encoding it into a digital signal having a predetermined number of bits, and is sent to delay units 11-1 to 11-n, respectively. Delay device 11-1 to 11-
Each of the shift registers n delays the input signal by a delay time that is an integral multiple of the period of the clock signal and sends it to the selector 20. delay device 11 or 1
The delay times n are preset to different values. The control signal is transmitted through delay devices 11-1 to 11-
This is a digital signal that specifies any one of n, and is sent to the selector 20 as a selection signal. The selector 20 is a data selector, and selects only one signal specified by the control signal from among the signals sent from the delay devices 11-1 to 11-n, and sends it as an output signal.
The output signal at this time is a signal obtained by delaying the input signal by the delay time of the delay device specified by the control signal.

Such a conventional variable delay circuit 1 includes a plurality of delay devices 11-1 to 11-n each having a predetermined delay time, and the delay time can be changed by selecting one of them. There is.
However, when applied to the above-mentioned motion detection circuit, for example, if the number of blocks is increased in order to perform detailed motion detection, the number of combinations in which blocks are made to correspond between frames increases, and the number of combinations that correspond to blocks between frames increases. The number of delay times for aligning signal timing increases. In such a case,
There is a drawback that the number of delay devices increases and the size of the variable delay circuit 1 increases.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a small variable delay circuit that uses fewer parts.

The variable delay circuit of the present invention writes a digital signal received from the outside to a write address location in response to an externally applied clock signal indicating write and read timing, and writes a digital signal received from the outside to a write address location, and writes the digital signal received from the outside to a read address location. a storage means for reading and transmitting a digital signal; a counter means for counting the clock signal by a counter that is reset at a constant cycle; and a first address for generating a first address by adding a constant value to the counted value of the counter means.
a second address generating means for generating a second address by adding a control signal indicating a delay time given from the outside and a count value of the counter means; and address indicating means for sending the first address signal to the storage means when the clock signal indicates the reading timing, and sending the second address signal to the storage means when the clock signal indicates the reading timing. .

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. In the variable delay circuit 3 of this embodiment, as in the case of FIG. A control signal indicating the input signal and a clock signal synchronized with the input signal are sent. The input signal is sent to read/write memory (RAM) 31, and the control signal is sent to adder 3.
3, and the clock signal is sent to counter 32, selector 21 and RAM 31. The counter 32 is a 2m-adic counter (where m is a predetermined positive integer), that is, a counter whose count value is reset to the initial value "0" when the 2m-th counting input is applied. is counted, and a signal indicating the counted value is sent to one input terminal of each of adders 33 and 34. The adder 33 sends a signal a obtained by adding the control signal and the count value signal of the counter 32 to the selector 21 . The adder 34 sends to the selector 21 a signal b obtained by adding the signal Dm indicating a predetermined integer m and the count signal of the counter 32. Adders 33 and 34 both perform remainder addition modulo the integer 2m. Signal b indicates a write address of an input signal to RAM 31, and signal a indicates a read address of an output signal from RAM 31. Selector 21
When the clock signal indicates writing of an input signal (or reading of an output signal), selects signal b (or signal a) and sends it to RAM 31 as signal c.

When the clock signal indicates writing of an input signal (or reading of an output signal), the input signal is written to the address in the RAM 31 indicated by the signal c (or the input signal is written to the address in the RAM 31 indicated by the signal c).
The signal written at the address within is read out and sent out as an output signal).

FIG. 3 is a time chart for explaining the operation of the circuit shown in FIG. 2. The clock signal is
This is a pulse train in which the voltage becomes high level (H) for a predetermined time every predetermined period T, and is synchronized with the input signal. Also, when the clock signal is at H voltage,
This indicates writing of an input signal to the RAM 31, and indicates reading from the RAM 31 when the voltage is low level (L). When the count value signal of the counter 32 in FIG. 2 indicates the initial value "0", the signal a indicates the integer d indicated by the control signal, and the signal b indicates the integer m indicated by the signal Dm. . During this time, when the clock signal is at H voltage, signal c indicates an integer m, and when the clock signal is at L voltage, signal c indicates an integer d. Therefore, the RAM 31 in FIG. When , the input signal is written to the location at address m, and then when the clock signal becomes an L voltage, the signal written at location at address d is read out and sent out.

Each time the pulse of the clock signal rises, the count value of the counter 32 in FIG.
Since remainder addition is performed modulo , the write address and read address of RAM31 are (2m−
1) After reaching the address, return to address "0" again.
Therefore, when an input signal is written to the location m in the RAM 31 as described above, and immediately after that, the signal is read from the location d, the output signal is an integer d.
If is smaller than the integer m (or if the integer d is larger than the integer m), then (m-d) (or (3m-
d) input signal written immediately after the rising edge of the previous timing pulse, that is, the input signal is essentially delayed by (m-d) x T (or (3m-d) x T). It's a signal. This delay time can be changed by changing the integer d indicated by the control signal.The center delay time, that is, the delay time when the integer d is zero, is (m×T), and the variable step of the delay time is T. And the variable range is ±(m×T)
variable delay time characteristics can be obtained.

In this manner, the present invention controls writing to and reading from memory within one clock, and also completes supply of write addresses and read addresses to the memory within one clock. Therefore, data can be written to the memory in one clock and read out with any amount of delay. Also, the clock speed can be the same as the data speed of the television signal,
It becomes possible to easily configure a circuit with a speed of 10 Mb/s or more.

As explained above, in this embodiment, RAM3
By controlling the time difference between writing of an input signal and reading of an output signal in No. 1 using a control signal, a variable delay circuit that uses fewer parts and is smaller than the conventional one is realized. Note that if it is not necessary to set the center delay time to (m×T) as in this embodiment, the adder 34 in FIG.
It is clear that the same effect can be obtained by sending it as . Furthermore, when the input signal is an analog signal, it is obvious that the present invention can be applied by adding an analog-to-digital conversion means.

As is clear from the above description, the present invention has the advantage that it is possible to realize a small variable delay circuit using fewer parts than before.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional variable delay circuit, and FIGS. 2 and 3 are a block diagram and time chart showing an embodiment of the present invention. 1, 3...variable delay circuit, 11-1 to 11-n
...Delay device, 20, 21...Selector, 31...
Memory for both reading and writing, 32... Counter, 3
3, 34... Adder.

Claims (1)

[Scope of Claims] 1. A digital signal received from the outside in response to a clock signal indicating write and read timings applied from the outside is written to the write address location and the digital signal written to the read address location. a storage means for reading and transmitting a signal; a counter means for counting the clock signal by a counter that is reset at a constant cycle; and a first address for generating a first address by adding a constant value to the counted value of the counter means. generating means; second address generating means for generating a second address by adding a control signal indicating a delay time given from the outside and a count value of the counter means; and a second address generating means for generating a second address, the clock signal indicating the write timing. and address indicating means for sending the first address signal to the storage means when the clock signal indicates the reading timing, and sending the second address signal to the storage means when the clock signal indicates the reading timing. variable delay circuit.