JPH0510866B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a thermal recording device, and particularly to a control circuit for thermal recording that generates gradation in the density of a recorded image (pixel).

[Background of the invention]

Thermosensitive recording creates characters and images by applying heat to paper that develops color due to heat, and the means for applying this heat is usually to run an electric current through a heating resistor.

The density (gradation) of the recorded image can be achieved by varying the amount of heat (energy) provided by the resistor, and usually by changing the magnitude of the current and the duration of the current. To change the current, change the voltage applied to the resistor. Also, if you want to change the energization time, use a timer or the like. In either case, control becomes complicated and the circuit scale increases. In particular, in thermal recording devices such as facsimiles, the number of heating resistors that are simultaneously controlled to be energized ranges from tens to hundreds, so the control circuit becomes quite large and often reduces reliability. .

FIG. 1 shows a conventional gradation control method, in which a number of timers are used to control a heat-sensitive resistor.
1 in the figure is a heat-sensitive resistor group, with heat-sensitive resistors 1A, 1B,
It consists of 1C,...etc. This group of resistors is present in the thermal head. Drive circuit group 2 includes drive circuits 2A, 2
B, 2C, . . . , etc., and provides electric energy for driving the heat-sensitive resistor. The timer group 3 consists of timers 3A, 3B, 3C, etc. The timer group 3 has an input terminal group 4, which consists of input terminals 4A, 4B, 4C, . . . .

A timer 3A corresponds to the input terminal 4A, which generates a pulse depending on the magnitude of the input signal (analog signal or digital signal) at the terminal 4A, and sends the pulse to the drive circuit 2A. That is, the duration of the pulse is made proportional to the magnitude of the input signal, and the pulse width can be modulated. The pulse is applied to a drive circuit 2A, where it is amplified in terms of power and applied to a heat-sensitive resistor 1A to generate heat.

That is, the pulse width (duration) of the drive pulse changes depending on the magnitude of the input signal, and the amount of heat (energy) generated changes accordingly, making it possible to control the density of the recorded image.

In this example, although timers are easy to control, it is usually difficult to integrate timers, and even if they can be integrated, many timers are
It is almost impossible to fit it inside the IC.

Various gradation control methods have been proposed to overcome these drawbacks. For example, in JP-A-56-92080, "Method for Forming Gradation Images Using a Thermal Printer," a method for forming gradation images by applying current to a thermal head with a pulse width proportional to the image density. A method of driving a heating element by modulating a signal into a plurality of pulse signals having a pulse width sufficiently smaller than the pulse width is described. In this method, since the pulse width is controlled by converting it into the number of pulses, the timer function can be provided by a counter and a clock pulse, and a timer is not required. However, even with this method, the circuit configuration and signal processing are quite complex.

[Summary of the invention]

The key point of the present invention is to use a shift register, decoder, data selector, etc. to change the application time of the voltage (current) to be applied to the heat-sensitive resistor according to the content of the gray scale signal, and to perform this operation in stages over time. Do it as many times as you like.

[Embodiments of the Invention] FIG. 2 shows a diagram of the principle of the present invention. The drive circuit 2 is controlled by the output of the shift register 5, and this output is a logic signal of "1" or "0". The shift register 5 has an input terminal 5A and a clock terminal 5.
B. It has a latch terminal 5C and a group of output terminals (this type of register is called a series type, and ordinary thermal heads are often equipped with this type of circuit), and the data at the input terminal can be clocked. Sequential reading is performed, and after the reading is completed, a latch signal is applied by 5C, and this data group is output to the output terminal.

Normally, 1, 2, and 5 are mounted on the head and are often formed as a single element. The input signal of the shift register 5 is a selector 6, a decoder 7,
It is provided through a shift register group 8. In other words, the data that controls the thermal head (1 or 0)
logic signal) is input terminal 8 of shift register group 8
given to A. This data is prepared in a number corresponding to the number of gradations (for example, 3 bits for 8 gradations), and the shift register group 8 is also prepared in the same number as this number of bits. That is, if this number of bits is N, there are N terminals of 8A and 8 register groups.
N output terminals are prepared. These N pieces of data are read into the register 8 every time a shift pulse is applied to the clock terminal 8B.

The number of registers in the shift register 8 is the same as the number of heat-sensitive resistors, and is usually about several hundred (often 126, 256, 512, etc.). N bits of the output data from the register 8 are input to the decoder 7, where they are decoded into ^2N outputs. That is, if we consider 3 bits as the input to the decoder 7, the output will be ²³ bits, or 8 bits.
The output of each of these is given to the selector 6.

The series of control operations in Figure 2 are shown in Figures 3 and 4.
This will be explained using FIG. In Figure 3,
It is assumed that the data includes information from gradation 1 to gradation 7, and this data is the output 8 of shift register 8.
It is given sequentially from C. Gradation level 1 between time t ₀ and _{t 1}
(For example, if the thermal line is 256 and the gradation is 3 bits, the decoder 7
There are three input lines to the shift register 5, and the number of register bits of the shift register 5 is 256. The following explanation assumes 256 lines and 3 bits of gradation information unless otherwise specified)
is sent to the shift register 5 through the decoder 7 and selector 6, and the gradation 1 is represented by the read signal pulse a generated at _t01 immediately before time _t1 .
The 0 or 1 bit signals are output from the shift register 5 at any time and applied to the drive circuit 2 (the read signal is applied to the terminal 5c of the register 5 in FIG. 2).

Next, between time _t1 and time _t2 , the information of gradation 2 is given to the register 5, and the register 5 is brought into an output state by the pulse b. At this time, the signal including the gradation is given to the decoder 7 from the output terminal of the register 8 as in the time t ₀ to _{t 1} , but the output signal from the selector 6 is the gradation 2.
The inside of selector 6 operates to represent this, and this operation is performed by a pulse signal from address generation circuit 9 (details of this operation will be described later).

As described above, the information on gradation 1 is set in the register 5 between times t ₀ and t ₁ and sent to the drive circuit, and the information on gradation 2 is set in the register between times t ₁ and _{t 2} . It is sent to the drive circuit and processed,
Thereafter, gradation 3 is processed between time _t2 and _t3 , gradation 4 is processed between time _t3 and _t4 , and each gradation is processed in the same way.
Gradation level 7 processing is performed between times t ₆ and t ₇ to complete the series of operations. That is, the gradation is controlled by repeating the operation seven times.

The above operation mainly describes the form of signals passing through register 8, decoder 7, selector 6, and register 5 in FIG. Figure 4 shows an explanation focusing on the following: These waveforms represent the flow of gradation information from time _t0 to _t1 , and the signals _a0 , _a1 , and _a2 are the outputs of the register 8, that is, the inputs of the decoder 7, and _a0 has a weight of 1 ( = 2 ⁰ gradation, a ₁ represents the gradation with weight 2 (= 2 ¹ ), and a ₂ represents the gradation with weight 4 (= 2 ² ). Pulse a ₀ , a ₁ , a ₂ There are 256 gradation information between time _t0 and _t1 , and in the figure, there are 256 pieces of gradation information between time _t0-1 , _t0-2 , _t0-3 ,
...t _0-256 corresponds to this.

The signals b ₁ , b ₂ , b ₃ , ..., b ₇ are output signals from the decoder 7 and are the decoded original signals a ₀ , a ₁ , a ₂ including gradations, and b ₁ is the output signal of gradation 1. , b ₂ is the gradation 2,...
..., b ₇ each represent gradation 7.

Signals a ₀ , a ₁ , a ₂ and decoder outputs b ₁ , b ₂ , ...,
The relationship with b ₇ will be described in detail later, but the signals a ₀ , a ₁ ,
For the decoder gradation information corresponding to the gradation information of a ₂ (expressed as 2 ⁰ × a ₀ + ^{2 1} × a ₁ + ^{2 2} × a ₂ ), all the gradation signals corresponding to below are output. Ru. For example, the gradation information between time t ₀₁ and t ₀₂ is a ₀ =
Since gradation level 1 is represented by "1", a ₁ = "0", and a ₂ = "0", only b ₁ among b ₁ to b ₇ is at the "1" level.
Next, in the tone information between time t ₀₂ and _{t 03} , only a ₁ is “1”
Therefore, the output b ₂ corresponding to gradation 2 and the output b ₁ below gradation 2 become “1” and enter the output state. Furthermore, since only a ₂ is "1" at time t ₀₃ to _{t 04} , the gray level is 4, and all of the signals b ₃ , b ₂ , and b ₁ below this, including b ₄ , are "1". Time t _0-4 ~
At _t0-5 , since _a0 and _a2 are "1", the gray level is 5, and _b5 , _b4 , _b3 , _b2 , _b1 are in the output state of "1".

That is, the signal b ₁ is always output as "1" when the tone is 1 or higher. This signal is transmitted from time t ₀ to _{t 1}
256 items are generated during this period, and are sequentially transferred to shift register 5 from time t _0-1 , and register 5 is transferred to shift register 5 by time t _01.
to go into. Then, they are read in by the register 5 by the pulse a of the read signal generated at time t ₀₁ , and all 256 outputs (which are a mixture of "1" and "0") are sent to the drive circuit 2 .

The signal processing performed from time _t0 to _t1 as shown in FIG. 4 is performed from time _t1 to _t2 , _t2 to _t3 , _t3 to _t4 , ₄ to _t5 , _t5
~t ₆ , t ₆ ~ _{t 7} are also performed, and signals related to gradation are created, but the gradation signal b ₁ ~ b ₇ selected at each time
corresponds as follows.

Time t ₀ - _{t 1} signal b ₁ (gradation 1) Time t ₁ - t ₂ signal b ₂ (gradation 2) Time t ₂ - t ₃ signal b ₃ (gradation 3) Time t ₃ - t ₄ signal b ₄ (gradation 4) Time t ₄ - t ₅ signal b ₅ (gradation 5) Time t ₅ - t ₆ signal b ₆ (gradation 6) Time t ₆ - t ₇ signal b ₇ (gradation 7) That is, When the control operations described above are performed in accordance with the order described above, a signal with a pulse width proportional to the number of gradations is obtained between times _t0 to _t7 . The waveform in FIG. 5 shows this. In the figure, LTH is a reading pulse and is the same as that in Figure 3. signal
D ₁ to D ₂₅₆ are signals given to each line of the thermal head, and there are 256 signals. When a read pulse is input at time t ₀₁ , data of gradation 1 is output from the output terminal of register 5, but at this time, data O ₁ of D ₁ corresponds to output O ₁ of gradation information b ₁ in Fig. 4. do.
Further, O ₂ of D ₂ corresponds to O ₂ of b ₁ , O ₃ of D ₃ corresponds to O ₃ of b ₁ , and so on. That is, information 1
The signal b ₁ with the data D ₁ to _{D 256} at time t ₀₁
It will be converted to when.

At time _t12 , the information _b2 of gradation 2 is read, and _P1 to _P8 in FIG. 4 are the same as P1 to _D1 to _D8 in FIG _.
P ₈ .... In other words, the gradation information P ₁ of the signal b ₂
〜P ₈ ... is the data D ₁ between time t ₁₂ and t ₂₃ in FIG.
〜D ₇ …… Q ₁ 〜Q ₈ …… will be obtained. Similarly below,
When the above control operation is performed and time t ₆₇ is reached, the information of gradation 7 is distributed to D ₁ to D ₂₅₆ , and after that,
At time tend, the register 5 is reset as shown in the figure to set all D ₁ to D ₂₅₆ to "0", completing the gradation control.

The control operation of the present invention is characterized by how the output of the decoder 7 is generated, and the operation of this decoder will be explained in detail below.

6 and 7 explain the operation of the decoder 7. FIG. 6 shows the input/output relationship of the conventional decoder, and FIG. 7 shows the input/output relationship of the decoder used in the present invention. As shown in the input signal-output signal characteristics in Figure 6, a conventional decoder performs one input signal (gradation information, signals a ₀ , a ₁ , and a ₂ in Figure 4) for one input signal. It only outputs an output signal. That is, the output signal b ₅ corresponds to the signal vi ₅ , and the output state corresponding to b ₅ is turned on. This decoder is compatible with octal decoders and decimal decoders that are already on the market.
The function is the same as that of an IC.

As shown in FIG. 7, the input/output characteristics of the decoder of the present invention are such that a plurality of output signals correspond to one input signal, and the output signal corresponds to the level of the input signal. , the state of the output signal also changes with the level of the input signal. In other words,
When the input signal is vi ₅ , the output signal is not only b ₅ , but also
All signals in the shaded part of the figure are output, and b ₁ , b ₂ ,
Five signals b ₃ , b ₄ , and b ₅ are turned on. In other words, this decoder has a function of outputting all of the lower outputs b ₄ , b ₃ , b ₂ , and b ₁ in addition to the conventional decode output b ₅ . This is the concept of the upper priority function mentioned above, and in combination with this decoder, a thermal recording method suitable for integration is obtained.

The decoder output generated in this way (if the information representing the gradation is 3 bits, there will be 7 logical signals.Actually, there are 8 because 2 ³ = 8, but since 0 is not considered to have a gradation, there will be 7 logical signals. ) becomes an input signal to the selector 6. The selector is a changeover switch having a selection function, and is controlled by a selection signal from the address generation circuit 9 to perform the switching operation. FIG. 8 shows a general configuration of the selector 6 (specific example for seven gradations), and the switch group 6B is the main configuration. As shown in FIG. 2, the selector has an input terminal 6A, an output terminal 6D, and a control terminal 6C. As shown in FIG. 8, the input terminal 6A has a plurality of input terminals 6A1, 6
A2, 6A3, . . . , 6A7, and output signals b ₁ , b ₂ , . . . , b ₇ from the decoder 7 are applied to each of them. The switch groups 6B are 6B1, 6B2,...
..., 6B7, and control signals C ₁ , C ₂ , ..., C ₇ are applied to each of these switches. When the control signal is turned on, the switch closes and operates to send one of the signals b ₁ to b ₇ to the output terminal 6D. The output terminal group 6D has a plurality of output terminals 6D1, 6D2, 6D3, . . . , 6D7, each corresponding to the input terminals 6A1 to 6A7.

Signals C ₁ to _{C 7} for controlling the opening and closing of the switches are generated by the address generation circuit 9, and the time sequence thereof is as shown in FIG. In Figure 9, signal CY
is a trigger signal applied to the input terminal 9B of the address generation circuit 9, and each time this signal arrives, the signal is
As shown in the figure, the levels of C ₁ , C ₂ , ..., C ₇ change from "0" to "1" to "0". signal
RS is a signal for resetting the address generation circuit (this is different from the reset in Figure 5), and in addition to the signal CY being applied,
Reset the rotation.

The signal as shown in the time sequence of Figure 9
_C1 to _C7 are generated sequentially. The signal _C1 becomes "1" from time _t0 to _t1 , and the switch 6B1 closes.
The signal _b1 is sent to the shift register 5 as a selection. As mentioned above, shift pulses (also called clock pulses) are applied to terminals 8B and 5B of shift registers 8 and 5 between times _t0 and _t1 to sequentially move the data in the registers. At this time, register 8 sends out data, and register 5 performs an operation of reading data.

As shown in the waveform of Fig. 4, the first wave after time t ₀
In response to the first shift pulse, the register 8 sends out the first data group of the gradation information that has been read, and provides these data to the decoder 7. The output of the decoder is selected by the selector 6, and since only the signal _C1 is in the "1" state at this time, only the lowest gradation information _b1 is sent to the register 5.

Next, the tone signal is read into the register 5 by the second shift pulse, and the register 8 sends out the second data of the read tone information. This data is similarly decoded by the decoder 7, selected by the switch 6B1 of the selector 6, and given to the register 5. This data is read into the register 5 by the third shift pulse.

Thereafter, a similar shift operation is performed, and when the shift operation is stopped when the number of shift pulses is exactly equal to the number of resistors in thermal resistor group 1, register group 8
The lowest gradation information _b1 is sent to the register 5 in order by the data equal to the number of heat-sensitive resistors,
It is set. In this state, when a data sending pulse is applied to the terminal 5C, all the data in the register is sent out in parallel to the driver 2, thereby providing power to the heat sensitive resistor group 1.

Since the number of heat-sensitive resistors is usually several hundred, if this is set to 256, for example, the number of shift pulses between times t ₀ and _{t 1} will be 256. That is, all information signals regarding 256 pixels are read into the register 5, and the time
At t ₀₁ , it is fed into the driver 2 and the head is driven. Since all the data in the register 8 is output between times t ₀ and _{t 1} , it is necessary to input the same data into the register 8 again during this period. For this reason, it is essential to input from the terminal 8A at the same time as the output.

At time _t1 , one carrier pulse CY is generated, so the signal _C2 becomes "1" and the switch 6
B2 becomes closed. Thereafter, the above operation is performed in the order of register 8 → decoder 7 → selector 6 → register 5 every time a shift pulse arrives. However, the gradation data at this time is not the lowest gradation signal, but a signal whose gradation is increased by 1 from this signal, and the output signal _b2 shown in FIG. 7 corresponds to this. That is, the period t ₁ ~
At time _t2, all data (256 pieces) related to the gradation output signal _b2 are processed, and at time _t2 , the head is driven.

Thereafter, the same operation is performed, and from time _t6 to _t7 , the highest gradation signal (corresponding to output signal _t7 in FIG. 7) is processed, completing a series of processes regarding all gradations. That is, at time _t7 , information of all gradations (7 gradations in this example) is given to the thermal head, and at this point, printing of pixels for one line is completed.

As described above, when the present invention is used, a decoder having a special function of giving priority to upper gradation information outputs the upper gradation information as "1" preferentially, and furthermore, all the gradation information below it is set to "1" state. Therefore, by sequentially selecting this information with a selector from the lowest gradation level and performing this selection operation sequentially for the number of gradations, it is possible to control the shading regarding thermal printing.

This method has the great advantage that it can be integrated, since a logic circuit can be used as the circuit and no timer or the like used in the conventional method is used.

FIG. 10 shows a specific embodiment of the present invention, in which the gradation signal is 3 bits and 7 gradations, and the number of heat-sensitive resistors, that is, the number of stages of the shift register is 256. Since the drive circuit and shift register attached to the heat-sensitive resistor head are often integrated, they are represented as a heat-sensitive head assembly 125 in this example.

The 3-bit information representing the gradation is input to the input terminal 8A1,
Given to 8A2 and 8A3. Shift register group 8
is composed of three registers 81, 82, 83,
Each has a number of stages of 265 bits. The shift operation of this register is performed by the clock pulse CP,
is applied to terminal 11.

In the initial state, the counters 91 and 92 of the address generation circuit 9 are reset, so the outputs of the address generation circuit are both "0", the AND gate group 61 is all closed, and the output D is It is “0”. Gradation data is read into registers 81, 82, and 83 between 1 and 255 clock pulses CP. CP is 256th shot, counter 91 is 1
Since the signal pulse CY is output and the contents of the counter 92 are incremented by 1, only one of the outputs of the decoder 93 is in the on state (meaning the output voltage is "1" state), and the gate g ₁ in the selector 6 is turned on. opens.
By opening this gate _g1 , the output of the decoder 7 is applied to the input 5A of the head assembly 125.

When the number of CP pulses is between 257 and 511, the outputs of the registers 81 to 83 sequentially output data by shift pulses, and these data are applied to the basic decoder circuit 71 of the decoder 7. The basic decoder circuit can be thought of as having the same function as that of an integrated circuit element that has already been integrated into an IC, and the 3-input-8-output octal decoder corresponds to this, and it corresponds to the input bit situation as shown in Figure 9. It generates outputs C ₁ to C ₇ like this. The OR gate group 72 is provided to give a higher priority function to the gradation information, and with this circuit configuration, a decoder having the function as shown in FIG. 7 can be realized. As can be seen from the connection of the OR gate group 72, in this circuit, when the data corresponding to the upper information becomes "1", the lower information also becomes "1".
becomes. This is achieved by sequentially sending the data of the upper information to the gate input of the lower information.

The above operation of the decoder 7 is always performed while input data is being added, and the gradation information is passed through the gate _g1 in the selector 6 to the head assembly 12.
The heat of the head is controlled at all times by the second carrier pulse CY, which is sequentially sent to the shift register No. 5 and generated at the 512th clock pulse CP.

After the 512nd clock pulse, only gate _g2 becomes open, and the data in the shift register 8 similarly passes through the decoder and selector to become gradation information. The above operation is repeated 7 times, and gate g ₇
completes all operations after performing the opening and closing described above.

In this embodiment, most of the circuits can realize AND and OR configurations, so the circuits can be integrated into ICs using general-purpose semiconductor processes.

FIG. 11 shows a modification of the present invention. In the explanation so far, the shift register 8 only has the function of shifting and storing, and it is necessary to input data while outputting it, and therefore, controlling the data coming into the input terminal 8A is complicated. The present invention has been modified to improve this point, and is basically based on the fact that input data is taken in only once, and the shift register 8 is used as a ring counter in subsequent operations.

First, when fetching the first data, output 99 of the address generation circuit is set to "0" and the AND gate 2
2 is closed, data input from input terminal 8A is applied to register 8 through OR gate 21, and all data is read into register 8 by performing a shift operation. Next, this gradation data is sent to the thermal head through the decoder 7 and selector 8, and at this time, the signal 99 is inverted and set to "1". In this state, the AND gate 22 is closed and the AND gate 23 is similarly opened. This results in output 8 of register 8
9 is applied to the entrance of the register 8 through the AND gate 23 and the OR gate 21, and this data is stored every time a shift pulse arrives. In other words, register 8 operates as a ring counter.

The subsequent operations are carried out in substantially the same manner, and the data representing the gradation is returned to the single input after leaving the register 8, and the data itself is not erased.
Therefore, no special measures are required to control the data applied to the terminal 8A, and the overall configuration of the device is simplified.

FIG. 12 shows a modification of the present invention. In this modified example, a memory circuit 110 is provided to store the contents of the gradation outputs _d1 to _d7 of the decoder 7 over all bits, and depending on this output state, an operation stop command is given to the address generation circuit 9, and the printing time is We aim to shorten the time. As shown in FIG. 4, the decoder 7 generates all gradation information b ₁ to b ₇ between times t ₀ and _{t 1} , so each of these signals is stored over all 256 bits. If you do this, you can immediately see how many gradations there are, and if you stop signal processing (printing) at this time, you can save time. FIG. 13 shows a specific example of a modification of FIG. 12. Gradation information
d ₁ to _{d 7} are led to a storage circuit 110. here,
One memory is placed corresponding to d ₁ to d ₇ , and one memory is placed corresponding to d ₁ to d 7.
If there is even one "1" in the bit information of _d7 , the memory is set to the output state. In other words, if the signal of _d1 is "1" between 256 bits from time _t0 to _t1 , _d1
The memory corresponding to is set to 1. This operation is also performed for each of d ₂ , d ₃ , . . . , d ₇ . The output of the memory is directed to a logic circuit 120,
Here, the output of the decoder 93 of the address generation circuit
A logical AND is performed with C ₁ to C ₇ , and all outputs of this logical product are logically determined by an OR circuit _OR1 . Signal C ₁ ~
_C7 occurs sequentially as shown in FIG. 9, and when the output of the memory circuit becomes "1" at each time, the output END of _OR1 always becomes "1". That is, when it is in the "1" state, there is a gradation, so signal processing continues, but when it is in the "0" state, there is no gradation, so signal processing is stopped. In other words, signals generated in a time series
The time can be shortened by sequentially checking the gradation information using _C1 to _C7 and determining that there is no gradation when the signal END disappears.

〔Effect of the invention〕

According to the present invention, it is possible to control the gradation, and since it does not require an element configuration such as a one-shot multi-chip device, which is difficult to implement in conventional ICs, it can be easily made into a single chip or a module.

[Brief explanation of drawings]

Figure 1 is a conventional circuit diagram regarding thermal gradation control.
Fig. 2 is a diagram of the principle of the present invention, Fig. 3 is an explanatory diagram of the operation of the present invention, Fig. 4 is a diagram of the signal processing mode of the present invention, and Fig. 5 is a diagram showing how to create a gradation signal of the present invention. , FIG. 6 is an operational diagram of the conventional decoder, FIG. 7 is an operational diagram of the decoder of the present invention, FIG. 8 is an explanatory diagram of the scanner operation, FIG. 9 is a diagram of the address generation situation, and FIG. 10 is the operational diagram of the decoder of the present invention. 11 is a circuit diagram of a modified example of the present invention, FIG. 12 is a block diagram of another modified example of the present invention, and FIG. 13 is a specific embodiment of the modified example in FIG. 12. It is a block diagram. 125...Thermal head assembly.

Claims (1)

[Scope of Claims] 1. A heating resistor is energized to generate heat in accordance with an image signal to be recorded, and this heat is transmitted to thermal recording paper to record an image gradation signal for coloring the thermal recording paper. a decoder that receives the output signal of the first storage section; a selector that selects the output of the decoder; a second storage section that receives the output of the selector; A heat-sensitive recording gradation control comprising: a head drive section that receives the output of the second storage section; a heat-sensitive resistor section that receives the output of the head drive section; and an address generation section for controlling each of the above sections. In the circuit, the output signal of the first storage section is outputted sequentially in time series to a decoder having a function of outputting up to the lowest gray level signal with respect to the input signal, and the decoder outputs the output signal sequentially from the lowest gray level signal to the input signal. A signal is repeatedly generated until the highest gradation is reached, and the gradation signal is sent to the selector and a separately provided third storage section, and the selector receives the signal sent from the decoder in response to the signal from the address generation section. Among the received gradation signals, the signals are selected so that the gradation level increases sequentially from the lowest gradation level, and are sequentially sent to the second storage unit, and the third storage unit selects the signals such that the gradation level increases sequentially from the lowest gradation level signal, and in the third storage unit, the signals are sent to the decoder. 1. A thermosensitive recording gradation control circuit, characterized in that a determining means for determining up to which gradation signal the output has information sends a signal for stopping signal processing to the address generation section.