JPH0512744B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] By connecting multiple processors, transferring data in word units, and adding invalid byte flags for start and end to the header words of the transferred data,
Enables information transfer in byte units.

[Industrial Application Field] The present invention relates to a system for efficiently transferring data between processors connected to a bus.

Usually, data transfer control between multiple processors is required for communication control between lines, etc.
It is desired to simplify data assembly and disassembly processing as much as possible.

[Prior Art] FIG. 3 is a diagram showing a conventional configuration of a data transfer system. In FIG. 3, 10 and 20 are processor CPUs, 11 and 21 are interprocessor communication devices connected to each processor, 12 and 22 are main memories MM for each processor, 13 and 23 are rearrangement control circuits for each processor, 14, 24 is a line control unit CCU, and 3 is a transmission bus. When data input to the processor 10 is transferred to the processor 20, for example, packet-switched data is input via the line control device 14. This data will be temporarily stored in the memory 12, and FIG. 4 shows an explanatory diagram of the processing operation when the stored data is transferred to the partner processor 20. 4A in FIG. 4A each indicate 1 byte of data stored in the main memory 12. In FIG. The inside of the memory is divided into blocks of several bytes (6 bytes and 4 bytes in the figure), and data is sequentially stored there. The data indicated by .about. is stored in a block with a starting byte address a and a number of bytes of 5 in the memory. In the example shown in FIG. 4A, the beginning is blank, and control information is stored there as necessary. When control information is not needed, data is stored starting from this blank area. If the number of data to be stored exceeds the first block (6 bytes in the figure), the data is packed to a predetermined position and then the data is stored from the beginning of the next block (4 bytes in the figure). Therefore, when data is stored across multiple blocks, there is no blank space between the blocks. The data indicated by ~ is stored in a block whose starting address is b (a value independent of a) and whose number of bytes is 4. Data ~ has a considerable amount of invalid bytes, such as another data area in the middle, so it is impractical to transfer the data as is to another processor because invalid byte information will also be transferred. . Also,
The inter-processor communication device 21 on the receiving side determines whether the beginning of the sent data is blank.
Therefore, when transmitting data, the rearrangement control circuit 13 rearranges the data by filling it in the buffer in the interprocessor communication device 11 from the beginning as shown in FIG. 4B. By doing this, the first byte sent is never an invalid byte. Therefore, the data is rearranged and packed into the buffer in the interprocessor communication device 11 by the rearrangement control circuit 13 as shown in FIG. 4B. Normally, the connection line to the interprocessor communication device 11 and the transmission bus 3 are capable of transmitting an even number of "stored bytes" in parallel. For example, two sets of storage bytes (16 bits)
It can be transmitted simultaneously, or 32 bits can be transmitted simultaneously.

Control information is sent at the beginning of transfer. The information is the number of bytes to be transferred (9 in this case) and the starting byte address (in this case an appropriate value c).
and send at position C. Next, the transfer data TXT is sent, and at that time, the flag provided in the headword adding section 16 of FIG. 4B is added to the beginning of the transfer data and transferred. In this case, the flag provided in the headword adding section 16 is set to the end invalid byte (end byte) flag EBF="1". This indicates that there is an invalid byte in the last word of data to be transferred (next in this case). Following the headword, data of an even number of bytes, for example, every 16 bits, is transferred from the interprocessor communication device 11 to another interprocessor communication device 21 via the transmission bus 3.

Next, in the other interprocessor communication device 21, the data exactly the same as that shown in FIG. 4B is stored in its internal buffer, and the data shown in FIG. 4C is obtained. Further data transfer in main memory 22 in processor 20 results in the situation shown in FIG. 4D. At that time, the data up to ~ are grouped together, although the arrangement differs from the original arrangement. ~
Since the flag EBF is “1” for
You can see that there is a blank space at the end.

[Problems to be Solved by the Invention] When data is transferred, the data is temporarily stored in a buffer in the interprocessor communication device, but at that time it is necessary to provide and operate a data rearrangement control circuit, which increases the hardware. There were flaws.

[Means for solving problems] The present invention will be explained using FIG.

FIG. 1 is a block diagram showing the basic configuration of the present invention, in which 10 and 20 are processor CPUs, 11 and 21
is an interprocessor communication device connected to each processor, and 12 and 22 are main memories for each processor.
MM, 14, 24 are line control units CCU, and 3 is a transmission bus. 10-1, 20-1 are inter-processor communication devices 11, 21 and processor 10,
A means of transferring multiple bytes in parallel between 20 and 20,
What each processor has, 11-1, 21-
Reference numeral 1 denotes means provided in the interprocessor communication devices 11 and 21, which attaches a header to data transferred from the processors 10 and 20, and transfers the same plural bytes in parallel to other interprocessor communication devices.

A communication system between multiple processors in which a plurality of processors each having a main memory and processing data in bytes are connected via a bus via an interprocessor communication device each having a buffer memory, and data is transferred between the multiple processors. The invention has the following configuration. That is, the processor is provided with means for parallelly transferring the data stored in the main memory word by word to the buffer memory of the interprocessor communication device, and the transfer data transferred to the buffer memory is transferred to the interprocessor communication device. A header consisting of a start invalid byte flag indicating the presence or absence of an invalid byte in the first word of the transfer data and an end invalid byte flag indicating the presence or absence of an invalid byte in the final word is attached to the transfer data, and multiple words are sent to the other interprocessor communication device. The processor is provided with means for transferring data in units of parallel in units of bytes, and at the time of data transfer, the processor transfers the data stored in the main memory in units of bytes to the storage area of the buffer memory as is in units of words by the parallel transfer means, The inter-processor communication device uses the parallel transfer means to
This is configured by adding the start invalid byte flag and the end invalid byte flag to the transfer data in the buffer memory before transferring the data.

[Operation] The present invention includes an address and a flag indicating the presence or absence of an invalid byte as control information for transfer control,
The interprocessor communication device that receives the transfer refers to the flag in the header word and stores it in the buffer, so that when the data is transferred to the main memory of the other processor, it can be stored immediately in the correct data arrangement.

[Example] An example will be described below with reference to explanatory diagrams of processing operations of the present invention in FIGS. 1 and 2. When data input to the processor 10 is transferred to the processor 20, for example, packet-switched data is input via the line control device 14. Assume that the data is stored in the main memory 12 as shown in FIG. 2A in FIG. 2A each indicate 1 byte of data, and 2 bytes form 1 word, so the starting word address α and the number of words in the memory are 3. Furthermore, the start invalid byte flag SBF is set to "1" to indicate that an invalid byte exists in the initial word. The start invalid byte SBF is taken into the headword together with the end invalid byte, which will be described later. Figure 2 A ~
is data with a start word address β and a word count of 2, and an end invalid byte (end byte) flag EBF is “1”. That is, this indicates that an exposure byte exists in the final word.

FIG. 2B shows the state in which the data is transmitted to the interprocessor communication device 11 and stored in the buffer. Further, the headword applying portion is shown as 17. At this time, each word is directly transferred and stored between the main memory 12 and the main memory 12 without using a rearrangement control circuit or the like. When transferring data from the interprocessor communication device 11 to another device 21, control information is transmitted before data, and the control information includes the following information: number of words to be transferred (3+2=5 words in this case), start word address (appropriate in this case) value δ)
and a flag indicating the presence or absence of a start invalid byte flag and an end invalid byte flag (in this case, the flag is present).

Furthermore, "1" is added to the beginning of the transfer data for the start invalid byte flag SBF and the end invalid byte flag EBF. The general format of the control information and transfer data is depicted adjacent to the transmission bus 3 in FIG.

In the other interprocessor communication device 21, the transferred data is temporarily stored in a buffer to obtain the data shown in FIG. 2C. Next, the data is directly transferred word by word to the main memory 22 to obtain the image shown in FIG. 2D.

[Effects of the Invention] As described above, according to the present invention, the data to be transferred stored in the main memory is transferred to the interprocessor communication device without being rearranged, so that processing operations can be speeded up.

[Brief explanation of drawings]

Figure 1 is a diagram showing the configuration of an embodiment of the present invention, Figure 2 is a diagram showing the configuration of an embodiment of the present invention.
1, FIG. 3 is a diagram showing a conventional configuration of a data transfer system, and FIG. 4 is an explanatory diagram of the operation of FIG. 3. 10,20...Processor, 10-1,20-
1... Data parallel transfer means, 11, 21... Inter-processor communication means, 11-1, 21-1... Data parallel transfer means, 12, 22... Main memory, 1
4, 24...Line control device, 17...Header attaching section, 3...Transmission bus.

Claims (1)

[Scope of Claims] 1. A plurality of processors 10, 20 having main memories 12, 22 and processing data in units of bytes are connected via a bus through interprocessor communication devices 11, 21 each having a buffer memory, In a multi-processor communication system in which data is transferred between processors 10 and 20, the inter-processor communication device 11 transfers data stored in the main memories 12 and 22 to each processor 10 and 20 in word units. means 10-1 for parallel transfer to the buffer memory of 21;
20-1 is provided, and the interprocessor communication devices 11 and 21 are provided with a start invalid byte flag (SBF) indicating the presence or absence of an invalid byte in the first word of the transfer data transferred to the buffer memory, and a start invalid byte flag (SBF) indicating the presence or absence of an invalid byte in the last word of the transfer data transferred to the buffer memory. means 11-1, 2 for attaching a header consisting of an end invalid byte flag (EBF) indicated to the transfer data to the other interprocessor communication devices 11, 21 in parallel in units of a plurality of words;
1-1, and during data transfer, the processors 10 and 20 are connected to the main memory 1.
The data to be stored in bytes in 2 and 22 is
The parallel transfer means 10-1, 20-1 directly transfer the data in word units to the storage area of the buffer memory; A communication system between a plurality of processors, characterized in that the transfer data in a buffer memory is transferred with the start invalid byte flag (SBF) and the end invalid byte flag (EBF) added.