JPH0512796B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a semiconductor memory device, and particularly to a dynamic random access memory with a so-called nibble mode function, in which a nibble cycle time is lengthened during nibble mode operation. The present invention relates to a semiconductor memory device that can lengthen the hold time of output data without having to do so.

(2) Background of the Technology Recently, semiconductor memory devices with a so-called nibble mode function have been used as image memories and the like. In nibble mode, after reading the input row address signal according to the row address strobe signal and column address strobe signal, data at multiple addresses can be read out at high speed by changing the column address strobe signal at a predetermined period. This is how it was done.

(3) Prior Art and Problems FIG. 1 is a time chart during nibble mode operation in a conventional semiconductor memory device. In other words, in a conventional semiconductor memory device, after the row address signal is received at the falling edge of the row address strobe signal and the row-related internal circuitry is activated, the column address signal is read when the column address strobe signal first falls. The signal is taken in, the column-related internal circuit and the output-related internal circuit are activated, and the output terminal is activated.
The first data DATA0 is output to D _OUT . Then, this output data DATA0 is reset by inactivating only the output system internal circuit at the rise of the column address strobe signal.
When the column address strobe signal falls again while the row address strobe signal is held at a low level, the output system internal circuit is activated again and the output data DATA1 at the next address is transferred to the output terminal D after a predetermined access time t _NCAC . Output from _OUT . Then, this output data DATA1 is reset when the column address strobe signal rises again. In this way, by sequentially turning on and off the column address strobe signal, data of a plurality of addresses can be sequentially output at high speed. and the row address strobe signal
The normal cycle time from when RAS falls to when the first data DATA0 is output, from rising to falling again, is approximately 2000 _os , whereas the period of the column address strobe signal during nibble operation, that is, the nibble cycle time. t _NC
is about 60 _os , so by using nibble mode it is possible to read data in about 1/3 of the normal cycle time.

However, in the conventional type, the column address strobe signal is at a low level for a time t _NCAS
The nibble cycle time t _NC is short, about 30 _os , which is half of the nibble cycle time _t is being output
_tDOH , that is, the hold time of the output data, becomes quite short, making it quite difficult to read the output data with an external circuit, and sometimes causing reading errors.

(4) Object of the Invention In view of the above-mentioned problems with the conventional type, an object of the present invention is to activate an output system internal circuit at the falling edge of a column address strobe signal in a semiconductor memory device with a nibble mode function to output data. Based on the concept of holding the output data until the next falling edge of the column address strobe signal after it is output, the hold time of the output data is lengthened without increasing the nibble cycle time during nibble mode operation. The object of the present invention is to improve the reliability of semiconductor memory devices by eliminating read errors.

(5) Structure of the Invention The object of the present invention is to read an input address signal in response to a row address strobe signal and a column address strobe signal, and then convert the column address strobe signal between a first level and a second level. A semiconductor memory device with a nibble mode function that sequentially outputs data at multiple addresses by repeatedly changing the column address strobe signal.
When the column address strobe signal changes from the first level to the second level, the output system internal circuit is activated, and the output data is held until the column address strobe signal changes from the first level to the second level again in the next cycle. This is achieved by providing a semiconductor memory device characterized in that it performs the following steps.

(6) Embodiment of the Invention FIG. 2 shows the timing of operation of a semiconductor memory device with a nibble mode function according to an embodiment of the invention. As shown in the figure, in the embodiment of the present invention, the row address strobe signal falls and the column address strobe signal is periodically turned on and off, thereby outputting data DATA0,
The point that DATA1, DATA2, DATA3, etc. are sequentially output every nibble cycle time t _NC is the same as in the case of the conventional type described above. However, as shown in FIG. 2, in the embodiment of the present invention, the column address strobe signal falls and after the nibble access time t _NCAC , the output data DATA0, DATA
1, . . . are output, but these output data are not reset at the rising edge of the column address strobe signal, but at the falling edge of the next cycle. Therefore, the output data hold time _tDOH can be made sufficiently long, and there is no need to increase the nibble cycle time _tNC to extend the output data hold time.

FIG. 3 shows a schematic configuration of a semiconductor memory device with a nibble mode function according to an embodiment of the present invention. The device in the figure has multiple word lines WL0, WL
1, WL2,..., WLn and multiple bit lines BL0,
It is composed of a memory cell array CLA having a plurality of memory cells MC connected between BL1, ..., BLm, a row address decoder RD, an input/output circuit IOC, a column address decoder CD output buffer BUF, an address counter CNT, etc. Ru.

In the device shown in FIG. 3, the input row address signal RA is taken into the row decoder RD in response to the fall of the row address strobe signal, and one word line, for example, WL1, is selected. Furthermore, at the time of the first fall of the column address strobe signal, the input column address signal CA is taken into the column decoder CD, and a column selection signal is generated in the column decoder CD and applied to the input/output circuit IOC. This allows the word line in memory cell array CLA to
The read signals from the memory cell MC connected to WL1 are simultaneously taken into the input/output circuit IOC, and four signals specified by the column decoder CD are sent through the data lines T0, T1, T2, and T3. Transferred to output buffer BUF. Output buffer
A count signal from an address counter CNT is applied to BUF, and the address counter CNT is, for example, a 4-bit counter and generates a count signal by counting the column address strobe signal. For example, four data lines T0, T1, T are connected depending on the count signal input to the output buffer BUF.
2. One of T3 is selected and the signal from the selected data line is sent to the output terminal D _OUT as output data.
is output from. In this case, the signal from the selected data line is held by a flip-flop or latch circuit provided within the output buffer.
More specifically, the output signal from the selected data line sets, for example, a flip-flop, and an output data signal is taken out from the output terminal of the flip-flop. It is about to be reset. This causes the output data to be held until the falling edge of the column address strobe signal. A gate circuit is provided in the output buffer BUF to select one of the signals from each signal line T0, T1, T2, T3 according to the value of the count value CT.

FIG. 4 schematically shows a memory system configured using a plurality of storage devices as shown in FIG. In the system shown in the figure, multiple memory devices MEM
(0,0),MEM(2,0),...,MEM(0,1),
MEM(1,1), MEM(2,1), etc. are arranged in a matrix. For example, the memory devices MEM(0,0) arranged in the same row,
A common row address strobe signal 0 is supplied to MEM(1,0), MEM(2,0),...
Also, the memory device MEM (0,
0), MEM (0, 1), etc. are connected to the same output line DO0. In this way, each memory device in the same row receives a common row address strobe signal.
RAS0, 1, . . . are applied, and the outputs from the memory devices arranged in the same column are respectively connected to common output lines DO0, DO1, DO2, . Note that a column address strobe signal, row and column address signals, read/write control signals, etc. are commonly input to all memory devices.

The operation of the memory system shown in FIG. 4 will be explained with reference to FIG. Consider a case where data is sequentially read out from memory devices assigned to the same column to a common output line. For example, row address strobe signal 0
is first set to a low level and the column address strobe signal is turned on and off at a predetermined period. At first, output data DATA0, DATA1, DATA2,
DATA3 is output. And the output data
At the time when DATA3 is output, the row address strobe signal 0 becomes high level, the column address strobe signal also remains high level, and the output line DO0 is connected to the memory device MEM.
The output data DATA3 from (0,0) remains output. Next, in this state, if the memory device MEM (0, 1) is selected and the row address strobe signal 1 connected to the memory device becomes low level, then the column address strobe signal is turned on and off at a predetermined period. By repeating this, output data DATA0, DATA1, . . . from the memory device MEM (0, 1) are sequentially output. On the other hand, the previously selected memory device MEM
For (0,0), the row address strobe signal 0 remains at high level and the column address strobe goes to low level, so the output of memory device MEM (0,0) cannot output data to DO0 again after being reset. do not have. With this configuration, it is possible to configure a large-capacity memory system using multiple memory devices, that is, memory packages, but even in such a memory system, outputs from multiple memory devices can be connected to a common output line. Data can be read accurately without being output simultaneously. That is, as shown in FIG. 5, the last output data DATA3 from the memory device MEM(0,0) is held until the fall of the column address strobe signal, but the next output data, that is, the memory device MEM(0, 1)
Since the first output data DATA0 from the column address strobe signal is output after a predetermined access time from the falling edge of the column address strobe signal, the output data from the memory device MEM (0,0) and the memory device (0,1) are different from each other. The output data will not overlap.

(7) Effects of the Invention As described above, according to the present invention, the output data, which was conventionally reset at the rising edge of the column address strobe signal, is reset at the falling edge of the next cycle. It becomes possible to lengthen the hold time of output data without increasing the time, and it becomes possible to completely prevent data reading errors and improve the reliability of the semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram for explaining the operation of a conventional semiconductor memory device with a nibble mode function, and FIG.
3 is a waveform diagram for explaining the operation of a semiconductor memory device with a nibble mode function according to an embodiment of the present invention, and FIG. 3 is a schematic diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention. block circuit diagram,
FIG. 4 is a block circuit diagram showing a memory system configured using a semiconductor memory device according to an embodiment of the present invention, and FIG. 5 is a waveform diagram for explaining the operation of the system shown in FIG. be. CLA...Memory cell array, RD...Row decoder, CD...Column decoder, IOC...Input/output circuit, BUF...Output buffer, CNT...Address counter, WL0, WL1, WL2,..., WLn
...Word line, BL0, BL1, BL2,..., BLm
...Bit line, T0, T1, T2, T3...Data line, MEM (0,0), MEM (1,0), MEM
(2,0),...,MEM(0,1),MEM(1,1),
MEM (2, 1), ... memory device, DO0, DO
1, DO2, ...output line.

Claims (1)

Claims: 1. Repeatedly changing the column address strobe signal between a first level and a second level after reading the input address signal in response to the row address strobe signal and the column address strobe signal. This is a semiconductor memory device with a nibble mode function that sequentially outputs data of multiple addresses, and all data output operations during the nibble mode are performed when the column address strobe signal changes from the first level to the second level. The output system internal circuit is activated at the time when the column address strobe signal changes from the first level to the second level again in the next cycle, and the output data is held. Semiconductor storage device.