JPH0513394B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A method of forming a dummy electrode outside the circuit in order to prevent contamination of the device when forming a circuit consisting of Josephson junction devices using reactive ion etching.

[Industrial application field]

The present invention relates to a manufacturing method that prevents contamination of Josephson junction devices during the formation of Josephson junction devices by reactive ion etching.

Josephson junction devices (hereinafter referred to as Josephson devices) are devices that utilize superconductivity, and their power consumption is approximately 1 μW per gate, which is three to four orders of magnitude lower than that of semiconductor devices, and the switching time is approximately 10 ps. , which are more than an order of magnitude shorter than transistors, are being used in high-speed computers.

Various devices have been put into practical use using Josephson elements.

An example of this is a superconducting quantum interference device, which has a configuration in which two or three Josephson junctions are connected in parallel via an inductance bridge.

Here, these devices are formed on a semiconductor substrate (wafer) such as silicon (Si),
As with various semiconductor devices, a large number of devices are simultaneously patterned and manufactured.

The present invention relates to a method for preventing contamination when patterning Josephson elements by photolithography.

[Conventional technology]

As shown in Figure 4, the Josephson element is made of niobium (Nb) or niobium nitride (Nb) on a substrate 1 such as Si.
There is a base electrode 2 made of a superconducting metal such as N), on which there is an interlayer insulating layer 3 made of silicon dioxide (SiO ₂ ) with a window open at the junction, and a region containing the junction is made of aluminum (Al). There is a tunnel oxide film 4 produced by oxidizing a thin film such as ), on which a counter electrode 5 made of a superconducting metal such as Nb or NbN is provided to form a Josephson element.

In a Josephson device having such a configuration, the quality of the characteristics is determined by the tunnel oxide film 4 having a thickness of several tens of angstroms or less, which must be homogeneous and free from contamination.

However, in reality, it is difficult to form a high-quality tunnel oxide film because it is easily contaminated during the patterning process.

Here, pattern formation is performed by a reactive ion etching (RIE) method, but contamination occurs during pattern formation.

Each manufacturing process of the Josephson device will be explained below.

Substrate electrode: Approximately Nb metal is applied on substrate 1 by sputtering method.
A film is formed to a thickness of 3000 Å, a resist is spin-coated, a large number of base electrode patterns are projected and exposed, and then developed to form a resist pattern.

Next, this is subjected to RIE to form a large number of substrate electrodes 2.

For example, the etching atmosphere is carbon tetrafluoride (CF ₄ ) + 30% by volume oxygen (O ₂ ).
The pressure is 80 mTorr and the power is 0.1 W/cm ² .

Interlayer insulating layer: SiO ₂ is deposited to a thickness of approximately 4000 Å over the entire area of the substrate where the substrate electrode 2 is formed by sputtering, and resist patterning is performed to form a bonding area.
Only the SiO ₂ layer is removed by RIE method.

The processing conditions in this case are, for example, trifluoromethane (CHF ₃ )+10% O ₂ , 15 mTorr, and 0.2 W/cm ² .

Tunnel oxide film: Argon (Ar) is applied to the substrate surface including substrate electrode 2.
After sputter cleaning using gas, Al
sputter to make an Al thin film of about 30 Å, and introduce O ₂ into the chamber to give a pressure of 0.01 to 1 Torr.
Leave for a minute to form a tunnel oxide film.

Counter electrode: After forming the tunnel oxide film, sputter Nb to a thickness of about 5000 Å and remove it by RIE, leaving the counter electrode after resist patterning.

Etching conditions are, for example, CF ₄ + 5% O ₂ , 50 m
Torr, 0.1W/ ^cm2 .

In this way, pattern formation is performed using the RIE method, but in RIE, sputter etching also occurs in parallel, and positive ions in the gas plasma bombard the sample placed on the cathode, causing Reactants or incomplete reactants may scatter to the surrounding area and cause contamination.

This contamination is a small amount and does not pose a problem when the etching area is small, such as when forming a bonding window after forming the interlayer insulating layer 3. When this is carried out, significant contamination occurs due to re-deposition of the scattered reactants, which poses a problem.

Specifically, when forming the base electrode 2 made of Nb by RIE, the substrate electrode 2 remaining on the resist layer on the substrate electrode pattern and after etching is
Resist reactants that have not been gasified and re-deposits such as Nb or Nb fluorides and oxides with low vapor pressure are precipitated on the shoulders of the resist, and these can be removed by resist removal treatment using a solvent such as acetone. However, it may remain on the surface and cannot be removed.

In such a case, if the tunnel oxide film 4 is formed thereon, the junction characteristics will be poor with a large amount of leakage current.

Therefore, there is a need for a pattern forming method that does not cause contamination.

[Problem that the invention seeks to solve]

As explained above, pattern formation of Josephson elements is performed by RIE, but the pattern surface formed by the deposits generated during pattern formation by sputter etching is contaminated, resulting in junctions with high leakage current. is the problem.

[Means for solving problems]

The above problem is solved by the process of providing a superconducting ground plane on the substrate, the process of providing a moat by opening a hole in the superconducting ground plane at a position surrounding the area where the Josephson gate is to be formed, and A method for manufacturing a Josephson junction element, comprising the steps of providing an electrode pattern for element formation and forming a dummy electrode so as to cover all or part of the moat portion. This can be solved by taking .

[Effect]

When forming a pattern using photoetching technology, the RIE method, which has directional etching, is most suitable for obtaining a highly accurate pattern using the dry etching method.

However, the deposition of minute amounts of reaction products due to sputter etching is unavoidable, and contamination caused by this is not allowed in the formation of Josephson junctions.

The inventors have discovered that such sputter etching contamination is also related to pattern placement.

That is, contamination is noticeable when a single element is formed in the center of a large substrate area, and when a large number of elements are formed in a matrix on a substrate, contamination appears on the elements at the outer periphery.

FIG. 3 shows this state. For example, when forming a layer of Nb as a superconducting metal on a substrate 1 made of Si and performing RIE to form a base electrode 2 in a matrix shape, the inventor As shown in Fig. 2, contaminants 6 are particularly concentrated on the shoulder part of the base electrode 2 on the outer periphery.
It was found that there is a tendency for the particles to adhere to each other.

Therefore, the present invention utilizes the adhesion of such sputtering reactants, and when making a large number of Josephson devices, a dummy electrode is provided around the sputtering reactant, and contaminants are attached to the dummy electrode to form an electrode that forms a bond. This is to prevent it from adhering to the surface.

〔Example〕

FIG. 1 shows a method of implementing the present invention, in which a dummy electrode pattern 8 is provided on the outer periphery of a large number of electrode patterns 7 for forming Josephson elements.

Here, the dummy patterns do not need to be formed in all of the element forming steps, but may be formed only in the RIE step in which electrodes are formed where adhesion of substances is undesirable.

FIG. 2 is a cross-sectional view showing an example of the method of implementing the present invention, in which Nb
Since it is a necessary condition that the surface of the base electrode 2 made of a superconducting metal such as A dummy electrode pattern 8 was formed around the periphery.

Conventionally, by adopting such a method, leakage defects occurred in elements on the outer periphery, but by implementing the present invention, uniform bonding characteristics can be obtained regardless of the pattern formation position.

Next, when implementing the present invention, it seems that the position of the dummy pattern provided on the outer periphery is uneconomical in terms of space.

In such cases, in Josephson logic circuits, a superconducting ground plane is provided on the substrate to prevent magnetic traps, the logic circuit is formed on top of this, and holes called moats are provided in the ground plane at positions surrounding the gate. ing.

Magnetic flux trap is a phenomenon in which when a circuit is cooled to an extremely low temperature, if a magnetic field is present, the magnetic field is taken into the superconducting film. The trapped magnetic field is quantized in units of magnetic flux quanta, and when it occurs near the junction, it changes the magnetic field current. In the moat, in order to prevent such an adverse magnetic flux trap from occurring near the junction, a groove that actively causes a magnetic flux trap is formed at a position surrounding the Josephson gate.

Since this moat portion is arranged so as to surround the periphery of the gate, it is economical to generate the dummy pattern according to the present invention so as to cover all or part of this moat portion.

〔Effect of the invention〕

As described above, by carrying out the present invention, it is possible to reduce bonding defects during the formation of Josephson devices and improve yield.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an example of the arrangement of dummy patterns according to the present invention, FIG. 2 is a cross-sectional view showing the method of implementing the present invention, FIG. 3 is a cross-sectional view explaining the contamination state of the pattern, and FIG. FIG. 3 is a cross-sectional structural diagram of a bonding element. In the figure, 1 is a substrate, 2 is a base electrode, 3 is an interlayer insulating layer, 4 is a tunnel oxide film, 5 is a counter electrode,
6 is a contaminant, 7 is an electrode pattern, 8 is a dummy electrode pattern, and 9 is a Josephson element.

Claims (1)

[Claims] 1. A step of providing a superconducting ground plane on a substrate, and a step of providing a moat by opening a hole in the superconducting ground plane at a position surrounding a region of the substrate where a Josephson gate is to be formed. A method for manufacturing a Josephson junction element, comprising the steps of: providing an electrode pattern for forming a Josephson element, and forming a dummy electrode so as to cover all or a part of the moat portion.