JPH0587193B2 - - Google Patents
Info
- Publication number
- JPH0587193B2 JPH0587193B2 JP1146277A JP14627789A JPH0587193B2 JP H0587193 B2 JPH0587193 B2 JP H0587193B2 JP 1146277 A JP1146277 A JP 1146277A JP 14627789 A JP14627789 A JP 14627789A JP H0587193 B2 JPH0587193 B2 JP H0587193B2
- Authority
- JP
- Japan
- Prior art keywords
- josephson junction
- lower electrode
- gas
- upper electrode
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、超伝導集積回路に用いられるジヨ
セフソン接合素子の製造方法に関するもので、特
にジヨセフソン接合を作製する際のドライエツチ
ングとして、CF4ガスでエツチングした後に、さ
らにCF4＋O2ガスでエツチングするようにしたジ
ヨセフソン接合素子の製造方法に関するものであ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a Josephson junction element used in a superconducting integrated circuit, and in particular, CF 4 gas is used as dry etching when producing a Josephson junction. The present invention relates to a method of manufacturing a Josephson junction element in which etching is performed using a CF 4 +O 2 gas after the etching is performed using a CF 4 +O 2 gas.
近年、超伝導現象を利用した論理回路は、低消
費電力で、高密度集積化に適しており、しかも非
常に高速の動作が期待されることから注目されて
いる。とりわけ、超伝導現象を利用した論理素子
としてもジヨセフソン素子は、超高速のコンピユ
ータへの応用を目指して各所で研究が行われてい
る。
In recent years, logic circuits that utilize superconductivity have attracted attention because they have low power consumption, are suitable for high-density integration, and are expected to operate at extremely high speeds. In particular, Josephson devices, which are logic elements that utilize superconductivity, are being researched in various places with the aim of applying them to ultra-high-speed computers.
従来、この種のジヨセフソン接合の製造方法と
しては、特願昭60−61244号またはAppl.Phy.
Letters.Vol.46No.11p.1098−1100が知られている。 Conventionally, methods for manufacturing this type of Josephson junction have been disclosed in Japanese Patent Application No. 60-61244 or Appl.Phys.
Letters.Vol.46No.11p.1098−1100 is known.
第２図ａ〜ｅは従来のジヨセフソン接合素子の
製造工程を示す。 2a to 2e show the manufacturing process of a conventional Josephson junction device.
第２図ａにおいて、基板１上にNbNからなる
下部電極２を形成した後、MgO，ZrO2，Al2O3
等のトンネル障壁３を形成し、さらにNbNから
なる上部電極４をそれぞれスパツタ装置を使用し
て形成してジヨセフソン接合を形成する。次い
で、第２図ｂに示すように、上部電極４の上に下
部電極用のレジストパターン５を形成し、これを
エツチングマスクとして使用して下部電極２、ト
ンネル障壁３、上部電極４をCF4のガスによりエ
ツチングした後、次いで第２図ｃに示すように上
部電極４に接合部用のレジストパターン６を形成
し、上部電極４とトンネル障壁３とをエツチング
した後、第２図ｄに示すように、レジストパター
ン６を除去し、絶縁膜７を堆積し、リフトオフ法
により上部電極４の部分の絶縁膜７を除去し、第
２図ｅに示すように、スパツタ装置を用いて配線
用のNb膜を堆積し、さらに配線用のレジストパ
ターン（図示せず）を形成してからCF4ガスによ
りエツチングして配線部８を形成する。 In FIG. 2a, after forming the lower electrode 2 made of NbN on the substrate 1, MgO, ZrO 2 , Al 2 O 3
A tunnel barrier 3 such as the above is formed, and an upper electrode 4 made of NbN is formed using a sputtering device to form a Josephson junction. Next, as shown in FIG. 2b, a resist pattern 5 for the lower electrode is formed on the upper electrode 4, and using this as an etching mask, the lower electrode 2, tunnel barrier 3, and upper electrode 4 are etched with CF4. Then, as shown in FIG. 2c, a resist pattern 6 for a junction is formed on the upper electrode 4, and after etching the upper electrode 4 and the tunnel barrier 3, a resist pattern 6 is formed as shown in FIG. 2d. As shown in FIG. A Nb film is deposited, a resist pattern for wiring (not shown) is formed, and then etched with CF 4 gas to form the wiring portion 8 .
〔発明が解決しようとする課題〕
しかしながら、上記の従来のジヨセフソン接合
素子の製造方法においては、ジヨセフソン接合が
完成した後に下部電極２の周辺に当たる場所に第
２図ｅに示すように、配線部８の断線の原因にな
る突起物９が生じるという問題点があつた。[Problem to be Solved by the Invention] However, in the above-described conventional method for manufacturing a Josephson junction element, after the Josephson junction is completed, a wiring portion 8 is formed around the lower electrode 2, as shown in FIG. 2e. There was a problem in that protrusions 9 were formed which caused wire breakage.
この突起物９が生じる原因を調べた結果、上部
電極４とトンネル障壁３をエツチングしたとき
に、下部電極２の周辺に黒色の堆積物１０が生じ
る現象のあることが分かつた。また、この突起物
９の影響は、配線部８および絶縁膜７の厚さを厚
くすれば避けることができるが、これは絶縁膜７
のストレスの増大を招き、また、配線部８のイン
ピーダンスを高くすることにもなり、好ましくな
い。したがつて、この突起物９を発生させないた
めの根本的な解決策が望まれていた。 As a result of investigating the cause of this protrusion 9, it was found that when the upper electrode 4 and tunnel barrier 3 are etched, there is a phenomenon in which black deposits 10 are formed around the lower electrode 2. Further, the influence of this protrusion 9 can be avoided by increasing the thickness of the wiring portion 8 and the insulating film 7;
This is undesirable because it causes an increase in stress and also increases the impedance of the wiring section 8. Therefore, a fundamental solution to prevent the protrusions 9 from occurring has been desired.
この発明は、上記の問題点を解決するためにな
されたもので、ジヨセフソン接合素子を製造する
際に下部電極の周辺に生じた黒色の炭素重合物と
思われる堆積物を除去することにより、完成した
ジヨセフソン接合に現れる突起物の生成を抑える
ようにしたジヨセフソン接合素子の製造方法を得
ることを目的とする。 This invention was made to solve the above-mentioned problems, and by removing the deposits that appear to be black carbon polymers that appeared around the lower electrode during the manufacture of Josephson junction devices, the device was completed. An object of the present invention is to provide a method for manufacturing a Josephson junction element that suppresses the formation of protrusions that appear in a Josephson junction.
この発明に係るジヨセフソン接合素子の製造方
法は、それぞれ超伝導体からなる下部電極と上部
電極との間にトンネル障壁を挟んでジヨセフソン
接合を形成し、上部電極上に接合部用のマスクを
形成した後、CF4ガスを用いて上部電極とトンネ
ル障壁のエツチングを行い、次いで、CF4ガスの
エツチングにより下部電極の周辺に発生した堆積
物を、CF4＋O2ガスでさらにエツチングして堆積
物を除去するものである。
A method for manufacturing a Josephson junction element according to the present invention includes forming a Josephson junction by sandwiching a tunnel barrier between a lower electrode and an upper electrode each made of a superconductor, and forming a mask for the junction on the upper electrode. After that, the upper electrode and tunnel barrier are etched using CF 4 gas, and then the deposits generated around the lower electrode due to CF 4 etching are further etched using CF 4 +O 2 gas to remove the deposits. It is to be removed.
この発明においては、ジヨセフソン接合素子を
製造するとき、CF4ガスでエツチングした後に、
下部電極の周辺に生じる黒色の堆積物をCF4＋O2
ガスでさらにエツチングすることにより除去し、
下部電極の上面を平坦にし、配線に悪影響を与え
る突起物の生成を阻止する。
In this invention, when manufacturing Josephson junction elements, after etching with CF 4 gas,
Remove the black deposits that occur around the lower electrode with CF 4 +O 2
removed by further etching with gas,
The upper surface of the lower electrode is made flat to prevent the formation of protrusions that adversely affect wiring.
第１図ａ〜ｅはこの発明の一実施例を示す工程
図で、第２図と同一符号は同一部分を示し、かつ
第１図ａ，ｂの工程は第２図ａ，ｂと同一の工程
であるので説明は省略する。次いで、第２図ｃに
示すように、CF4ガスにより上部電極４と、トン
ネル障壁３とを従来と同様に除去した後、さらに
CF4＋O2ガスを使用してエツチングを行い、従来
の第２図ｅで説明した下部電極２の周辺に発生し
た堆積物１０を除去する。以下、第１図ｄ，ｅの
工程も第２図ｄ，ｅと同一であるため、その説明
を省略する。
Figures 1 a to e are process diagrams showing one embodiment of the present invention, in which the same reference numerals as in Figure 2 indicate the same parts, and the steps in Figure 1 a and b are the same as in Figure 2 a and b. Since this is a process, the explanation will be omitted. Next, as shown in FIG. 2c, after removing the upper electrode 4 and the tunnel barrier 3 with CF 4 gas in the same manner as before, further steps are performed.
Etching is performed using CF 4 +O 2 gas to remove the deposit 10 generated around the lower electrode 2 as described in the prior art with reference to FIG. 2e. Hereinafter, since the steps d and e in FIG. 1 are the same as those in FIG. 2 d and e, their explanation will be omitted.
以上説明したように、この発明は、それぞれ超
伝導体からなる下部電極と上部電極との間にトン
ネル障壁を挟んでジヨセフソン接合を形成し、上
部電極上に接合部用のマスクを形成した後、CF4
ガスを用いて上部電極とトンネル障壁のエツチン
グを行い、次いで、CF4ガスのエツチングにより
下部電極の周辺に発生した堆積物を、CF4＋O2ガ
スを用いてエツチングにより除去するようにした
ので、トンネル障壁にMgO，ZrO2，Al2O3など
の絶縁材料を用いたジヨセフソン接合を有するジ
ヨセフソン素子を製造する場合に、従来生じてい
た下部電極周辺の突起物の生成を阻止することが
できるため、超伝導集積回路の製造において、そ
の製造歩留りと品質とを飛躍的に向上させること
ができる利点を有する。
As explained above, in the present invention, a Josephson junction is formed by sandwiching a tunnel barrier between a lower electrode and an upper electrode each made of a superconductor, and a mask for the junction is formed on the upper electrode. CF4
The upper electrode and tunnel barrier were etched using gas, and then the deposits generated around the lower electrode due to etching with CF 4 gas were removed by etching using CF 4 +O 2 gas. When manufacturing a Josephson device with a Josephson junction using an insulating material such as MgO, ZrO 2 , Al 2 O 3 for the tunnel barrier, it is possible to prevent the formation of protrusions around the lower electrode that conventionally occur. , has the advantage of dramatically improving manufacturing yield and quality in the manufacturing of superconducting integrated circuits.
第１図ａ〜ｅはこの発明の一実施例を示す工程
図、第２図ａ〜ｅは従来のジヨセフソン接合素子
を形成する工程を示す図である。
図中、１は基板、２は下部電極、３はトンネル
障壁、４は上部電極、５，６は下部電極用、接合
部用のレジストパターン、７は絶縁膜、８は配線
部である。
1A to 1E are process diagrams showing one embodiment of the present invention, and FIGS. 2A to 2E are diagrams showing the process of forming a conventional Josephson junction element. In the figure, 1 is a substrate, 2 is a lower electrode, 3 is a tunnel barrier, 4 is an upper electrode, 5 and 6 are resist patterns for the lower electrode and a bonding part, 7 is an insulating film, and 8 is a wiring part.
Claims (1)
極との間にトンネル障壁を挟んでジヨセフソン接
合を形成し、前記上部電極上に接合部用のマスク
を形成した後、CF4ガスを用いて前記上部電極と
前記トンネル障壁のエツチングを行い、次いで、
前記エツチングにより前記下部電極の周辺に発生
した堆積物を、CF4＋O2ガスを用いてエツチング
により除去する工程を含むことを特徴とするジヨ
セフソン接合素子の製造方法。1 A Josephson junction is formed by sandwiching a tunnel barrier between a lower electrode and an upper electrode, each made of a superconductor, and a mask for the junction is formed on the upper electrode, and then the upper electrode is formed using CF 4 gas. Etching the electrode and the tunnel barrier, then
A method for manufacturing a Josephson junction element, comprising the step of removing deposits generated around the lower electrode by etching using CF 4 +O 2 gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1146277A JPH0311675A (en) | 1989-06-08 | 1989-06-08 | Manufacture of josephson junction element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1146277A JPH0311675A (en) | 1989-06-08 | 1989-06-08 | Manufacture of josephson junction element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0311675A JPH0311675A (en) | 1991-01-18 |
| JPH0587193B2 true JPH0587193B2 (en) | 1993-12-15 |
Family
ID=15404088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1146277A Granted JPH0311675A (en) | 1989-06-08 | 1989-06-08 | Manufacture of josephson junction element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0311675A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58154280A (en) * | 1982-03-10 | 1983-09-13 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of tunnel type josephson element |
| JPS6279684A (en) * | 1985-10-02 | 1987-04-13 | Agency Of Ind Science & Technol | Josephson integrated circuit manufacturing method |
-
1989
- 1989-06-08 JP JP1146277A patent/JPH0311675A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0311675A (en) | 1991-01-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |