JPH0513539B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that employs a tape-automated bonding (TAB) type mounting structure for mounting high-speed ICs.

[Conventional technology]

In recent years, planar type transistors on semi-insulating GaAs substrates have been used as high-performance transistors in the microwave band.
MESFETs, GaAsFETs with a modulation doped structure, and HBTs with a heterojunction structure are attracting attention, and efforts are being made to make them monolithic and to achieve higher frequencies.

For example, a circuit formed on such a GaAs substrate includes a GaAs monolithic FET amplifier, and the structure thereof will be explained below with reference to the drawings.

3a to 3c are a plan view, an equivalent circuit diagram, and a mount side view of a semiconductor chip of a GaAs monolithic FET amplifier, respectively, for explaining an example of such a conventional device. Here, a case will be described in which a matching circuit consisting of a series inductor and a parallel capacitor is formed only in the input section.

As shown in FIG. 3a, a source electrode 42 and a drain electrode 43 made of an ohmic metal such as AuGeNi and a gate made of a short metal such as WSi are formed on a GaAs wafer 41 in which n-type impurities are ion-implanted onto a semi-insulating substrate. An input matching circuit is formed of an FET consisting of an electrode 44, an inductor 45 with a metal pattern connected in series to the gate electrode 44, and a capacitor 46 with a comb-shaped metal pattern connected in parallel from its input terminal side. death,
50 chips including GaAs monolithic FET amplifier
is configured. Note that each electrode of the FET amplifier constituting the chip 50 is provided with a terminal, and the source electrode 42 is provided with a ground terminal 47.
An input terminal 48 is formed in the input matching circuit connected to the gate electrode 44, and an output terminal 49 is formed in the drain electrode 43. Further, 51 to 53 each indicate bonding wires.

Figure 3b shows the equivalent circuit of the GaAs monolithic FET amplifier mentioned above, and Figure 3c shows the equivalent circuit of Figure 3a.
This figure shows a side view of an example in which the amplifier shown in Figure 1 is mounted in an actual package.

As shown in Figure 3c, the attachment to the package cage is
Chip 50 on Au plated heat sink 54
a dielectric material 55, on which a metal is vapor-deposited on the lower surface and an electrode pattern for bonding is formed on the upper surface.
56 and the heat sink 54, a ground terminal 47, an input terminal 48, and an output terminal 49 made of the metal pattern shown in FIG.
This is done by connecting through 52 and 53. As a result, high frequency signals are input/output processed through the electrode patterns 57 and 58, which serve as input/output terminals.

On the other hand, as another conventional example, a flip-chip type GaAs monolithic FET amplifier can be considered. This is an IC chip in which bumps of several tens of micrometers are formed on part of the signal electrodes and power supply electrodes, and then mounted onto a package made of the same dielectric material as above, with the amplifier circuit section facing down.

[Problem that the invention seeks to solve]

In the conventional GaAs monolithic FET amplifier described above, as can be seen from the equivalent circuit diagram in Figure 3b, the input impedance of the monolithic FET amplifier is matched to a predetermined resistance (50Ω) by an input matching circuit. Therefore, the input/output terminals must be directly connected to a transmission line whose characteristic impedance is a predetermined resistance (50Ω). However, as can be seen from FIGS.
8, 49 and bonding wires 51, 52, it is inevitable that the parasitic inductance of the bonding wires will be added. This parasitic inductance has a disadvantage in that it is definitely disadvantageous in terms of characteristics when obtaining a device that operates at a very high frequency.

For example, to give an example of the parasitic inductance of a bonding wire, the diameter of the bonding wire is 20 μm and the length is 1 mm.
When bonding is done at a position of 0.15mm, the parasitic inductance is 1nH/mm.

In addition, in the flip-chip type GaAs monolithic FET amplifier described above, a bump several tens of micrometers thick formed on the IC chip and a part of the electrode formed by Au plating is arranged and bonded to the electrode pattern for bonding on the upper surface. However, the drawback is that it is not possible to check whether the electrode pattern and the bumps on the IC chip are connected due to the structure of the FET.

An object of the present invention is to provide a semiconductor device in which the parasitic inductance of such a bonding wire can be reduced and connection of electrode patterns can be easily confirmed.

[Means for solving problems]

The present invention provides a semiconductor chip having a plurality of metal electrode portions protruding from its main surface, and a semiconductor chip that is arranged and coupled to the metal electrode portions of the semiconductor chip in a specific positional relationship.
In a semiconductor device having a TAB-shaped lead metal, the entire lower surface has metal and the upper surface has metal.
The semiconductor chip is placed with its main surface facing down on a dielectric material having a metal pattern that is arranged and coupled to a TAB-shaped lead metal, and the TAB-shaped lead metal has a predetermined characteristic impedance as a distributed constant line. The ratio of the width of the TAB-shaped lead metal to the thickness of the dielectric is set to a specific value according to the dielectric constant of the dielectric.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1A to 1C are a plan view, an equivalent circuit diagram, and a mount side view of a semiconductor chip of a GaAs monolithic FET amplifier, respectively, for explaining a first embodiment of the present invention. In particular, in Figure 1a,
This shows a GaAs monolithic FET amplifier in which a matching circuit consisting of a series inductance and a parallel capacitor is formed only at the input section.

As shown in FIG. 1a, on a GaAs wafer 1 in which n-type impurities are ion-implanted onto a semi-insulating substrate,
A FET consisting of a source electrode 2 and a drain electrode 3 made of ohmic metal such as AuGeNi, and a gate electrode 4 made of a short metal such as WSi, a metal pattern 5 having an inductance component connected in series to the gate electrode 4, and an input terminal. An input matching circuit composed of capacitors 6 connected in parallel nearby is formed. In addition, the input/output terminals 8, 9 must be directly connected to a transmission line with a characteristic impedance of 50Ω, but parts 12, 13 of these input/output terminals 8, 9 and a part 11 of the ground terminal 7 are plated with Au, etc. From 15μm
A bump 15 with a thickness of 20 μm is formed. These bumps, the FET, and the input matching circuit constitute a monolithic FET amplifier chip 10.

Figure 1b shows a GaAs monolith as described above.
This is an equivalent circuit diagram of a FET amplifier, and is similar to the equivalent circuit shown in FIG. 3b.

Next, as shown in FIG. 1c, TAB bonding is performed on the chip 10 of this monolithic FET amplifier. Next, a metal 19 is deposited on the entire lower surface, and an electrode pattern 17 is formed on the upper surface at a specific position so as to be arranged and connected to the lead metal 16 of the TAB.
The TAB bonded monolithic FET amplifier chip 10 is mounted on a dielectric 18 having a
is placed with the main surface on which the amplifier circuit 14 is formed facing down. Furthermore, the relative permittivity of the dielectric material 18 is adjusted so that the lead metal 16 of the TAB has a characteristic impedance of 50Ω as a distributed constant line.
The ratio between the width W of the lead metal 16 of the TAB and the thickness H of the dielectric 18 is set. In addition, when alumina ceramic is used as the dielectric material, and assuming that the dielectric constant of alumina ceramic is 9, the ratio W/H of the width W of the TAB lead metal and the thickness H of the dielectric material is W/H=1.
It is. In this way GaAs monolithic FET
The amplifier is configured and the input/output terminals 8 and 9 of the mount
A high frequency signal is processed from the electrode pattern 17 connected to.

Although the above embodiment has been described with respect to a GaAs monolithic FET amplifier, it can be similarly applied to an MMIC circuit having a high-speed bipolar transistor, a GaAs FET having a modulation doped structure formed on a GaAs substrate, and an HBT circuit having a heterojunction structure. .

FIGS. 2a and 2b are a block diagram of an ultra-high-speed operating digital LSI chip and a side view of the mount of the chip, respectively, for explaining a second embodiment of the present invention.

As shown in FIG. 2a, this LSI chip mainly includes an input terminal electrode 21 to which an input signal is applied, an input buffer 23 that converts the input signal level to an internal logic level, a logic function block 24 that digitally processes the logic of the input signal, Output buffer 2 that converts the output logic from internal logic level to external logic level
5, and an output terminal electrode 27 for extracting its output level. Parts 22 and 26 of the input/output terminal electrodes 21 and 27 are bumps with a thickness of 15 to 20 μm formed by Au plating.

Next, as shown in FIG. 2b, TAB bonding is performed on this LSI chip. Next, the LSI chip is placed with the surface on which the logic circuit 29 of the LSI chip is formed facing down on a package consisting of a dielectric material 33 on which a metal 34 is vapor-deposited on the lower surface and an electrode pattern 32 for bonding is formed on the upper surface. Further, the ratio between the width W of the lead metal and the thickness H of the dielectric is set according to the dielectric constant of the dielectric so that the lead metal 31 of the TAB has a characteristic impedance of 50Ω as a distributed constant line. This allows direct connection from the input/output terminal electrodes.
It is connected to a transmission line with a characteristic impedance of 50Ω, reducing parasitic inductance caused by conventional bonding wires.

〔Effect of the invention〕

As explained above, the present invention forms bumps on part of the signal electrode and power supply electrode of an IC chip.
A chip that has been subjected to TAB bonding is placed on a dielectric material that has a metal vapor-deposited on the bottom surface and an electrode bonded to the TAB lead metal on the top surface.
By setting the ratio of the TAB lead metal width and dielectric thickness according to the relative dielectric constant of the dielectric so that the TAB lead metal has a specific impedance, the characteristic impedance of the distributed constant line can be bonded. This has the effect of reducing parasitic inductance. In other words, the size of the bump formed on the IC chip is 100μm x 100μm, and the height is 20μm.
The parasitic inductance in this case can be made sufficiently smaller than the parasitic inductance of the bonding wire.

In addition, in flip-chip ICs, once
Since TAB bonding is performed, it is possible to confirm the connection between the bump part and the electrode pattern.

[Brief explanation of the drawing]

Figures 1a to 1c are a plan view, an equivalent circuit diagram, and a side view of a semiconductor chip mount of a GaAs monolithic FET amplifier for explaining the first embodiment of the present invention, respectively, and Figures 2a and 2b are each a diagram of the present invention. A block configuration diagram of a digital LSI chip for explaining a second embodiment of the present invention, a side view of the mount of the chip, and a plan view of a GaAs monolithic FET amplifier for explaining a conventional example, respectively. FIG. 2 is an equivalent circuit diagram and a side view of a semiconductor chip mount. 1...GaAs wafer, 2...GaAsFET source electrode, 3...GaAsFET drain electrode, 4...
...Gate electrode of GaAsFET, 5...Inductor,
6...Capacitor, 7...Ground terminal, 8...
Input terminal, 9...Output terminal, 10...GaAs monolithic FET amplifier (chip), 11, 12, 1
3... Bump, 14... Amplifier circuit, 15... Bump, 16... TAB lead electrode, 17... Electrode pattern, 18... Dielectric, 19... Vapor deposited metal, 21... Input terminal electrode, 22 ...Bump, 2
3...Input buffer, 24...Logic function block, 25...Output buffer, 26...Bump, 2
7...Output terminal electrode, 28...Digital LSI chip, 29...Logic circuit, 30...Bump, 31
...TAB lead electrode, 32...electrode pattern,
33...Dielectric material, 34... Vapor deposited metal.

Claims (1)

[Claims] 1. A semiconductor chip having a plurality of metal electrode parts protruding from the main surface, and a TAB arranged and coupled to the metal electrode parts of the semiconductor chip in a specific positional relationship.
In a semiconductor device having a lead metal of
The semiconductor chip is placed with its main surface facing down on a dielectric material that has metal on the entire lower surface and has a metal pattern on the upper surface that is arranged and coupled to the TAB-shaped lead metal, and The ratio of the width of the TAB-shaped lead metal to the thickness of the dielectric is set to a specific value according to the dielectric constant of the dielectric so that the lead metal has a predetermined characteristic impedance as a distributed constant line. A semiconductor device characterized by: